From 6489598fb449531c34bfb25a52189196ee2b1086 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 2 Dec 2014 06:08:25 -0500 Subject: stats: Bump stats for fixes, mostly TLB and WriteInvalidate --- .../arm/linux/realview64-simple-timing/stats.txt | 2317 ++++++++++---------- 1 file changed, 1173 insertions(+), 1144 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt') diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index c88d045b6..e087cdc41 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,140 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.781056 # Number of seconds simulated -sim_ticks 51781056074000 # Number of ticks simulated -final_tick 51781056074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821204 # Number of seconds simulated +sim_ticks 51821203872000 # Number of ticks simulated +final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717486 # Simulator instruction rate (inst/s) -host_op_rate 843154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44175728553 # Simulator tick rate (ticks/s) -host_mem_usage 650840 # Number of bytes of host memory used -host_seconds 1172.16 # Real time elapsed on the host -sim_insts 841009423 # Number of instructions simulated -sim_ops 988312418 # Number of ops (including micro ops) simulated +host_inst_rate 797175 # Simulator instruction rate (inst/s) +host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46008450754 # Simulator tick rate (ticks/s) +host_mem_usage 656028 # Number of bytes of host memory used +host_seconds 1126.34 # Real time elapsed on the host +sim_insts 897890420 # Number of instructions simulated +sim_ops 1055061464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 385216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 437760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 790272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4324596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 53060296 # Number of bytes read from this memory -system.physmem.bytes_read::total 58998140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4324596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4324596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 30687936 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 99485540 # Number of bytes written to this memory -system.physmem.bytes_written::total 136999972 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 6840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 12348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 107979 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 829080 # Number of read requests responded to by this memory -system.physmem.num_reads::total 962266 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 479499 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 1556713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2142876 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 7439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 8454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 15262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 83517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1024705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1139377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 83517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 83517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 592648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 131834 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1921273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2645755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 592648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 139273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 15262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 83517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2945978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3785132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 962266 # Number of read requests accepted -system.physmem.writeReqs 2142876 # Number of write requests accepted -system.physmem.readBursts 962266 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2142876 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61369728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 215296 # Total number of bytes read from write queue -system.physmem.bytesWritten 132432768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58998140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136999972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 3364 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 73592 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 33443 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65026 # Per bank write bursts -system.physmem.perBankRdBursts::1 59757 # Per bank write bursts -system.physmem.perBankRdBursts::2 57697 # Per bank write bursts -system.physmem.perBankRdBursts::3 55201 # Per bank write bursts -system.physmem.perBankRdBursts::4 59686 # Per bank write bursts -system.physmem.perBankRdBursts::5 66424 # Per bank write bursts -system.physmem.perBankRdBursts::6 54909 # Per bank write bursts -system.physmem.perBankRdBursts::7 46752 # Per bank write bursts -system.physmem.perBankRdBursts::8 56185 # Per bank write bursts -system.physmem.perBankRdBursts::9 105428 # Per bank write bursts -system.physmem.perBankRdBursts::10 56738 # Per bank write bursts -system.physmem.perBankRdBursts::11 56925 # Per bank write bursts -system.physmem.perBankRdBursts::12 52656 # Per bank write bursts -system.physmem.perBankRdBursts::13 52461 # Per bank write bursts -system.physmem.perBankRdBursts::14 54958 # Per bank write bursts -system.physmem.perBankRdBursts::15 58099 # Per bank write bursts -system.physmem.perBankWrBursts::0 127089 # Per bank write bursts -system.physmem.perBankWrBursts::1 113639 # Per bank write bursts -system.physmem.perBankWrBursts::2 227284 # Per bank write bursts -system.physmem.perBankWrBursts::3 120346 # Per bank write bursts -system.physmem.perBankWrBursts::4 128596 # Per bank write bursts -system.physmem.perBankWrBursts::5 124885 # Per bank write bursts -system.physmem.perBankWrBursts::6 105979 # Per bank write bursts -system.physmem.perBankWrBursts::7 88244 # Per bank write bursts -system.physmem.perBankWrBursts::8 113178 # Per bank write bursts -system.physmem.perBankWrBursts::9 146103 # Per bank write bursts -system.physmem.perBankWrBursts::10 105873 # Per bank write bursts -system.physmem.perBankWrBursts::11 119118 # Per bank write bursts -system.physmem.perBankWrBursts::12 106014 # Per bank write bursts -system.physmem.perBankWrBursts::13 144894 # Per bank write bursts -system.physmem.perBankWrBursts::14 168059 # Per bank write bursts -system.physmem.perBankWrBursts::15 129961 # Per bank write bursts +system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory +system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959683 # Number of read requests accepted +system.physmem.writeReqs 1860672 # Number of write requests accepted +system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue +system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56975 # Per bank write bursts +system.physmem.perBankRdBursts::1 58359 # Per bank write bursts +system.physmem.perBankRdBursts::2 58716 # Per bank write bursts +system.physmem.perBankRdBursts::3 57264 # Per bank write bursts +system.physmem.perBankRdBursts::4 61545 # Per bank write bursts +system.physmem.perBankRdBursts::5 66145 # Per bank write bursts +system.physmem.perBankRdBursts::6 57228 # Per bank write bursts +system.physmem.perBankRdBursts::7 52937 # Per bank write bursts +system.physmem.perBankRdBursts::8 52189 # Per bank write bursts +system.physmem.perBankRdBursts::9 99547 # Per bank write bursts +system.physmem.perBankRdBursts::10 57680 # Per bank write bursts +system.physmem.perBankRdBursts::11 61393 # Per bank write bursts +system.physmem.perBankRdBursts::12 54506 # Per bank write bursts +system.physmem.perBankRdBursts::13 60286 # Per bank write bursts +system.physmem.perBankRdBursts::14 51564 # Per bank write bursts +system.physmem.perBankRdBursts::15 52667 # Per bank write bursts +system.physmem.perBankWrBursts::0 114739 # Per bank write bursts +system.physmem.perBankWrBursts::1 115397 # Per bank write bursts +system.physmem.perBankWrBursts::2 117633 # Per bank write bursts +system.physmem.perBankWrBursts::3 119136 # Per bank write bursts +system.physmem.perBankWrBursts::4 120318 # Per bank write bursts +system.physmem.perBankWrBursts::5 121968 # Per bank write bursts +system.physmem.perBankWrBursts::6 116613 # Per bank write bursts +system.physmem.perBankWrBursts::7 113695 # Per bank write bursts +system.physmem.perBankWrBursts::8 109286 # Per bank write bursts +system.physmem.perBankWrBursts::9 116370 # Per bank write bursts +system.physmem.perBankWrBursts::10 115629 # Per bank write bursts +system.physmem.perBankWrBursts::11 118249 # Per bank write bursts +system.physmem.perBankWrBursts::12 111968 # Per bank write bursts +system.physmem.perBankWrBursts::13 117797 # Per bank write bursts +system.physmem.perBankWrBursts::14 110347 # Per bank write bursts +system.physmem.perBankWrBursts::15 113912 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 51781053518000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 51821201316000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 577071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.837219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.071808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 364.354794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 225600 39.09% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 129681 22.47% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48337 8.38% 69.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25344 4.39% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16032 2.78% 77.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12773 2.21% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9903 1.72% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10527 1.82% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 98874 17.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 577071 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 103651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.251131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 174.136795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 103646 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 103651 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 103651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.963744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.612401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.068688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 47209 45.55% 45.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51400 49.59% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1703 1.64% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1371 1.32% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 882 0.85% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 145 0.14% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 167 0.16% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 75 0.07% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 86 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.01% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.01% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 393 0.38% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 40 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 32 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 31 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 103651 # Writes before turning the bus around for reads -system.physmem.totQLat 10497513500 # Total ticks spent queuing -system.physmem.totMemAccLat 28476926000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4794510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10947.43 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads +system.physmem.totQLat 12714966775 # Total ticks spent queuing +system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29697.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 723659 # Number of row buffer hits during reads -system.physmem.writeRowHits 1727431 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 16675905.17 # Average gap between requests -system.physmem.pageHitRate 80.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49473510377000 # Time in different power states -system.physmem.memoryStateTime::REF 1729083200000 # Time in different power states +system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing +system.physmem.readRowHits 722338 # Number of row buffer hits during reads +system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes +system.physmem.avgGap 18373999.48 # Average gap between requests +system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states +system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 578461163500 # Time in different power states +system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2226745080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2135911680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1214989875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1165428000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3630494400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3848871000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6713681760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6695136000 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3382086739200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3382086739200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1381227557085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1374892031880 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29857029495750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29862586974000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34634129703150 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34633411091760 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.857174 # Core power per rank (mW) -system.physmem.averagePower::1 668.843296 # Core power per rank (mW) +system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.686370 # Core power per rank (mW) +system.physmem.averagePower::1 668.663363 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -330,191 +326,12 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 445419 # Transaction distribution -system.membus.trans_dist::ReadResp 445419 # Transaction distribution -system.membus.trans_dist::WriteReq 33871 # Transaction distribution -system.membus.trans_dist::WriteResp 33871 # Transaction distribution -system.membus.trans_dist::Writeback 479499 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1660804 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1660804 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33447 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33449 # Transaction distribution -system.membus.trans_dist::ReadExReq 553497 # Transaction distribution -system.membus.trans_dist::ReadExResp 553497 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5572311 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5702495 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 228222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5930717 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 188786400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 188956724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7211712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 196168436 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2862 # Total snoops (count) -system.membus.snoop_fanout::samples 3095773 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3095773 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3095773 # Request fanout histogram -system.membus.reqLayer0.occupancy 106099500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5682499 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21134514240 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 11065598028 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599963 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40401 # Transaction distribution -system.iobus.trans_dist::ReadResp 40401 # Transaction distribution -system.iobus.trans_dist::WriteReq 136730 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334424 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334424 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492830 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981107027 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179038037 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -539,25 +356,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 158219223 # DTB read hits -system.cpu.dtb.read_misses 140465 # DTB read misses -system.cpu.dtb.write_hits 143634632 # DTB write hits -system.cpu.dtb.write_misses 49220 # DTB write misses +system.cpu.dtb.read_hits 168646043 # DTB read hits +system.cpu.dtb.read_misses 158497 # DTB read misses +system.cpu.dtb.write_hits 153371607 # DTB write hits +system.cpu.dtb.write_misses 56347 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71391 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7071 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18891 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 158359688 # DTB read accesses -system.cpu.dtb.write_accesses 143683852 # DTB write accesses +system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168804540 # DTB read accesses +system.cpu.dtb.write_accesses 153427954 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 301853855 # DTB hits -system.cpu.dtb.misses 189685 # DTB misses -system.cpu.dtb.accesses 302043540 # DTB accesses +system.cpu.dtb.hits 322017650 # DTB hits +system.cpu.dtb.misses 214844 # DTB misses +system.cpu.dtb.accesses 322232494 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -579,142 +396,348 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 841528845 # ITB inst hits -system.cpu.itb.inst_misses 119634 # ITB inst misses +system.cpu.itb.inst_hits 898442559 # ITB inst hits +system.cpu.itb.inst_misses 123457 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 51154 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 841648479 # ITB inst accesses -system.cpu.itb.hits 841528845 # DTB hits -system.cpu.itb.misses 119634 # DTB misses -system.cpu.itb.accesses 841648479 # DTB accesses -system.cpu.numCycles 103562112148 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898566016 # ITB inst accesses +system.cpu.itb.hits 898442559 # DTB hits +system.cpu.itb.misses 123457 # DTB misses +system.cpu.itb.accesses 898566016 # DTB accesses +system.cpu.numCycles 103642407744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 841009423 # Number of instructions committed -system.cpu.committedOps 988312418 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 908272324 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899019 # Number of float alu accesses -system.cpu.num_func_calls 50313277 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 127741607 # number of instructions that are conditional controls -system.cpu.num_int_insts 908272324 # number of integer instructions -system.cpu.num_fp_insts 899019 # number of float instructions -system.cpu.num_int_register_reads 1317064952 # number of times the integer registers were read -system.cpu.num_int_register_writes 720072212 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450897 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759632 # number of times the floating registers were written -system.cpu.num_cc_register_reads 218662872 # number of times the CC registers were read -system.cpu.num_cc_register_writes 218058310 # number of times the CC registers were written -system.cpu.num_mem_refs 301832909 # number of memory refs -system.cpu.num_load_insts 158209551 # Number of load instructions -system.cpu.num_store_insts 143623358 # Number of store instructions -system.cpu.num_idle_cycles 100527171614.894058 # Number of idle cycles -system.cpu.num_busy_cycles 3034940533.105942 # Number of busy cycles -system.cpu.not_idle_fraction 0.029306 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970694 # Percentage of idle cycles -system.cpu.Branches 187669847 # Number of branches fetched +system.cpu.committedInsts 897890420 # Number of instructions committed +system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses +system.cpu.num_func_calls 53165114 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls +system.cpu.num_int_insts 968615704 # number of integer instructions +system.cpu.num_fp_insts 900077 # number of float instructions +system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read +system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written +system.cpu.num_mem_refs 322001322 # number of memory refs +system.cpu.num_load_insts 168639088 # Number of load instructions +system.cpu.num_store_insts 153362234 # Number of store instructions +system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles +system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969412 # Percentage of idle cycles +system.cpu.Branches 200577010 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 684692132 69.24% 69.24% # Class of executed instruction -system.cpu.op_class::IntMult 2140683 0.22% 69.46% # Class of executed instruction -system.cpu.op_class::IntDiv 96951 0.01% 69.47% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 112246 0.01% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::MemRead 158209551 16.00% 85.48% # Class of executed instruction -system.cpu.op_class::MemWrite 143623358 14.52% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 988874964 # Class of executed instruction +system.cpu.op_class::total 1055656727 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16062 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 13492469 # number of replacements -system.cpu.icache.tags.tagsinuse 511.894753 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 828035859 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13492981 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 61.367896 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31319075250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.894753 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999794 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10282368 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits +system.cpu.dcache.overall_hits::total 303464910 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses +system.cpu.dcache.overall_misses::total 8890915 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015138 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767453 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.767453 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.785363 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.785363 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076531 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076531 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024403 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7918344 # number of writebacks +system.cpu.dcache.writebacks::total 7918344 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7198 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7198 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21104 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21104 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70788 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70788 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 28302 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 28302 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 28302 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 28302 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5336889 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5336889 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2215562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2215562 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308413 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1308413 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1231947 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1231947 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 235707 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 235707 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7552451 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7552451 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8860864 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8860864 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72465482990 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72465482990 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59129774715 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59129774715 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19473134500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19473134500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25050592494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25050592494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2902318500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2902318500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 243499 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 243499 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 131595257705 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014996 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014996 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.785363 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.785363 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058856 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058856 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 855021831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 855021831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 828035859 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 828035859 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 828035859 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 828035859 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 828035859 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65835.195983 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61238.551820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59650.507352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59881.575604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65835.195983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61238.551820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59650.507352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59881.575604 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1031,312 +1067,203 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1216524124 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1216524124 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148096939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148096939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 136359357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 136359357 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 375583 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 375583 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2016394 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2016394 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1154103 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1154103 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 288962 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 288962 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6919158 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6919158 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8073261 # number of overall misses -system.cpu.dcache.overall_misses::total 8073261 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76779469503 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76779469503 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60928492192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60928492192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4073605250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4073605250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137707961695 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137707961695 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137707961695 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137707961695 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 152999703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 152999703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 138375751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 138375751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1529686 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1529686 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1554140 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1554140 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3656069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3656069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3654439 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3654439 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291375454 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291375454 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292905140 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292905140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014572 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014572 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754471 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.754471 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023747 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023747 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15660.445721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15660.445721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30216.560946 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30216.560946 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14097.373530 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14097.373530 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19902.416117 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19902.416117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17057.290938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17057.290938 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1554140 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 6407423 # number of writebacks -system.cpu.dcache.writebacks::total 6407423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5098 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5098 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21192 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21192 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69202 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69202 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 26290 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 26290 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 26290 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 26290 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4897666 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4897666 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1995202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1995202 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1152860 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1152860 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 219760 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 219760 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 6892868 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 6892868 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8045728 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8045728 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66593476247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 66593476247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56238194808 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 56238194808 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 17420344250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 17420344250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 50499536991 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 50499536991 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2639848250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2639848250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 122831671055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 122831671055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 140252015305 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 140252015305 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5728170249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728170249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573361000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573361000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301531249 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301531249 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753658 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753658 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060108 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060108 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027469 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027469 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13596.981960 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13596.981960 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.717339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.717339 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15110.546163 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15110.546163 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12012.414680 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12012.414680 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17820.110737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17820.110737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17431.861393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17431.861393 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 20761818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20753624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6407423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1660819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1554140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 42524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 42526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1952681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1952681 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27072222 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 26182676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 874780 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 54730977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 863723604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1036044256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1950336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2556184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1904274380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 465684 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 30748357 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.061188 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 474114 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 30632803 99.62% 99.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115554 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 30748357 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23350352499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1018500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20304235714 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13344056707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 358207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 555725500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115481 # number of replacements -system.iocache.tags.tagsinuse 10.454792 # Cycle average of tags in use +system.iobus.trans_dist::ReadReq 40402 # Transaction distribution +system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115480 # number of replacements +system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115497 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153677258000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.509713 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945079 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219357 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434067 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653424 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039872 # Number of tag accesses -system.iocache.tags.data_accesses 1039872 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039857 # Number of tag accesses +system.iocache.tags.data_accesses 1039857 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8835 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8835 # number of demand (read+write) misses -system.iocache.demand_misses::total 8875 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses +system.iocache.demand_misses::total 8876 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8835 # number of overall misses -system.iocache.overall_misses::total 8875 # number of overall misses +system.iocache.overall_misses::realview.ide 8836 # number of overall misses +system.iocache.overall_misses::total 8876 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1898661362 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1904146362 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1898661362 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1904485362 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1898661362 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1904485362 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8835 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106667 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106667 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8835 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8875 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8835 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8875 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000028 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000028 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1344,53 +1271,61 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 214902.248104 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 214624.251803 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214589.899944 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214589.899944 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51753 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.426776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106629 # number of writebacks +system.iocache.writebacks::total 106629 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8835 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8872 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8835 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8875 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8835 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8875 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1439157862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1442718862 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6525754202 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6525754202 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1439157862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1442901862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1439157862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1442901862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses @@ -1398,18 +1333,112 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 162892.797057 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 162614.840171 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 462201 # Transaction distribution +system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::WriteReq 33872 # Transaction distribution +system.membus.trans_dist::WriteResp 33872 # Transaction distribution +system.membus.trans_dist::Writeback 1241967 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution +system.membus.trans_dist::ReadExReq 534513 # Transaction distribution +system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3244 # Total snoops (count) +system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2814199 # Request fanout histogram +system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- -- cgit v1.2.3