From 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 24 Jan 2013 12:29:00 -0600 Subject: regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables. --- .../fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini | 1 + .../fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout | 6 +++--- .../fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 10 +++++----- .../fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini | 1 + .../fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout | 6 +++--- .../fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 10 +++++----- 6 files changed, 18 insertions(+), 16 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/x86') diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 12b6dc7b6..527c82daf 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -74,6 +74,7 @@ slave=system.membus.master[1] [system.cpu] type=AtomicSimpleCPU children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer +branchPred=Null checker=Null clock=500 cpu_id=0 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index c9e113bf6..c7231a234 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 21:50:34 -gem5 started Sep 10 2012 21:50:39 +gem5 compiled Jan 23 2013 16:30:44 +gem5 started Jan 23 2013 18:32:27 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent @@ -12,4 +12,4 @@ Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112043255000 because m5_exit instruction encountered +Exiting @ tick 5112040970500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 4d2d6b5c4..175418c2b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1661898 # Simulator instruction rate (inst/s) -host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42518772648 # Simulator tick rate (ticks/s) -host_mem_usage 621064 # Number of bytes of host memory used -host_seconds 120.23 # Real time elapsed on the host +host_inst_rate 1071475 # Simulator instruction rate (inst/s) +host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27413112180 # Simulator tick rate (ticks/s) +host_mem_usage 626876 # Number of bytes of host memory used +host_seconds 186.48 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated sim_ops 409125923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 378234e02..f5bfaf68d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -74,6 +74,7 @@ slave=system.membus.master[1] [system.cpu] type=TimingSimpleCPU children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer +branchPred=Null checker=Null clock=500 cpu_id=0 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 954f254a4..0439ed364 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 21:50:34 -gem5 started Sep 10 2012 21:50:39 +gem5 compiled Jan 23 2013 16:30:44 +gem5 started Jan 23 2013 18:02:27 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent @@ -12,4 +12,4 @@ Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5196043137000 because m5_exit instruction encountered +Exiting @ tick 5191112864000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5586ee7f0..5387a3a4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.191113 # Nu sim_ticks 5191112864000 # Number of ticks simulated final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1076481 # Simulator instruction rate (inst/s) -host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43574012985 # Simulator tick rate (ticks/s) -host_mem_usage 651144 # Number of bytes of host memory used -host_seconds 119.13 # Real time elapsed on the host +host_inst_rate 663100 # Simulator instruction rate (inst/s) +host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26841102406 # Simulator tick rate (ticks/s) +host_mem_usage 658020 # Number of bytes of host memory used +host_seconds 193.40 # Real time elapsed on the host sim_insts 128244620 # Number of instructions simulated sim_ops 247214608 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory -- cgit v1.2.3