From fbc1feb39ac19379983ca714f4c7fadcd9fdabf6 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 28 Sep 2013 15:25:17 -0400 Subject: tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority. --- .../linux/tsunami-simple-atomic-dual/config.ini | 224 +- .../alpha/linux/tsunami-simple-atomic-dual/simout | 10 +- .../linux/tsunami-simple-atomic-dual/stats.txt | 118 +- .../alpha/linux/tsunami-simple-atomic/config.ini | 191 +- .../ref/alpha/linux/tsunami-simple-atomic/simout | 10 +- .../alpha/linux/tsunami-simple-atomic/stats.txt | 82 +- .../linux/tsunami-simple-timing-dual/config.ini | 201 +- .../alpha/linux/tsunami-simple-timing-dual/simout | 12 +- .../tsunami-simple-timing-dual/system.terminal | 4 +- .../alpha/linux/tsunami-simple-timing/config.ini | 188 +- .../ref/alpha/linux/tsunami-simple-timing/simout | 10 +- .../linux/tsunami-simple-timing/system.terminal | 2 +- .../linux/realview-simple-atomic-dual/config.ini | 244 +- .../arm/linux/realview-simple-atomic-dual/simerr | 1 + .../arm/linux/realview-simple-atomic-dual/simout | 8 +- .../linux/realview-simple-atomic-dual/stats.txt | 124 +- .../arm/linux/realview-simple-atomic-dual/status | 1 - .../realview-simple-atomic-dual/system.terminal | Bin 5940 -> 5940 bytes .../arm/linux/realview-simple-atomic/config.ini | 207 +- .../ref/arm/linux/realview-simple-atomic/simerr | 1 + .../ref/arm/linux/realview-simple-atomic/simout | 8 +- .../ref/arm/linux/realview-simple-atomic/stats.txt | 76 +- .../ref/arm/linux/realview-simple-atomic/status | 1 - .../linux/realview-simple-atomic/system.terminal | Bin 5878 -> 5878 bytes .../linux/realview-simple-timing-dual/config.ini | 217 +- .../arm/linux/realview-simple-timing-dual/simout | 10 +- .../arm/linux/realview-simple-timing-dual/status | 1 - .../realview-simple-timing-dual/system.terminal | Bin 5939 -> 5939 bytes .../arm/linux/realview-simple-timing/config.ini | 204 +- .../ref/arm/linux/realview-simple-timing/simerr | 1 + .../ref/arm/linux/realview-simple-timing/simout | 10 +- .../ref/arm/linux/realview-simple-timing/status | 1 - .../linux/realview-simple-timing/system.terminal | Bin 5878 -> 5878 bytes .../linux/realview-switcheroo-atomic/config.ini | 190 +- .../arm/linux/realview-switcheroo-atomic/simerr | 1 + .../arm/linux/realview-switcheroo-atomic/simout | 4673 ++++++++++---------- .../ref/x86/linux/pc-simple-atomic/config.ini | 199 +- .../ref/x86/linux/pc-simple-atomic/simout | 10 +- .../ref/x86/linux/pc-simple-timing/config.ini | 196 +- .../ref/x86/linux/pc-simple-timing/simout | 10 +- 40 files changed, 4099 insertions(+), 3347 deletions(-) delete mode 100644 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status delete mode 100644 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status delete mode 100644 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status delete mode 100644 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status (limited to 'tests/quick/fs/10.linux-boot') diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 573c7933c..f697c291f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +cache_line_size=64 +clk_domain=system.clk_domain +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -36,7 +37,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=8796093022208:18446744073709551615 req_size=16 @@ -44,12 +45,16 @@ resp_size=16 master=system.iobus.slave[0] slave=system.membus.master[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -68,6 +73,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -80,10 +89,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -94,22 +103,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=AlphaTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -120,12 +138,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=AlphaInterrupts @@ -142,9 +169,8 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -163,6 +189,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -175,10 +205,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -189,22 +219,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=AlphaTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -215,12 +254,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=AlphaInterrupts @@ -234,6 +282,11 @@ size=48 [system.cpu1.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.disk0] type=IdeDisk children=image @@ -251,7 +304,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -271,7 +324,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -280,8 +333,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -291,10 +343,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -305,18 +357,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -327,18 +388,27 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -347,7 +417,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -364,28 +434,35 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 -conf_table_reported=false +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[1] [system.simple_disk] @@ -396,7 +473,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -408,9 +485,9 @@ port=3456 [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side @@ -424,7 +501,7 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor -clock=1000 +clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 @@ -436,7 +513,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8803072344064 pio_latency=100000 system=system @@ -483,7 +560,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=2000 +clk_domain=system.clk_domain config_latency=20000 dma_data_free=false dma_desc_free=false @@ -514,7 +591,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -531,7 +608,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -548,7 +625,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -565,7 +642,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -582,7 +659,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -599,7 +676,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -616,7 +693,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -633,7 +710,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -650,7 +727,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -667,7 +744,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -684,7 +761,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -701,7 +778,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -718,7 +795,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -735,7 +812,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -752,7 +829,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -769,7 +846,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -786,7 +863,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -803,7 +880,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -820,7 +897,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -837,7 +914,7 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice -clock=1000 +clk_domain=system.clk_domain devicename=FrameBuffer pio_addr=8804615848912 pio_latency=100000 @@ -884,7 +961,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 @@ -901,7 +978,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO -clock=1000 +clk_domain=system.clk_domain frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -913,7 +990,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8802535473152 pio_latency=100000 system=system @@ -923,7 +1000,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.tsunami size=16777216 @@ -932,7 +1010,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 -clock=1000 +clk_domain=system.clk_domain pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -940,3 +1018,7 @@ system=system terminal=system.terminal pio=system.iobus.master[23] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index a62617d01..410351310 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:01:11 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:50 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 -Exiting @ tick 1870325497500 because m5_exit instruction encountered +Exiting @ tick 1870335643500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 101a67dc8..1e009881b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335643500 # Number of ticks simulated final_tick 1870335643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1417566 # Simulator instruction rate (inst/s) -host_op_rate 1417565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41981821830 # Simulator tick rate (ticks/s) -host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 44.55 # Real time elapsed on the host +host_inst_rate 2937220 # Simulator instruction rate (inst/s) +host_op_rate 2937218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86986978503 # Simulator tick rate (ticks/s) +host_mem_usage 308008 # Number of bytes of host memory used +host_seconds 21.50 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory @@ -198,23 +198,23 @@ system.physmem.avgGap nan # Av system.membus.throughput 42160246 # Throughput (bytes/s) system.membus.data_through_bus 78853810 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.tags.replacements 1000626 # number of replacements -system.l2c.tags.tagsinuse 65381.922487 # Cycle average of tags in use -system.l2c.tags.total_refs 2464723 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.312626 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56158.706931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4894.235246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4134.598984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 174.423126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.958201 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.tags.replacements 1000626 # number of replacements +system.l2c.tags.tagsinuse 65381.922487 # Cycle average of tags in use +system.l2c.tags.total_refs 2464723 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.312626 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 56158.706931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4894.235246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4134.598984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 174.423126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 19.958201 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 873088 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 763068 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 101908 # number of ReadReq hits @@ -326,15 +326,15 @@ system.l2c.cache_copies 0 # nu system.l2c.writebacks::writebacks 81316 # number of writebacks system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -562,15 +562,15 @@ system.toL2Bus.data_through_bus 246743154 # To system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) system.iobus.throughput 1460500 # Throughput (bytes/s) system.iobus.data_through_bus 2731626 # Total data (bytes) -system.cpu0.icache.tags.replacements 884406 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 884406 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 56345130 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 56345130 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 56345130 # number of demand (read+write) hits @@ -604,15 +604,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1978683 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 1978683 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129817 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 7298341 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7298341 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5462261 # number of WriteReq hits @@ -799,15 +799,15 @@ system.cpu1.kern.mode_ticks::kernel 1373906500 0.07% 0.07% # nu system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1868002681000 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 103103 # number of replacements -system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 103103 # number of replacements +system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 5832124 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 5832124 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 5832124 # number of demand (read+write) hits @@ -841,15 +841,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 62052 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 62052 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.569557 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823378 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 1109514 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1109514 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 707455 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 50088b4ab..ac72e998f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami +children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +cache_line_size=64 +clk_domain=system.clk_domain +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -36,7 +37,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=8796093022208:18446744073709551615 req_size=16 @@ -44,12 +45,16 @@ resp_size=16 master=system.iobus.slave[0] slave=system.membus.master[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -68,6 +73,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -80,10 +89,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -94,22 +103,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -120,12 +138,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=AlphaInterrupts @@ -138,10 +165,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -152,17 +179,26 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -171,6 +207,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.disk0] type=IdeDisk children=image @@ -188,7 +229,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -208,7 +249,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -217,8 +258,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -228,10 +268,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -242,18 +282,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -262,7 +311,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -279,28 +328,35 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 -conf_table_reported=false +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[1] [system.simple_disk] @@ -311,7 +367,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -329,7 +385,7 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor -clock=1000 +clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 @@ -341,7 +397,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8803072344064 pio_latency=100000 system=system @@ -388,7 +444,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=2000 +clk_domain=system.clk_domain config_latency=20000 dma_data_free=false dma_desc_free=false @@ -419,7 +475,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -436,7 +492,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -453,7 +509,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -470,7 +526,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -487,7 +543,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -504,7 +560,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -521,7 +577,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -538,7 +594,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -555,7 +611,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -572,7 +628,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -589,7 +645,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -606,7 +662,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -623,7 +679,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -640,7 +696,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -657,7 +713,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -674,7 +730,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -691,7 +747,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -708,7 +764,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -725,7 +781,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -742,7 +798,7 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice -clock=1000 +clk_domain=system.clk_domain devicename=FrameBuffer pio_addr=8804615848912 pio_latency=100000 @@ -789,7 +845,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 @@ -806,7 +862,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO -clock=1000 +clk_domain=system.clk_domain frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -818,7 +874,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8802535473152 pio_latency=100000 system=system @@ -828,7 +884,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.tsunami size=16777216 @@ -837,7 +894,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 -clock=1000 +clk_domain=system.clk_domain pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -845,3 +902,7 @@ system=system terminal=system.terminal pio=system.iobus.master[23] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index c4aa2f920..b63c77b44 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:01:49 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:50 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1829330593000 because m5_exit instruction encountered +Exiting @ tick 1829332269000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index ee54d11d9..d5ea0605d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332269000 # Number of ticks simulated final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1710493 # Simulator instruction rate (inst/s) -host_op_rate 1710492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52117657653 # Simulator tick rate (ticks/s) -host_mem_usage 306192 # Number of bytes of host memory used -host_seconds 35.10 # Real time elapsed on the host +host_inst_rate 2947908 # Simulator instruction rate (inst/s) +host_op_rate 2947905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89820884398 # Simulator tick rate (ticks/s) +host_mem_usage 305960 # Number of bytes of host memory used +host_seconds 20.37 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory @@ -188,15 +188,15 @@ system.physmem.avgGap nan # Av system.membus.throughput 42552540 # Throughput (bytes/s) system.membus.data_through_bus 77842734 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.tags.replacements 41686 # number of replacements +system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -416,15 +416,15 @@ system.tsunami.ethernet.postedInterrupts 0 # nu system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.iobus.throughput 1480181 # Throughput (bytes/s) system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919609 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 919609 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits @@ -458,19 +458,19 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992301 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 992301 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits @@ -538,15 +538,15 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks system.cpu.l2cache.writebacks::total 74291 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042706 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2042706 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 007c56f0a..4764f4e77 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +cache_line_size=64 +clk_domain=system.clk_domain +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -36,7 +37,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=8796093022208:18446744073709551615 req_size=16 @@ -44,12 +45,16 @@ resp_size=16 master=system.iobus.slave[0] slave=system.membus.master[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -67,6 +72,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -76,10 +82,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -90,22 +96,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=AlphaTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -116,12 +131,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=AlphaInterrupts @@ -138,9 +162,8 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -158,6 +181,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer @@ -167,10 +191,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -181,22 +205,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=AlphaTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -207,12 +240,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=AlphaInterrupts @@ -226,6 +268,11 @@ size=48 [system.cpu1.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.disk0] type=IdeDisk children=image @@ -243,7 +290,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -263,7 +310,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -272,8 +319,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -283,10 +329,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -297,18 +343,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -319,17 +374,25 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -340,7 +403,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -358,19 +421,24 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -381,7 +449,6 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[1] [system.simple_disk] @@ -392,7 +459,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -404,8 +471,7 @@ port=3456 [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -421,7 +487,7 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor -clock=1000 +clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 @@ -433,7 +499,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8803072344064 pio_latency=100000 system=system @@ -480,7 +546,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=2000 +clk_domain=system.clk_domain config_latency=20000 dma_data_free=false dma_desc_free=false @@ -511,7 +577,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -528,7 +594,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -545,7 +611,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -562,7 +628,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -579,7 +645,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -596,7 +662,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -613,7 +679,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -630,7 +696,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -647,7 +713,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -664,7 +730,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -681,7 +747,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -698,7 +764,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -715,7 +781,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -732,7 +798,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -749,7 +815,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -766,7 +832,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -783,7 +849,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -800,7 +866,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -817,7 +883,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -834,7 +900,7 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice -clock=1000 +clk_domain=system.clk_domain devicename=FrameBuffer pio_addr=8804615848912 pio_latency=100000 @@ -881,7 +947,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 @@ -898,7 +964,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO -clock=1000 +clk_domain=system.clk_domain frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -910,7 +976,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8802535473152 pio_latency=100000 system=system @@ -920,7 +986,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.tsunami size=16777216 @@ -929,7 +996,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 -clock=1000 +clk_domain=system.clk_domain pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -937,3 +1004,7 @@ system=system terminal=system.terminal pio=system.iobus.master[23] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 117d6c541..a33dd389d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 14:39:13 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:51 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 614109000 -Exiting @ tick 1955749107000 because m5_exit instruction encountered +info: Launching CPU 1 @ 675287000 +Exiting @ tick 1961841175000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index aa80e0b5e..0d754b641 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 unix_boot_mem ends at FFFFFC0000078000 k_argc = 0 jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 CallbackFixup 0 18000, t7=FFFFFC000070C000 + Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memcluster 1, usage 0, start 392, end 16384 freeing pages 1069:16384 reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles + 4096K Bcache detected; load hit latency 38 cycles, load miss latency 142 cycles SMP: 2 CPUs probed -- cpu_present_mask = 3 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d8f41ddb0..54bf6e928 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami +children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +cache_line_size=64 +clk_domain=system.clk_domain +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -36,7 +37,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=8796093022208:18446744073709551615 req_size=16 @@ -44,12 +45,16 @@ resp_size=16 master=system.iobus.slave[0] slave=system.membus.master[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -67,6 +72,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -76,10 +82,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -90,22 +96,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -116,12 +131,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=AlphaInterrupts @@ -134,10 +158,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -148,17 +172,26 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -167,6 +200,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.disk0] type=IdeDisk children=image @@ -184,7 +222,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -204,7 +242,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -213,8 +251,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -224,10 +261,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -238,18 +275,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -258,7 +304,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -275,28 +321,35 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 -conf_table_reported=false +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[1] [system.simple_disk] @@ -307,7 +360,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -325,7 +378,7 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor -clock=1000 +clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 @@ -337,7 +390,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8803072344064 pio_latency=100000 system=system @@ -384,7 +437,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=2000 +clk_domain=system.clk_domain config_latency=20000 dma_data_free=false dma_desc_free=false @@ -415,7 +468,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -432,7 +485,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -449,7 +502,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -466,7 +519,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -483,7 +536,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -500,7 +553,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -517,7 +570,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -534,7 +587,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -551,7 +604,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -568,7 +621,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -585,7 +638,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -602,7 +655,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -619,7 +672,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -636,7 +689,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -653,7 +706,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -670,7 +723,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -687,7 +740,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -704,7 +757,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -721,7 +774,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -738,7 +791,7 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice -clock=1000 +clk_domain=system.clk_domain devicename=FrameBuffer pio_addr=8804615848912 pio_latency=100000 @@ -785,7 +838,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 @@ -802,7 +855,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO -clock=1000 +clk_domain=system.clk_domain frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -814,7 +867,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip -clock=1000 +clk_domain=system.clk_domain pio_addr=8802535473152 pio_latency=100000 system=system @@ -824,7 +877,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.tsunami size=16777216 @@ -833,7 +887,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 -clock=1000 +clk_domain=system.clk_domain pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -841,3 +895,7 @@ system=system terminal=system.terminal pio=system.iobus.master[23] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 229260842..cabc90a11 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:32:52 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:50 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1910582068000 because m5_exit instruction encountered +Exiting @ tick 1918473094000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index ff644ed3f..0d89ac053 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memcluster 1, usage 0, start 392, end 16384 freeing pages 1069:16384 reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles + 4096K Bcache detected; load hit latency 38 cycles, load miss latency 142 cycles SMP: 1 CPUs probed -- cpu_present_mask = 1 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 25f4e376e..b499d5442 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1000 -dtb_filename= +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -27,6 +28,8 @@ mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -40,7 +43,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -65,15 +68,19 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -92,6 +99,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -104,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -118,12 +129,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=ArmTLB children=walker @@ -132,17 +152,17 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -153,12 +173,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=ArmInterrupts @@ -187,7 +216,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -198,9 +227,8 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -219,6 +247,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -231,10 +263,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -245,12 +277,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=ArmTLB children=walker @@ -259,17 +300,17 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -280,12 +321,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=ArmInterrupts @@ -314,7 +364,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -322,14 +372,18 @@ port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.intrctrl] type=IntrControl sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -338,10 +392,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -352,18 +406,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -374,27 +437,36 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -411,29 +483,36 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 +burst_length=8 +channels=1 +clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[2] +port=system.membus.master[6] [system.realview] type=RealView @@ -446,16 +525,16 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1000 +clk_domain=system.clk_domain pio_addr=520093696 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -502,7 +581,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -520,7 +599,7 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -534,7 +613,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -543,7 +622,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -559,8 +638,8 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic -clock=1000 +type=Pl390 +clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -569,12 +648,12 @@ int_latency=10000 it_lines=128 platform=system.realview system=system -pio=system.membus.master[3] +pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -584,7 +663,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -594,7 +673,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -604,7 +683,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=52 @@ -618,7 +697,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=53 @@ -631,7 +710,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -644,23 +723,23 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system -pio=system.membus.master[6] +pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -670,19 +749,18 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=false in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 -zero=true port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1000 +clk_domain=system.clk_domain idreg=0 pio_addr=268435456 pio_latency=100000 @@ -694,7 +772,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=100000 int_num=42 @@ -707,7 +785,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -717,7 +795,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -727,7 +805,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -737,7 +815,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -747,7 +825,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -761,7 +839,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -774,7 +852,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1000 +clk_domain=system.clk_domain end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -789,7 +867,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -799,7 +877,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -809,7 +887,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -819,7 +897,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -835,9 +913,9 @@ port=3456 [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side @@ -849,3 +927,7 @@ frame_capture=false number=0 port=5900 +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index e8e271d58..4ccac5e7b 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index c2890e671..789ceb651 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:45:38 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 09:04:45 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 912096763500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index ee810dcc9..1f4c71309 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 749434 # Simulator instruction rate (inst/s) -host_op_rate 964895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11092016800 # Simulator tick rate (ticks/s) -host_mem_usage 399496 # Number of bytes of host memory used -host_seconds 82.23 # Real time elapsed on the host +host_inst_rate 1616966 # Simulator instruction rate (inst/s) +host_op_rate 2081841 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23931929912 # Simulator tick rate (ticks/s) +host_mem_usage 396248 # Number of bytes of host memory used +host_seconds 38.11 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -234,29 +234,29 @@ system.realview.nvmem.bw_total::total 75 # To system.membus.throughput 64986577 # Throughput (bytes/s) system.membus.data_through_bus 59274047 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use -system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.replacements 70658 # number of replacements +system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -487,15 +487,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 428546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits @@ -529,15 +529,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 323609 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits @@ -663,15 +663,15 @@ system.cpu1.not_idle_fraction 0.022362 # Pe system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 433942 # number of replacements +system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits @@ -705,15 +705,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 294289 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 294289 # number of replacements +system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits @@ -773,12 +773,12 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status deleted file mode 100644 index 7edf5b1c7..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status +++ /dev/null @@ -1 +0,0 @@ -build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED! diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal index 17e9c9abf..f2f53421d 100644 Binary files a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal and b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal differ diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 687db2fa1..4246eb19f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver +children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1000 -dtb_filename= +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -27,6 +28,8 @@ mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -40,7 +43,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -65,15 +68,19 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -92,6 +99,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -104,10 +115,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -118,12 +129,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=ArmTLB children=walker @@ -132,17 +152,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -153,12 +173,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=ArmInterrupts @@ -187,17 +216,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -208,17 +237,26 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -227,14 +265,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.intrctrl] type=IntrControl sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -243,10 +285,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -257,27 +299,36 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -294,29 +345,36 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 +burst_length=8 +channels=1 +clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[2] +port=system.membus.master[6] [system.realview] type=RealView @@ -329,16 +387,16 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1000 +clk_domain=system.clk_domain pio_addr=520093696 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -385,7 +443,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -403,7 +461,7 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -417,7 +475,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -426,7 +484,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -442,8 +500,8 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic -clock=1000 +type=Pl390 +clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -452,12 +510,12 @@ int_latency=10000 it_lines=128 platform=system.realview system=system -pio=system.membus.master[3] +pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -467,7 +525,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -477,7 +535,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -487,7 +545,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=52 @@ -501,7 +559,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=53 @@ -514,7 +572,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -527,23 +585,23 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system -pio=system.membus.master[6] +pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -553,19 +611,18 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=false in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 -zero=true port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1000 +clk_domain=system.clk_domain idreg=0 pio_addr=268435456 pio_latency=100000 @@ -577,7 +634,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=100000 int_num=42 @@ -590,7 +647,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -600,7 +657,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -610,7 +667,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -620,7 +677,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -630,7 +687,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -644,7 +701,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -657,7 +714,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1000 +clk_domain=system.clk_domain end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -672,7 +729,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -682,7 +739,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -692,7 +749,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -702,7 +759,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -722,3 +779,7 @@ frame_capture=false number=0 port=5900 +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 3ee89fc27..eda827fb8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index ec6b1ae21..0ff7b53a5 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:44:32 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 08:30:49 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332810264000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 44e286527..a865904c2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 692273 # Simulator instruction rate (inst/s) -host_op_rate 890221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26733610702 # Simulator tick rate (ticks/s) -host_mem_usage 396420 # Number of bytes of host memory used -host_seconds 87.26 # Real time elapsed on the host +host_inst_rate 1522133 # Simulator instruction rate (inst/s) +host_op_rate 1957369 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58780416325 # Simulator tick rate (ticks/s) +host_mem_usage 396116 # Number of bytes of host memory used +host_seconds 39.70 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -285,15 +285,15 @@ system.cpu.not_idle_fraction 0.016889 # Pe system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 850590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits @@ -327,23 +327,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 62243 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits @@ -435,15 +435,15 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623337 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits @@ -502,12 +502,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status deleted file mode 100644 index 5d3e81846..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status +++ /dev/null @@ -1 +0,0 @@ -build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED! diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal index c810346c6..d321164ca 100644 Binary files a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal and b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal differ diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 2d5c88739..6e5d183fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -27,6 +28,8 @@ mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -40,7 +43,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -65,15 +68,19 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -91,6 +98,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -100,10 +108,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -114,12 +122,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=ArmTLB children=walker @@ -128,17 +145,17 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -149,12 +166,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=ArmInterrupts @@ -183,7 +209,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -194,9 +220,8 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -214,6 +239,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer @@ -223,10 +249,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -237,12 +263,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=ArmTLB children=walker @@ -251,17 +286,17 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -272,12 +307,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=ArmInterrupts @@ -306,7 +350,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -314,14 +358,18 @@ port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.intrctrl] type=IntrControl sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -330,10 +378,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -344,18 +392,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -366,28 +423,36 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -405,19 +470,24 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -428,8 +498,7 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[2] +port=system.membus.master[6] [system.realview] type=RealView @@ -442,16 +511,16 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1000 +clk_domain=system.clk_domain pio_addr=520093696 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -498,7 +567,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -516,7 +585,7 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -530,7 +599,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -539,7 +608,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -556,7 +625,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Pl390 -clock=1000 +clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -565,12 +634,12 @@ int_latency=10000 it_lines=128 platform=system.realview system=system -pio=system.membus.master[3] +pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -580,7 +649,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -590,7 +659,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -600,7 +669,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=52 @@ -614,7 +683,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=53 @@ -627,7 +696,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -640,23 +709,23 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system -pio=system.membus.master[6] +pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -666,19 +735,18 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=false in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 -zero=true port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1000 +clk_domain=system.clk_domain idreg=0 pio_addr=268435456 pio_latency=100000 @@ -690,7 +758,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=100000 int_num=42 @@ -703,7 +771,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -713,7 +781,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -723,7 +791,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -733,7 +801,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -743,7 +811,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -757,7 +825,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -770,7 +838,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1000 +clk_domain=system.clk_domain end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -785,7 +853,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -795,7 +863,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -805,7 +873,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -815,7 +883,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -831,8 +899,7 @@ port=3456 [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -846,3 +913,7 @@ frame_capture=false number=0 port=5900 +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index a21ab0771..c328b3227 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:15:23 -gem5 started Mar 26 2013 15:15:53 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 08:25:29 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1183437503500 because m5_exit instruction encountered +Exiting @ tick 1194883580500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status deleted file mode 100644 index 8ae0da5a8..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status +++ /dev/null @@ -1 +0,0 @@ -build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED! diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal index 4f02e6414..69edb0827 100644 Binary files a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal and b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal differ diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index f1513514e..01d95ba19 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver +children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1000 -dtb_filename= +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -27,6 +28,8 @@ mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -40,7 +43,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -65,15 +68,19 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -91,6 +98,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -100,10 +108,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -114,12 +122,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=ArmTLB children=walker @@ -128,17 +145,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -149,12 +166,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=ArmInterrupts @@ -183,17 +209,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -204,17 +230,26 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -223,14 +258,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.intrctrl] type=IntrControl sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -239,10 +278,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -253,27 +292,36 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -290,29 +338,36 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM -addr_mapping=openmap +activation_limit=4 +addr_mapping=RaBaChCo banks_per_rank=8 -clock=1000 +burst_length=8 +channels=1 +clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[2] +port=system.membus.master[6] [system.realview] type=RealView @@ -325,16 +380,16 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1000 +clk_domain=system.clk_domain pio_addr=520093696 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -381,7 +436,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -399,7 +454,7 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -413,7 +468,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -422,7 +477,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -438,8 +493,8 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic -clock=1000 +type=Pl390 +clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -448,12 +503,12 @@ int_latency=10000 it_lines=128 platform=system.realview system=system -pio=system.membus.master[3] +pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -463,7 +518,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -473,7 +528,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -483,7 +538,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=52 @@ -497,7 +552,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=53 @@ -510,7 +565,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -523,23 +578,23 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system -pio=system.membus.master[6] +pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -549,19 +604,18 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=false in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 -zero=true port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1000 +clk_domain=system.clk_domain idreg=0 pio_addr=268435456 pio_latency=100000 @@ -573,7 +627,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=100000 int_num=42 @@ -586,7 +640,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -596,7 +650,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -606,7 +660,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -616,7 +670,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -626,7 +680,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -640,7 +694,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -653,7 +707,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1000 +clk_domain=system.clk_domain end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -668,7 +722,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -678,7 +732,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -688,7 +742,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -698,7 +752,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -718,3 +772,7 @@ frame_capture=false number=0 port=5900 +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 3ee89fc27..eda827fb8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index a83c8cf44..b95a8c30f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:45:50 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 08:14:19 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2603634694000 because m5_exit instruction encountered +Exiting @ tick 2615716222000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status deleted file mode 100644 index 4523c3c36..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ /dev/null @@ -1 +0,0 @@ -build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal index 3191ccab8..ca0537849 100644 Binary files a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal and b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal differ diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 7bfde3940..d251aac9e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false @@ -24,7 +25,7 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -42,7 +43,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -70,12 +71,16 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -110,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -124,12 +129,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=ArmTLB children=walker @@ -138,17 +152,17 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -159,12 +173,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=ArmInterrupts @@ -193,7 +216,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -203,10 +226,9 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer -branchPred=Null +children=dtb isa itb tracer checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -215,7 +237,7 @@ dtb=system.cpu1.dtb fastmem=false function_trace=false function_trace_start=0 -interrupts=system.cpu1.interrupts +interrupts=Null isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 @@ -245,13 +267,10 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system -[system.cpu1.interrupts] -type=ArmInterrupts - [system.cpu1.isa] type=ArmISA fpsid=1090793632 @@ -277,21 +296,25 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.intrctrl] type=IntrControl sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -300,10 +323,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -314,18 +337,27 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -336,28 +368,36 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -375,19 +415,24 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -398,8 +443,7 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[2] +port=system.membus.master[6] [system.realview] type=RealView @@ -412,16 +456,16 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1000 +clk_domain=system.clk_domain pio_addr=520093696 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -468,7 +512,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -486,7 +530,7 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -500,7 +544,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -509,7 +553,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -526,7 +570,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Pl390 -clock=1000 +clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -535,12 +579,12 @@ int_latency=10000 it_lines=128 platform=system.realview system=system -pio=system.membus.master[3] +pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -550,7 +594,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -560,7 +604,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -570,7 +614,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=52 @@ -584,7 +628,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=1000000 int_num=53 @@ -597,7 +641,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -610,23 +654,23 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system -pio=system.membus.master[6] +pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -636,19 +680,18 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 +clk_domain=system.clk_domain conf_table_reported=false in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 -zero=true port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1000 +clk_domain=system.clk_domain idreg=0 pio_addr=268435456 pio_latency=100000 @@ -660,7 +703,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1000 +clk_domain=system.clk_domain gic=system.realview.gic int_delay=100000 int_num=42 @@ -673,7 +716,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -683,7 +726,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -693,7 +736,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -703,7 +746,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -713,7 +756,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -727,7 +770,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1000 +clk_domain=system.clk_domain clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -740,7 +783,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1000 +clk_domain=system.clk_domain end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -755,7 +798,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -765,7 +808,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -775,7 +818,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -785,7 +828,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1000 +clk_domain=system.clk_domain ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -801,8 +844,7 @@ port=3456 [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -816,3 +858,7 @@ frame_capture=false number=0 port=5900 +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index 083c63715..06edbeba7 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index ac14d4997..9b6e36065 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:48:26 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 07:58:36 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Switching CPUs... @@ -35,9312 +35,9315 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 6000000000. Starting simulation... switching cpus -info: Entering event queue @ 6000001000. Starting simulation... +info: Entering event queue @ 6000003500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 7000001000. Starting simulation... +info: Entering event queue @ 7000003500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 8000001000. Starting simulation... +info: Entering event queue @ 8000003500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000001000. Starting simulation... +info: Entering event queue @ 9000003500. Starting simulation... switching cpus -info: Entering event queue @ 9000002500. Starting simulation... +info: Entering event queue @ 9000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 10000002500. Starting simulation... +info: Entering event queue @ 10000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 11000002500. Starting simulation... +info: Entering event queue @ 11000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 12000002500. Starting simulation... +info: Entering event queue @ 12000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 13000002500. Starting simulation... +info: Entering event queue @ 13000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 14000002500. Starting simulation... +info: Entering event queue @ 14000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 15000002500. Starting simulation... +info: Entering event queue @ 15000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 16000002500. Starting simulation... +info: Entering event queue @ 16000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 17000002500. Starting simulation... +info: Entering event queue @ 17000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 18000002500. Starting simulation... +info: Entering event queue @ 18000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 19000002500. Starting simulation... +info: Entering event queue @ 19000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 20000002500. Starting simulation... +info: Entering event queue @ 20000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 21000002500. Starting simulation... +info: Entering event queue @ 21000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 22000002500. Starting simulation... +info: Entering event queue @ 22000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 23000002500. Starting simulation... +info: Entering event queue @ 23000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 24000002500. Starting simulation... +info: Entering event queue @ 24000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 25000002500. Starting simulation... +info: Entering event queue @ 25000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 26000002500. Starting simulation... +info: Entering event queue @ 26000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 27000002500. Starting simulation... +info: Entering event queue @ 27000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 28000002500. Starting simulation... +info: Entering event queue @ 28000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 29000002500. Starting simulation... +info: Entering event queue @ 29000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 30000002500. Starting simulation... +info: Entering event queue @ 30000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 31000002500. Starting simulation... +info: Entering event queue @ 31000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 32000002500. Starting simulation... +info: Entering event queue @ 32000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 33000002500. Starting simulation... +info: Entering event queue @ 33000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 34000002500. Starting simulation... +info: Entering event queue @ 34000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 35000002500. Starting simulation... +info: Entering event queue @ 35000006500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU +info: Entering event queue @ 36000006500. Starting simulation... switching cpus -info: Entering event queue @ 36000002500. Starting simulation... +info: Entering event queue @ 36000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 37000002500. Starting simulation... +info: Entering event queue @ 37000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 38000002500. Starting simulation... +info: Entering event queue @ 38000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 39000002500. Starting simulation... +info: Entering event queue @ 39000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 40000002500. Starting simulation... +info: Entering event queue @ 40000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 41000002500. Starting simulation... +info: Entering event queue @ 41000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 42000002500. Starting simulation... +info: Entering event queue @ 42000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 43000002500. Starting simulation... +info: Entering event queue @ 43000007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 44000002500. Starting simulation... +info: Entering event queue @ 44000007000. Starting simulation... switching cpus -info: Entering event queue @ 44000004000. Starting simulation... +info: Entering event queue @ 44000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 45000004000. Starting simulation... +info: Entering event queue @ 45000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 46000004000. Starting simulation... +info: Entering event queue @ 46000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 47000004000. Starting simulation... +info: Entering event queue @ 47000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 48000004000. Starting simulation... +info: Entering event queue @ 48000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 49000004000. Starting simulation... +info: Entering event queue @ 49000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 50000004000. Starting simulation... +info: Entering event queue @ 50000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 51000004000. Starting simulation... +info: Entering event queue @ 51000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 52000004000. Starting simulation... +info: Entering event queue @ 52000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 53000004000. Starting simulation... +info: Entering event queue @ 53000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 54000004000. Starting simulation... +info: Entering event queue @ 54000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 55000004000. Starting simulation... +info: Entering event queue @ 55000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 56000004000. Starting simulation... +info: Entering event queue @ 56000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 57000004000. Starting simulation... +info: Entering event queue @ 57000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 58000004000. Starting simulation... +info: Entering event queue @ 58000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 59000004000. Starting simulation... +info: Entering event queue @ 59000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 60000004000. Starting simulation... +info: Entering event queue @ 60000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 61000004000. Starting simulation... +info: Entering event queue @ 61000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 62000004000. Starting simulation... +info: Entering event queue @ 62000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 63000004000. Starting simulation... +info: Entering event queue @ 63000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 64000004000. Starting simulation... +info: Entering event queue @ 64000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 65000004000. Starting simulation... +info: Entering event queue @ 65000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 66000004000. Starting simulation... +info: Entering event queue @ 66000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 67000004000. Starting simulation... +info: Entering event queue @ 67000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 68000004000. Starting simulation... +info: Entering event queue @ 68000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 69000004000. Starting simulation... +info: Entering event queue @ 69000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 70000004000. Starting simulation... +info: Entering event queue @ 70000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 71000004000. Starting simulation... +info: Entering event queue @ 71000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 72000004000. Starting simulation... +info: Entering event queue @ 72000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 73000004000. Starting simulation... +info: Entering event queue @ 73000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 74000004000. Starting simulation... +info: Entering event queue @ 74000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 75000004000. Starting simulation... +info: Entering event queue @ 75000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 76000004000. Starting simulation... +info: Entering event queue @ 76000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 77000004000. Starting simulation... +info: Entering event queue @ 77000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 78000004000. Starting simulation... +info: Entering event queue @ 78000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 79000004000. Starting simulation... +info: Entering event queue @ 79000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 80000004000. Starting simulation... +info: Entering event queue @ 80000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 81000004000. Starting simulation... +info: Entering event queue @ 81000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 82000004000. Starting simulation... +info: Entering event queue @ 82000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 83000004000. Starting simulation... +info: Entering event queue @ 83000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 84000004000. Starting simulation... +info: Entering event queue @ 84000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 85000004000. Starting simulation... +info: Entering event queue @ 85000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 86000004000. Starting simulation... +info: Entering event queue @ 86000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 87000004000. Starting simulation... +info: Entering event queue @ 87000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 88000004000. Starting simulation... +info: Entering event queue @ 88000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 89000004000. Starting simulation... +info: Entering event queue @ 89000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 90000004000. Starting simulation... +info: Entering event queue @ 90000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 91000004000. Starting simulation... +info: Entering event queue @ 91000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 92000004000. Starting simulation... +info: Entering event queue @ 92000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 93000004000. Starting simulation... +info: Entering event queue @ 93000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 94000004000. Starting simulation... +info: Entering event queue @ 94000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 95000004000. Starting simulation... +info: Entering event queue @ 95000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 96000004000. Starting simulation... +info: Entering event queue @ 96000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 97000004000. Starting simulation... +info: Entering event queue @ 97000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 98000004000. Starting simulation... +info: Entering event queue @ 98000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 99000004000. Starting simulation... +info: Entering event queue @ 99000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 100000004000. Starting simulation... +info: Entering event queue @ 100000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 101000004000. Starting simulation... +info: Entering event queue @ 101000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 102000004000. Starting simulation... +info: Entering event queue @ 102000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 103000004000. Starting simulation... +info: Entering event queue @ 103000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 104000004000. Starting simulation... +info: Entering event queue @ 104000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 105000004000. Starting simulation... +info: Entering event queue @ 105000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 106000004000. Starting simulation... +info: Entering event queue @ 106000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 107000004000. Starting simulation... +info: Entering event queue @ 107000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 108000004000. Starting simulation... +info: Entering event queue @ 108000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 109000004000. Starting simulation... +info: Entering event queue @ 109000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 110000004000. Starting simulation... +info: Entering event queue @ 110000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 111000004000. Starting simulation... +info: Entering event queue @ 111000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 112000004000. Starting simulation... +info: Entering event queue @ 112000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 113000004000. Starting simulation... +info: Entering event queue @ 113000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 114000004000. Starting simulation... +info: Entering event queue @ 114000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 115000004000. Starting simulation... +info: Entering event queue @ 115000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 116000004000. Starting simulation... +info: Entering event queue @ 116000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 117000004000. Starting simulation... +info: Entering event queue @ 117000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 118000004000. Starting simulation... +info: Entering event queue @ 118000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 119000004000. Starting simulation... +info: Entering event queue @ 119000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 120000004000. Starting simulation... +info: Entering event queue @ 120000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 121000004000. Starting simulation... +info: Entering event queue @ 121000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 122000004000. Starting simulation... +info: Entering event queue @ 122000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 123000004000. Starting simulation... +info: Entering event queue @ 123000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 124000004000. Starting simulation... +info: Entering event queue @ 124000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 125000004000. Starting simulation... +info: Entering event queue @ 125000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 126000004000. Starting simulation... +info: Entering event queue @ 126000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 127000004000. Starting simulation... +info: Entering event queue @ 127000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 128000004000. Starting simulation... +info: Entering event queue @ 128000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 129000004000. Starting simulation... +info: Entering event queue @ 129000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 130000004000. Starting simulation... +info: Entering event queue @ 130000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 131000004000. Starting simulation... +info: Entering event queue @ 131000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 132000004000. Starting simulation... +info: Entering event queue @ 132000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 133000004000. Starting simulation... +info: Entering event queue @ 133000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 134000004000. Starting simulation... +info: Entering event queue @ 134000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 135000004000. Starting simulation... +info: Entering event queue @ 135000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 136000004000. Starting simulation... +info: Entering event queue @ 136000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 137000004000. Starting simulation... +info: Entering event queue @ 137000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 138000004000. Starting simulation... +info: Entering event queue @ 138000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 139000004000. Starting simulation... +info: Entering event queue @ 139000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 140000004000. Starting simulation... +info: Entering event queue @ 140000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 141000004000. Starting simulation... +info: Entering event queue @ 141000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 142000004000. Starting simulation... +info: Entering event queue @ 142000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 143000004000. Starting simulation... +info: Entering event queue @ 143000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 144000004000. Starting simulation... +info: Entering event queue @ 144000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 145000004000. Starting simulation... +info: Entering event queue @ 145000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 146000004000. Starting simulation... +info: Entering event queue @ 146000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 147000004000. Starting simulation... +info: Entering event queue @ 147000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 148000004000. Starting simulation... +info: Entering event queue @ 148000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 149000004000. Starting simulation... +info: Entering event queue @ 149000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 150000004000. Starting simulation... +info: Entering event queue @ 150000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 151000004000. Starting simulation... +info: Entering event queue @ 151000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 152000004000. Starting simulation... +info: Entering event queue @ 152000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 153000004000. Starting simulation... +info: Entering event queue @ 153000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 154000004000. Starting simulation... +info: Entering event queue @ 154000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 155000004000. Starting simulation... +info: Entering event queue @ 155000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 156000004000. Starting simulation... +info: Entering event queue @ 156000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 157000004000. Starting simulation... +info: Entering event queue @ 157000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 158000004000. Starting simulation... +info: Entering event queue @ 158000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 159000004000. Starting simulation... +info: Entering event queue @ 159000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 160000004000. Starting simulation... +info: Entering event queue @ 160000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 161000004000. Starting simulation... +info: Entering event queue @ 161000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 162000004000. Starting simulation... +info: Entering event queue @ 162000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 163000004000. Starting simulation... +info: Entering event queue @ 163000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 164000004000. Starting simulation... +info: Entering event queue @ 164000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 165000004000. Starting simulation... +info: Entering event queue @ 165000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 166000004000. Starting simulation... +info: Entering event queue @ 166000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 167000004000. Starting simulation... +info: Entering event queue @ 167000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 168000004000. Starting simulation... +info: Entering event queue @ 168000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 169000004000. Starting simulation... +info: Entering event queue @ 169000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 170000004000. Starting simulation... +info: Entering event queue @ 170000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 171000004000. Starting simulation... +info: Entering event queue @ 171000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 172000004000. Starting simulation... +info: Entering event queue @ 172000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 173000004000. Starting simulation... +info: Entering event queue @ 173000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 174000004000. Starting simulation... +info: Entering event queue @ 174000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 175000004000. Starting simulation... +info: Entering event queue @ 175000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 176000004000. Starting simulation... +info: Entering event queue @ 176000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 177000004000. Starting simulation... +info: Entering event queue @ 177000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 178000004000. Starting simulation... +info: Entering event queue @ 178000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 179000004000. Starting simulation... +info: Entering event queue @ 179000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 180000004000. Starting simulation... +info: Entering event queue @ 180000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 181000004000. Starting simulation... +info: Entering event queue @ 181000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 182000004000. Starting simulation... +info: Entering event queue @ 182000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 183000004000. Starting simulation... +info: Entering event queue @ 183000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 184000004000. Starting simulation... +info: Entering event queue @ 184000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 185000004000. Starting simulation... +info: Entering event queue @ 185000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 186000004000. Starting simulation... +info: Entering event queue @ 186000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 187000004000. Starting simulation... +info: Entering event queue @ 187000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 188000004000. Starting simulation... +info: Entering event queue @ 188000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 189000004000. Starting simulation... +info: Entering event queue @ 189000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 190000004000. Starting simulation... +info: Entering event queue @ 190000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 191000004000. Starting simulation... +info: Entering event queue @ 191000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 192000004000. Starting simulation... +info: Entering event queue @ 192000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 193000004000. Starting simulation... +info: Entering event queue @ 193000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 194000004000. Starting simulation... +info: Entering event queue @ 194000010500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU +info: Entering event queue @ 195000010500. Starting simulation... switching cpus -info: Entering event queue @ 195000004000. Starting simulation... +info: Entering event queue @ 195000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 196000004000. Starting simulation... +info: Entering event queue @ 196000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 197000004000. Starting simulation... +info: Entering event queue @ 197000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 198000004000. Starting simulation... +info: Entering event queue @ 198000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 199000004000. Starting simulation... +info: Entering event queue @ 199000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 200000004000. Starting simulation... +info: Entering event queue @ 200000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 201000004000. Starting simulation... +info: Entering event queue @ 201000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 202000004000. Starting simulation... +info: Entering event queue @ 202000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 203000004000. Starting simulation... +info: Entering event queue @ 203000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 204000004000. Starting simulation... +info: Entering event queue @ 204000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 205000004000. Starting simulation... +info: Entering event queue @ 205000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 206000004000. Starting simulation... +info: Entering event queue @ 206000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 207000004000. Starting simulation... +info: Entering event queue @ 207000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 208000004000. Starting simulation... +info: Entering event queue @ 208000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 209000004000. Starting simulation... +info: Entering event queue @ 209000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 210000004000. Starting simulation... +info: Entering event queue @ 210000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 211000004000. Starting simulation... +info: Entering event queue @ 211000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 212000004000. Starting simulation... +info: Entering event queue @ 212000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 213000004000. Starting simulation... +info: Entering event queue @ 213000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 214000004000. Starting simulation... +info: Entering event queue @ 214000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 215000004000. Starting simulation... +info: Entering event queue @ 215000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 216000004000. Starting simulation... +info: Entering event queue @ 216000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 217000004000. Starting simulation... +info: Entering event queue @ 217000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 218000004000. Starting simulation... +info: Entering event queue @ 218000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 219000004000. Starting simulation... +info: Entering event queue @ 219000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 220000004000. Starting simulation... +info: Entering event queue @ 220000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 221000004000. Starting simulation... +info: Entering event queue @ 221000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 222000004000. Starting simulation... +info: Entering event queue @ 222000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 223000004000. Starting simulation... +info: Entering event queue @ 223000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 224000004000. Starting simulation... +info: Entering event queue @ 224000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 225000004000. Starting simulation... +info: Entering event queue @ 225000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 226000004000. Starting simulation... +info: Entering event queue @ 226000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 227000004000. Starting simulation... +info: Entering event queue @ 227000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 228000004000. Starting simulation... +info: Entering event queue @ 228000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 229000004000. Starting simulation... +info: Entering event queue @ 229000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 230000004000. Starting simulation... +info: Entering event queue @ 230000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 231000004000. Starting simulation... +info: Entering event queue @ 231000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 232000004000. Starting simulation... +info: Entering event queue @ 232000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 233000004000. Starting simulation... +info: Entering event queue @ 233000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 234000004000. Starting simulation... +info: Entering event queue @ 234000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 235000004000. Starting simulation... +info: Entering event queue @ 235000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 236000004000. Starting simulation... +info: Entering event queue @ 236000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 237000004000. Starting simulation... +info: Entering event queue @ 237000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 238000004000. Starting simulation... +info: Entering event queue @ 238000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 239000004000. Starting simulation... +info: Entering event queue @ 239000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 240000004000. Starting simulation... +info: Entering event queue @ 240000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 241000004000. Starting simulation... +info: Entering event queue @ 241000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 242000004000. Starting simulation... +info: Entering event queue @ 242000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 243000004000. Starting simulation... +info: Entering event queue @ 243000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 244000004000. Starting simulation... +info: Entering event queue @ 244000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 245000004000. Starting simulation... +info: Entering event queue @ 245000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 246000004000. Starting simulation... +info: Entering event queue @ 246000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 247000004000. Starting simulation... +info: Entering event queue @ 247000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 248000004000. Starting simulation... +info: Entering event queue @ 248000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 249000004000. Starting simulation... +info: Entering event queue @ 249000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 250000004000. Starting simulation... +info: Entering event queue @ 250000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 251000004000. Starting simulation... +info: Entering event queue @ 251000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 252000004000. Starting simulation... +info: Entering event queue @ 252000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 253000004000. Starting simulation... +info: Entering event queue @ 253000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 254000004000. Starting simulation... +info: Entering event queue @ 254000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 255000004000. Starting simulation... +info: Entering event queue @ 255000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 256000004000. Starting simulation... +info: Entering event queue @ 256000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 257000004000. Starting simulation... +info: Entering event queue @ 257000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 258000004000. Starting simulation... +info: Entering event queue @ 258000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 259000004000. Starting simulation... +info: Entering event queue @ 259000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 260000004000. Starting simulation... +info: Entering event queue @ 260000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 261000004000. Starting simulation... +info: Entering event queue @ 261000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 262000004000. Starting simulation... +info: Entering event queue @ 262000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 263000004000. Starting simulation... +info: Entering event queue @ 263000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 264000004000. Starting simulation... +info: Entering event queue @ 264000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 265000004000. Starting simulation... +info: Entering event queue @ 265000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 266000004000. Starting simulation... +info: Entering event queue @ 266000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 267000004000. Starting simulation... +info: Entering event queue @ 267000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 268000004000. Starting simulation... +info: Entering event queue @ 268000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 269000004000. Starting simulation... +info: Entering event queue @ 269000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 270000004000. Starting simulation... +info: Entering event queue @ 270000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 271000004000. Starting simulation... +info: Entering event queue @ 271000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 272000004000. Starting simulation... +info: Entering event queue @ 272000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 273000004000. Starting simulation... +info: Entering event queue @ 273000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 274000004000. Starting simulation... +info: Entering event queue @ 274000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 275000004000. Starting simulation... +info: Entering event queue @ 275000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 276000004000. Starting simulation... +info: Entering event queue @ 276000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 277000004000. Starting simulation... +info: Entering event queue @ 277000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 278000004000. Starting simulation... +info: Entering event queue @ 278000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 279000004000. Starting simulation... +info: Entering event queue @ 279000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 280000004000. Starting simulation... +info: Entering event queue @ 280000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 281000004000. Starting simulation... +info: Entering event queue @ 281000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 282000004000. Starting simulation... +info: Entering event queue @ 282000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 283000004000. Starting simulation... +info: Entering event queue @ 283000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 284000004000. Starting simulation... +info: Entering event queue @ 284000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 285000004000. Starting simulation... +info: Entering event queue @ 285000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 286000004000. Starting simulation... +info: Entering event queue @ 286000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 287000004000. Starting simulation... +info: Entering event queue @ 287000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 288000004000. Starting simulation... +info: Entering event queue @ 288000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 289000004000. Starting simulation... +info: Entering event queue @ 289000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 290000004000. Starting simulation... +info: Entering event queue @ 290000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 291000004000. Starting simulation... +info: Entering event queue @ 291000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 292000004000. Starting simulation... +info: Entering event queue @ 292000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 293000004000. Starting simulation... +info: Entering event queue @ 293000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 294000004000. Starting simulation... +info: Entering event queue @ 294000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 295000004000. Starting simulation... +info: Entering event queue @ 295000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 296000004000. Starting simulation... +info: Entering event queue @ 296000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 297000004000. Starting simulation... +info: Entering event queue @ 297000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 298000004000. Starting simulation... +info: Entering event queue @ 298000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 299000004000. Starting simulation... +info: Entering event queue @ 299000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 300000004000. Starting simulation... +info: Entering event queue @ 300000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 301000004000. Starting simulation... +info: Entering event queue @ 301000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 302000004000. Starting simulation... +info: Entering event queue @ 302000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 303000004000. Starting simulation... +info: Entering event queue @ 303000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 304000004000. Starting simulation... +info: Entering event queue @ 304000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 305000004000. Starting simulation... +info: Entering event queue @ 305000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 306000004000. Starting simulation... +info: Entering event queue @ 306000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 307000004000. Starting simulation... +info: Entering event queue @ 307000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 308000004000. Starting simulation... +info: Entering event queue @ 308000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 309000004000. Starting simulation... +info: Entering event queue @ 309000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 310000004000. Starting simulation... +info: Entering event queue @ 310000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 311000004000. Starting simulation... +info: Entering event queue @ 311000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 312000004000. Starting simulation... +info: Entering event queue @ 312000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 313000004000. Starting simulation... +info: Entering event queue @ 313000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 314000004000. Starting simulation... +info: Entering event queue @ 314000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 315000004000. Starting simulation... +info: Entering event queue @ 315000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 316000004000. Starting simulation... +info: Entering event queue @ 316000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 317000004000. Starting simulation... +info: Entering event queue @ 317000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 318000004000. Starting simulation... +info: Entering event queue @ 318000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 319000004000. Starting simulation... +info: Entering event queue @ 319000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 320000004000. Starting simulation... +info: Entering event queue @ 320000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 321000004000. Starting simulation... +info: Entering event queue @ 321000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 322000004000. Starting simulation... +info: Entering event queue @ 322000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 323000004000. Starting simulation... +info: Entering event queue @ 323000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 324000004000. Starting simulation... +info: Entering event queue @ 324000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 325000004000. Starting simulation... +info: Entering event queue @ 325000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 326000004000. Starting simulation... +info: Entering event queue @ 326000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 327000004000. Starting simulation... +info: Entering event queue @ 327000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 328000004000. Starting simulation... +info: Entering event queue @ 328000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 329000004000. Starting simulation... +info: Entering event queue @ 329000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 330000004000. Starting simulation... +info: Entering event queue @ 330000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 331000004000. Starting simulation... +info: Entering event queue @ 331000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 332000004000. Starting simulation... +info: Entering event queue @ 332000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 333000004000. Starting simulation... +info: Entering event queue @ 333000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 334000004000. Starting simulation... +info: Entering event queue @ 334000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 335000004000. Starting simulation... +info: Entering event queue @ 335000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 336000004000. Starting simulation... +info: Entering event queue @ 336000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 337000004000. Starting simulation... +info: Entering event queue @ 337000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 338000004000. Starting simulation... +info: Entering event queue @ 338000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 339000004000. Starting simulation... +info: Entering event queue @ 339000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 340000004000. Starting simulation... +info: Entering event queue @ 340000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 341000004000. Starting simulation... +info: Entering event queue @ 341000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 342000004000. Starting simulation... +info: Entering event queue @ 342000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 343000004000. Starting simulation... +info: Entering event queue @ 343000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 344000004000. Starting simulation... +info: Entering event queue @ 344000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 345000004000. Starting simulation... +info: Entering event queue @ 345000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 346000004000. Starting simulation... +info: Entering event queue @ 346000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 347000004000. Starting simulation... +info: Entering event queue @ 347000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 348000004000. Starting simulation... +info: Entering event queue @ 348000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 349000004000. Starting simulation... +info: Entering event queue @ 349000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 350000004000. Starting simulation... +info: Entering event queue @ 350000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 351000004000. Starting simulation... +info: Entering event queue @ 351000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 352000004000. Starting simulation... +info: Entering event queue @ 352000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 353000004000. Starting simulation... +info: Entering event queue @ 353000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 354000004000. Starting simulation... +info: Entering event queue @ 354000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 355000004000. Starting simulation... +info: Entering event queue @ 355000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 356000004000. Starting simulation... +info: Entering event queue @ 356000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 357000004000. Starting simulation... +info: Entering event queue @ 357000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 358000004000. Starting simulation... +info: Entering event queue @ 358000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 359000004000. Starting simulation... +info: Entering event queue @ 359000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 360000004000. Starting simulation... +info: Entering event queue @ 360000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 361000004000. Starting simulation... +info: Entering event queue @ 361000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 362000004000. Starting simulation... +info: Entering event queue @ 362000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 363000004000. Starting simulation... +info: Entering event queue @ 363000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 364000004000. Starting simulation... +info: Entering event queue @ 364000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 365000004000. Starting simulation... +info: Entering event queue @ 365000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 366000004000. Starting simulation... +info: Entering event queue @ 366000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 367000004000. Starting simulation... +info: Entering event queue @ 367000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 368000004000. Starting simulation... +info: Entering event queue @ 368000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 369000004000. Starting simulation... +info: Entering event queue @ 369000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 370000004000. Starting simulation... +info: Entering event queue @ 370000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 371000004000. Starting simulation... +info: Entering event queue @ 371000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 372000004000. Starting simulation... +info: Entering event queue @ 372000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 373000004000. Starting simulation... +info: Entering event queue @ 373000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 374000004000. Starting simulation... +info: Entering event queue @ 374000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 375000004000. Starting simulation... +info: Entering event queue @ 375000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 376000004000. Starting simulation... +info: Entering event queue @ 376000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 377000004000. Starting simulation... +info: Entering event queue @ 377000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 378000004000. Starting simulation... +info: Entering event queue @ 378000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 379000004000. Starting simulation... +info: Entering event queue @ 379000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 380000004000. Starting simulation... +info: Entering event queue @ 380000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 381000004000. Starting simulation... +info: Entering event queue @ 381000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 382000004000. Starting simulation... +info: Entering event queue @ 382000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 383000004000. Starting simulation... +info: Entering event queue @ 383000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 384000004000. Starting simulation... +info: Entering event queue @ 384000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 385000004000. Starting simulation... +info: Entering event queue @ 385000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 386000004000. Starting simulation... +info: Entering event queue @ 386000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 387000004000. Starting simulation... +info: Entering event queue @ 387000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 388000004000. Starting simulation... +info: Entering event queue @ 388000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 389000004000. Starting simulation... +info: Entering event queue @ 389000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 390000004000. Starting simulation... +info: Entering event queue @ 390000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 391000004000. Starting simulation... +info: Entering event queue @ 391000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 392000004000. Starting simulation... +info: Entering event queue @ 392000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 393000004000. Starting simulation... +info: Entering event queue @ 393000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 394000004000. Starting simulation... +info: Entering event queue @ 394000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 395000004000. Starting simulation... +info: Entering event queue @ 395000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 396000004000. Starting simulation... +info: Entering event queue @ 396000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 397000004000. Starting simulation... +info: Entering event queue @ 397000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 398000004000. Starting simulation... +info: Entering event queue @ 398000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 399000004000. Starting simulation... +info: Entering event queue @ 399000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 400000004000. Starting simulation... +info: Entering event queue @ 400000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 401000004000. Starting simulation... +info: Entering event queue @ 401000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 402000004000. Starting simulation... +info: Entering event queue @ 402000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 403000004000. Starting simulation... +info: Entering event queue @ 403000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 404000004000. Starting simulation... +info: Entering event queue @ 404000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 405000004000. Starting simulation... +info: Entering event queue @ 405000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 406000004000. Starting simulation... +info: Entering event queue @ 406000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 407000004000. Starting simulation... +info: Entering event queue @ 407000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 408000004000. Starting simulation... +info: Entering event queue @ 408000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 409000004000. Starting simulation... +info: Entering event queue @ 409000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 410000004000. Starting simulation... +info: Entering event queue @ 410000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 411000004000. Starting simulation... +info: Entering event queue @ 411000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 412000004000. Starting simulation... +info: Entering event queue @ 412000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 413000004000. Starting simulation... +info: Entering event queue @ 413000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 414000004000. Starting simulation... +info: Entering event queue @ 414000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 415000004000. Starting simulation... +info: Entering event queue @ 415000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 416000004000. Starting simulation... +info: Entering event queue @ 416000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 417000004000. Starting simulation... +info: Entering event queue @ 417000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 418000004000. Starting simulation... +info: Entering event queue @ 418000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 419000004000. Starting simulation... +info: Entering event queue @ 419000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 420000004000. Starting simulation... +info: Entering event queue @ 420000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 421000004000. Starting simulation... +info: Entering event queue @ 421000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 422000004000. Starting simulation... +info: Entering event queue @ 422000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 423000004000. Starting simulation... +info: Entering event queue @ 423000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 424000004000. Starting simulation... +info: Entering event queue @ 424000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 425000004000. Starting simulation... +info: Entering event queue @ 425000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 426000004000. Starting simulation... +info: Entering event queue @ 426000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 427000004000. Starting simulation... +info: Entering event queue @ 427000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 428000004000. Starting simulation... +info: Entering event queue @ 428000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 429000004000. Starting simulation... +info: Entering event queue @ 429000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 430000004000. Starting simulation... +info: Entering event queue @ 430000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 431000004000. Starting simulation... +info: Entering event queue @ 431000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 432000004000. Starting simulation... +info: Entering event queue @ 432000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 433000004000. Starting simulation... +info: Entering event queue @ 433000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 434000004000. Starting simulation... +info: Entering event queue @ 434000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 435000004000. Starting simulation... +info: Entering event queue @ 435000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 436000004000. Starting simulation... +info: Entering event queue @ 436000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 437000004000. Starting simulation... +info: Entering event queue @ 437000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 438000004000. Starting simulation... +info: Entering event queue @ 438000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 439000004000. Starting simulation... +info: Entering event queue @ 439000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 440000004000. Starting simulation... +info: Entering event queue @ 440000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 441000004000. Starting simulation... +info: Entering event queue @ 441000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 442000004000. Starting simulation... +info: Entering event queue @ 442000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 443000004000. Starting simulation... +info: Entering event queue @ 443000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 444000004000. Starting simulation... +info: Entering event queue @ 444000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 445000004000. Starting simulation... +info: Entering event queue @ 445000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 446000004000. Starting simulation... +info: Entering event queue @ 446000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 447000004000. Starting simulation... +info: Entering event queue @ 447000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 448000004000. Starting simulation... +info: Entering event queue @ 448000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 449000004000. Starting simulation... +info: Entering event queue @ 449000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 450000004000. Starting simulation... +info: Entering event queue @ 450000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 451000004000. Starting simulation... +info: Entering event queue @ 451000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 452000004000. Starting simulation... +info: Entering event queue @ 452000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 453000004000. Starting simulation... +info: Entering event queue @ 453000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 454000004000. Starting simulation... +info: Entering event queue @ 454000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 455000004000. Starting simulation... +info: Entering event queue @ 455000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 456000004000. Starting simulation... +info: Entering event queue @ 456000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 457000004000. Starting simulation... +info: Entering event queue @ 457000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 458000004000. Starting simulation... +info: Entering event queue @ 458000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 459000004000. Starting simulation... +info: Entering event queue @ 459000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 460000004000. Starting simulation... +info: Entering event queue @ 460000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 461000004000. Starting simulation... +info: Entering event queue @ 461000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 462000004000. Starting simulation... +info: Entering event queue @ 462000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 463000004000. Starting simulation... +info: Entering event queue @ 463000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 464000004000. Starting simulation... +info: Entering event queue @ 464000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 465000004000. Starting simulation... +info: Entering event queue @ 465000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 466000004000. Starting simulation... +info: Entering event queue @ 466000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 467000004000. Starting simulation... +info: Entering event queue @ 467000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 468000004000. Starting simulation... +info: Entering event queue @ 468000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 469000004000. Starting simulation... +info: Entering event queue @ 469000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 470000004000. Starting simulation... +info: Entering event queue @ 470000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 471000004000. Starting simulation... +info: Entering event queue @ 471000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 472000004000. Starting simulation... +info: Entering event queue @ 472000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 473000004000. Starting simulation... +info: Entering event queue @ 473000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 474000004000. Starting simulation... +info: Entering event queue @ 474000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 475000004000. Starting simulation... +info: Entering event queue @ 475000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 476000004000. Starting simulation... +info: Entering event queue @ 476000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 477000004000. Starting simulation... +info: Entering event queue @ 477000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 478000004000. Starting simulation... +info: Entering event queue @ 478000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 479000004000. Starting simulation... +info: Entering event queue @ 479000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 480000004000. Starting simulation... +info: Entering event queue @ 480000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 481000004000. Starting simulation... +info: Entering event queue @ 481000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 482000004000. Starting simulation... +info: Entering event queue @ 482000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 483000004000. Starting simulation... +info: Entering event queue @ 483000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 484000004000. Starting simulation... +info: Entering event queue @ 484000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 485000004000. Starting simulation... +info: Entering event queue @ 485000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 486000004000. Starting simulation... +info: Entering event queue @ 486000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 487000004000. Starting simulation... +info: Entering event queue @ 487000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 488000004000. Starting simulation... +info: Entering event queue @ 488000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 489000004000. Starting simulation... +info: Entering event queue @ 489000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 490000004000. Starting simulation... +info: Entering event queue @ 490000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 491000004000. Starting simulation... +info: Entering event queue @ 491000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 492000004000. Starting simulation... +info: Entering event queue @ 492000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 493000004000. Starting simulation... +info: Entering event queue @ 493000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 494000004000. Starting simulation... +info: Entering event queue @ 494000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 495000004000. Starting simulation... +info: Entering event queue @ 495000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 496000004000. Starting simulation... +info: Entering event queue @ 496000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 497000004000. Starting simulation... +info: Entering event queue @ 497000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 498000004000. Starting simulation... +info: Entering event queue @ 498000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 499000004000. Starting simulation... +info: Entering event queue @ 499000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 500000004000. Starting simulation... +info: Entering event queue @ 500000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 501000004000. Starting simulation... +info: Entering event queue @ 501000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 502000004000. Starting simulation... +info: Entering event queue @ 502000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 503000004000. Starting simulation... +info: Entering event queue @ 503000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 504000004000. Starting simulation... +info: Entering event queue @ 504000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 505000004000. Starting simulation... +info: Entering event queue @ 505000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 506000004000. Starting simulation... +info: Entering event queue @ 506000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 507000004000. Starting simulation... +info: Entering event queue @ 507000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 508000004000. Starting simulation... +info: Entering event queue @ 508000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 509000004000. Starting simulation... +info: Entering event queue @ 509000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 510000004000. Starting simulation... +info: Entering event queue @ 510000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 511000004000. Starting simulation... +info: Entering event queue @ 511000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 512000004000. Starting simulation... +info: Entering event queue @ 512000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 513000004000. Starting simulation... +info: Entering event queue @ 513000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 514000004000. Starting simulation... +info: Entering event queue @ 514000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 515000004000. Starting simulation... +info: Entering event queue @ 515000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 516000004000. Starting simulation... +info: Entering event queue @ 516000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 517000004000. Starting simulation... +info: Entering event queue @ 517000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 518000004000. Starting simulation... +info: Entering event queue @ 518000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 519000004000. Starting simulation... +info: Entering event queue @ 519000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 520000004000. Starting simulation... +info: Entering event queue @ 520000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 521000004000. Starting simulation... +info: Entering event queue @ 521000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 522000004000. Starting simulation... +info: Entering event queue @ 522000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 523000004000. Starting simulation... +info: Entering event queue @ 523000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 524000004000. Starting simulation... +info: Entering event queue @ 524000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 525000004000. Starting simulation... +info: Entering event queue @ 525000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 526000004000. Starting simulation... +info: Entering event queue @ 526000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 527000004000. Starting simulation... +info: Entering event queue @ 527000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 528000004000. Starting simulation... +info: Entering event queue @ 528000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 529000004000. Starting simulation... +info: Entering event queue @ 529000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 530000004000. Starting simulation... +info: Entering event queue @ 530000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 531000004000. Starting simulation... +info: Entering event queue @ 531000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 532000004000. Starting simulation... +info: Entering event queue @ 532000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 533000004000. Starting simulation... +info: Entering event queue @ 533000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 534000004000. Starting simulation... +info: Entering event queue @ 534000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 535000004000. Starting simulation... +info: Entering event queue @ 535000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 536000004000. Starting simulation... +info: Entering event queue @ 536000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 537000004000. Starting simulation... +info: Entering event queue @ 537000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 538000004000. Starting simulation... +info: Entering event queue @ 538000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 539000004000. Starting simulation... +info: Entering event queue @ 539000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 540000004000. Starting simulation... +info: Entering event queue @ 540000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 541000004000. Starting simulation... +info: Entering event queue @ 541000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 542000004000. Starting simulation... +info: Entering event queue @ 542000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 543000004000. Starting simulation... +info: Entering event queue @ 543000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 544000004000. Starting simulation... +info: Entering event queue @ 544000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 545000004000. Starting simulation... +info: Entering event queue @ 545000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 546000004000. Starting simulation... +info: Entering event queue @ 546000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 547000004000. Starting simulation... +info: Entering event queue @ 547000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 548000004000. Starting simulation... +info: Entering event queue @ 548000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 549000004000. Starting simulation... +info: Entering event queue @ 549000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 550000004000. Starting simulation... +info: Entering event queue @ 550000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 551000004000. Starting simulation... +info: Entering event queue @ 551000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 552000004000. Starting simulation... +info: Entering event queue @ 552000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 553000004000. Starting simulation... +info: Entering event queue @ 553000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 554000004000. Starting simulation... +info: Entering event queue @ 554000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 555000004000. Starting simulation... +info: Entering event queue @ 555000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 556000004000. Starting simulation... +info: Entering event queue @ 556000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 557000004000. Starting simulation... +info: Entering event queue @ 557000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 558000004000. Starting simulation... +info: Entering event queue @ 558000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 559000004000. Starting simulation... +info: Entering event queue @ 559000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 560000004000. Starting simulation... +info: Entering event queue @ 560000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 561000004000. Starting simulation... +info: Entering event queue @ 561000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 562000004000. Starting simulation... +info: Entering event queue @ 562000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 563000004000. Starting simulation... +info: Entering event queue @ 563000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 564000004000. Starting simulation... +info: Entering event queue @ 564000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 565000004000. Starting simulation... +info: Entering event queue @ 565000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 566000004000. Starting simulation... +info: Entering event queue @ 566000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 567000004000. Starting simulation... +info: Entering event queue @ 567000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 568000004000. Starting simulation... +info: Entering event queue @ 568000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 569000004000. Starting simulation... +info: Entering event queue @ 569000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 570000004000. Starting simulation... +info: Entering event queue @ 570000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 571000004000. Starting simulation... +info: Entering event queue @ 571000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 572000004000. Starting simulation... +info: Entering event queue @ 572000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 573000004000. Starting simulation... +info: Entering event queue @ 573000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 574000004000. Starting simulation... +info: Entering event queue @ 574000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 575000004000. Starting simulation... +info: Entering event queue @ 575000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 576000004000. Starting simulation... +info: Entering event queue @ 576000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 577000004000. Starting simulation... +info: Entering event queue @ 577000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 578000004000. Starting simulation... +info: Entering event queue @ 578000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 579000004000. Starting simulation... +info: Entering event queue @ 579000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 580000004000. Starting simulation... +info: Entering event queue @ 580000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 581000004000. Starting simulation... +info: Entering event queue @ 581000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 582000004000. Starting simulation... +info: Entering event queue @ 582000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 583000004000. Starting simulation... +info: Entering event queue @ 583000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 584000004000. Starting simulation... +info: Entering event queue @ 584000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 585000004000. Starting simulation... +info: Entering event queue @ 585000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 586000004000. Starting simulation... +info: Entering event queue @ 586000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 587000004000. Starting simulation... +info: Entering event queue @ 587000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 588000004000. Starting simulation... +info: Entering event queue @ 588000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 589000004000. Starting simulation... +info: Entering event queue @ 589000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 590000004000. Starting simulation... +info: Entering event queue @ 590000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 591000004000. Starting simulation... +info: Entering event queue @ 591000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 592000004000. Starting simulation... +info: Entering event queue @ 592000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 593000004000. Starting simulation... +info: Entering event queue @ 593000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 594000004000. Starting simulation... +info: Entering event queue @ 594000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 595000004000. Starting simulation... +info: Entering event queue @ 595000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 596000004000. Starting simulation... +info: Entering event queue @ 596000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 597000004000. Starting simulation... +info: Entering event queue @ 597000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 598000004000. Starting simulation... +info: Entering event queue @ 598000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 599000004000. Starting simulation... +info: Entering event queue @ 599000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 600000004000. Starting simulation... +info: Entering event queue @ 600000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 601000004000. Starting simulation... +info: Entering event queue @ 601000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 602000004000. Starting simulation... +info: Entering event queue @ 602000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 603000004000. Starting simulation... +info: Entering event queue @ 603000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 604000004000. Starting simulation... +info: Entering event queue @ 604000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 605000004000. Starting simulation... +info: Entering event queue @ 605000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 606000004000. Starting simulation... +info: Entering event queue @ 606000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 607000004000. Starting simulation... +info: Entering event queue @ 607000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 608000004000. Starting simulation... +info: Entering event queue @ 608000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 609000004000. Starting simulation... +info: Entering event queue @ 609000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 610000004000. Starting simulation... +info: Entering event queue @ 610000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 611000004000. Starting simulation... +info: Entering event queue @ 611000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 612000004000. Starting simulation... +info: Entering event queue @ 612000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 613000004000. Starting simulation... +info: Entering event queue @ 613000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 614000004000. Starting simulation... +info: Entering event queue @ 614000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 615000004000. Starting simulation... +info: Entering event queue @ 615000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 616000004000. Starting simulation... +info: Entering event queue @ 616000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 617000004000. Starting simulation... +info: Entering event queue @ 617000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 618000004000. Starting simulation... +info: Entering event queue @ 618000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 619000004000. Starting simulation... +info: Entering event queue @ 619000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 620000004000. Starting simulation... +info: Entering event queue @ 620000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 621000004000. Starting simulation... +info: Entering event queue @ 621000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 622000004000. Starting simulation... +info: Entering event queue @ 622000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 623000004000. Starting simulation... +info: Entering event queue @ 623000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 624000004000. Starting simulation... +info: Entering event queue @ 624000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 625000004000. Starting simulation... +info: Entering event queue @ 625000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 626000004000. Starting simulation... +info: Entering event queue @ 626000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 627000004000. Starting simulation... +info: Entering event queue @ 627000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 628000004000. Starting simulation... +info: Entering event queue @ 628000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 629000004000. Starting simulation... +info: Entering event queue @ 629000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 630000004000. Starting simulation... +info: Entering event queue @ 630000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 631000004000. Starting simulation... +info: Entering event queue @ 631000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 632000004000. Starting simulation... +info: Entering event queue @ 632000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 633000004000. Starting simulation... +info: Entering event queue @ 633000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 634000004000. Starting simulation... +info: Entering event queue @ 634000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 635000004000. Starting simulation... +info: Entering event queue @ 635000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 636000004000. Starting simulation... +info: Entering event queue @ 636000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 637000004000. Starting simulation... +info: Entering event queue @ 637000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 638000004000. Starting simulation... +info: Entering event queue @ 638000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 639000004000. Starting simulation... +info: Entering event queue @ 639000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 640000004000. Starting simulation... +info: Entering event queue @ 640000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 641000004000. Starting simulation... +info: Entering event queue @ 641000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 642000004000. Starting simulation... +info: Entering event queue @ 642000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 643000004000. Starting simulation... +info: Entering event queue @ 643000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 644000004000. Starting simulation... +info: Entering event queue @ 644000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 645000004000. Starting simulation... +info: Entering event queue @ 645000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 646000004000. Starting simulation... +info: Entering event queue @ 646000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 647000004000. Starting simulation... +info: Entering event queue @ 647000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 648000004000. Starting simulation... +info: Entering event queue @ 648000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 649000004000. Starting simulation... +info: Entering event queue @ 649000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 650000004000. Starting simulation... +info: Entering event queue @ 650000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 651000004000. Starting simulation... +info: Entering event queue @ 651000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 652000004000. Starting simulation... +info: Entering event queue @ 652000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 653000004000. Starting simulation... +info: Entering event queue @ 653000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 654000004000. Starting simulation... +info: Entering event queue @ 654000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 655000004000. Starting simulation... +info: Entering event queue @ 655000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 656000004000. Starting simulation... +info: Entering event queue @ 656000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 657000004000. Starting simulation... +info: Entering event queue @ 657000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 658000004000. Starting simulation... +info: Entering event queue @ 658000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 659000004000. Starting simulation... +info: Entering event queue @ 659000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 660000004000. Starting simulation... +info: Entering event queue @ 660000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 661000004000. Starting simulation... +info: Entering event queue @ 661000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 662000004000. Starting simulation... +info: Entering event queue @ 662000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 663000004000. Starting simulation... +info: Entering event queue @ 663000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 664000004000. Starting simulation... +info: Entering event queue @ 664000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 665000004000. Starting simulation... +info: Entering event queue @ 665000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 666000004000. Starting simulation... +info: Entering event queue @ 666000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 667000004000. Starting simulation... +info: Entering event queue @ 667000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 668000004000. Starting simulation... +info: Entering event queue @ 668000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 669000004000. Starting simulation... +info: Entering event queue @ 669000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 670000004000. Starting simulation... +info: Entering event queue @ 670000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 671000004000. Starting simulation... +info: Entering event queue @ 671000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 672000004000. Starting simulation... +info: Entering event queue @ 672000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 673000004000. Starting simulation... +info: Entering event queue @ 673000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 674000004000. Starting simulation... +info: Entering event queue @ 674000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 675000004000. Starting simulation... +info: Entering event queue @ 675000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 676000004000. Starting simulation... +info: Entering event queue @ 676000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 677000004000. Starting simulation... +info: Entering event queue @ 677000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 678000004000. Starting simulation... +info: Entering event queue @ 678000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 679000004000. Starting simulation... +info: Entering event queue @ 679000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 680000004000. Starting simulation... +info: Entering event queue @ 680000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 681000004000. Starting simulation... +info: Entering event queue @ 681000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 682000004000. Starting simulation... +info: Entering event queue @ 682000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 683000004000. Starting simulation... +info: Entering event queue @ 683000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 684000004000. Starting simulation... +info: Entering event queue @ 684000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 685000004000. Starting simulation... +info: Entering event queue @ 685000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 686000004000. Starting simulation... +info: Entering event queue @ 686000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 687000004000. Starting simulation... +info: Entering event queue @ 687000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 688000004000. Starting simulation... +info: Entering event queue @ 688000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 689000004000. Starting simulation... +info: Entering event queue @ 689000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 690000004000. Starting simulation... +info: Entering event queue @ 690000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 691000004000. Starting simulation... +info: Entering event queue @ 691000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 692000004000. Starting simulation... +info: Entering event queue @ 692000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 693000004000. Starting simulation... +info: Entering event queue @ 693000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 694000004000. Starting simulation... +info: Entering event queue @ 694000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 695000004000. Starting simulation... +info: Entering event queue @ 695000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 696000004000. Starting simulation... +info: Entering event queue @ 696000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 697000004000. Starting simulation... +info: Entering event queue @ 697000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 698000004000. Starting simulation... +info: Entering event queue @ 698000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 699000004000. Starting simulation... +info: Entering event queue @ 699000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 700000004000. Starting simulation... +info: Entering event queue @ 700000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 701000004000. Starting simulation... +info: Entering event queue @ 701000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 702000004000. Starting simulation... +info: Entering event queue @ 702000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 703000004000. Starting simulation... +info: Entering event queue @ 703000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 704000004000. Starting simulation... +info: Entering event queue @ 704000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 705000004000. Starting simulation... +info: Entering event queue @ 705000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 706000004000. Starting simulation... +info: Entering event queue @ 706000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 707000004000. Starting simulation... +info: Entering event queue @ 707000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 708000004000. Starting simulation... +info: Entering event queue @ 708000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 709000004000. Starting simulation... +info: Entering event queue @ 709000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 710000004000. Starting simulation... +info: Entering event queue @ 710000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 711000004000. Starting simulation... +info: Entering event queue @ 711000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 712000004000. Starting simulation... +info: Entering event queue @ 712000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 713000004000. Starting simulation... +info: Entering event queue @ 713000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 714000004000. Starting simulation... +info: Entering event queue @ 714000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 715000004000. Starting simulation... +info: Entering event queue @ 715000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 716000004000. Starting simulation... +info: Entering event queue @ 716000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 717000004000. Starting simulation... +info: Entering event queue @ 717000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 718000004000. Starting simulation... +info: Entering event queue @ 718000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 719000004000. Starting simulation... +info: Entering event queue @ 719000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 720000004000. Starting simulation... +info: Entering event queue @ 720000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 721000004000. Starting simulation... +info: Entering event queue @ 721000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 722000004000. Starting simulation... +info: Entering event queue @ 722000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 723000004000. Starting simulation... +info: Entering event queue @ 723000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 724000004000. Starting simulation... +info: Entering event queue @ 724000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 725000004000. Starting simulation... +info: Entering event queue @ 725000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 726000004000. Starting simulation... +info: Entering event queue @ 726000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 727000004000. Starting simulation... +info: Entering event queue @ 727000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 728000004000. Starting simulation... +info: Entering event queue @ 728000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 729000004000. Starting simulation... +info: Entering event queue @ 729000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 730000004000. Starting simulation... +info: Entering event queue @ 730000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 731000004000. Starting simulation... +info: Entering event queue @ 731000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 732000004000. Starting simulation... +info: Entering event queue @ 732000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 733000004000. Starting simulation... +info: Entering event queue @ 733000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 734000004000. Starting simulation... +info: Entering event queue @ 734000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 735000004000. Starting simulation... +info: Entering event queue @ 735000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 736000004000. Starting simulation... +info: Entering event queue @ 736000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 737000004000. Starting simulation... +info: Entering event queue @ 737000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 738000004000. Starting simulation... +info: Entering event queue @ 738000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 739000004000. Starting simulation... +info: Entering event queue @ 739000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 740000004000. Starting simulation... +info: Entering event queue @ 740000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 741000004000. Starting simulation... +info: Entering event queue @ 741000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 742000004000. Starting simulation... +info: Entering event queue @ 742000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 743000004000. Starting simulation... +info: Entering event queue @ 743000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 744000004000. Starting simulation... +info: Entering event queue @ 744000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 745000004000. Starting simulation... +info: Entering event queue @ 745000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 746000004000. Starting simulation... +info: Entering event queue @ 746000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 747000004000. Starting simulation... +info: Entering event queue @ 747000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 748000004000. Starting simulation... +info: Entering event queue @ 748000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 749000004000. Starting simulation... +info: Entering event queue @ 749000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 750000004000. Starting simulation... +info: Entering event queue @ 750000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 751000004000. Starting simulation... +info: Entering event queue @ 751000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 752000004000. Starting simulation... +info: Entering event queue @ 752000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 753000004000. Starting simulation... +info: Entering event queue @ 753000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 754000004000. Starting simulation... +info: Entering event queue @ 754000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 755000004000. Starting simulation... +info: Entering event queue @ 755000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 756000004000. Starting simulation... +info: Entering event queue @ 756000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 757000004000. Starting simulation... +info: Entering event queue @ 757000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 758000004000. Starting simulation... +info: Entering event queue @ 758000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 759000004000. Starting simulation... +info: Entering event queue @ 759000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 760000004000. Starting simulation... +info: Entering event queue @ 760000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 761000004000. Starting simulation... +info: Entering event queue @ 761000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 762000004000. Starting simulation... +info: Entering event queue @ 762000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 763000004000. Starting simulation... +info: Entering event queue @ 763000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 764000004000. Starting simulation... +info: Entering event queue @ 764000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 765000004000. Starting simulation... +info: Entering event queue @ 765000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 766000004000. Starting simulation... +info: Entering event queue @ 766000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 767000004000. Starting simulation... +info: Entering event queue @ 767000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 768000004000. Starting simulation... +info: Entering event queue @ 768000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 769000004000. Starting simulation... +info: Entering event queue @ 769000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 770000004000. Starting simulation... +info: Entering event queue @ 770000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 771000004000. Starting simulation... +info: Entering event queue @ 771000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 772000004000. Starting simulation... +info: Entering event queue @ 772000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 773000004000. Starting simulation... +info: Entering event queue @ 773000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 774000004000. Starting simulation... +info: Entering event queue @ 774000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 775000004000. Starting simulation... +info: Entering event queue @ 775000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 776000004000. Starting simulation... +info: Entering event queue @ 776000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 777000004000. Starting simulation... +info: Entering event queue @ 777000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 778000004000. Starting simulation... +info: Entering event queue @ 778000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 779000004000. Starting simulation... +info: Entering event queue @ 779000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 780000004000. Starting simulation... +info: Entering event queue @ 780000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 781000004000. Starting simulation... +info: Entering event queue @ 781000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 782000004000. Starting simulation... +info: Entering event queue @ 782000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 783000004000. Starting simulation... +info: Entering event queue @ 783000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 784000004000. Starting simulation... +info: Entering event queue @ 784000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 785000004000. Starting simulation... +info: Entering event queue @ 785000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 786000004000. Starting simulation... +info: Entering event queue @ 786000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 787000004000. Starting simulation... +info: Entering event queue @ 787000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 788000004000. Starting simulation... +info: Entering event queue @ 788000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 789000004000. Starting simulation... +info: Entering event queue @ 789000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 790000004000. Starting simulation... +info: Entering event queue @ 790000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 791000004000. Starting simulation... +info: Entering event queue @ 791000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 792000004000. Starting simulation... +info: Entering event queue @ 792000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 793000004000. Starting simulation... +info: Entering event queue @ 793000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 794000004000. Starting simulation... +info: Entering event queue @ 794000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 795000004000. Starting simulation... +info: Entering event queue @ 795000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 796000004000. Starting simulation... +info: Entering event queue @ 796000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 797000004000. Starting simulation... +info: Entering event queue @ 797000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 798000004000. Starting simulation... +info: Entering event queue @ 798000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 799000004000. Starting simulation... +info: Entering event queue @ 799000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 800000004000. Starting simulation... +info: Entering event queue @ 800000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 801000004000. Starting simulation... +info: Entering event queue @ 801000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 802000004000. Starting simulation... +info: Entering event queue @ 802000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 803000004000. Starting simulation... +info: Entering event queue @ 803000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 804000004000. Starting simulation... +info: Entering event queue @ 804000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 805000004000. Starting simulation... +info: Entering event queue @ 805000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 806000004000. Starting simulation... +info: Entering event queue @ 806000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 807000004000. Starting simulation... +info: Entering event queue @ 807000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 808000004000. Starting simulation... +info: Entering event queue @ 808000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 809000004000. Starting simulation... +info: Entering event queue @ 809000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 810000004000. Starting simulation... +info: Entering event queue @ 810000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 811000004000. Starting simulation... +info: Entering event queue @ 811000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 812000004000. Starting simulation... +info: Entering event queue @ 812000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 813000004000. Starting simulation... +info: Entering event queue @ 813000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 814000004000. Starting simulation... +info: Entering event queue @ 814000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 815000004000. Starting simulation... +info: Entering event queue @ 815000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 816000004000. Starting simulation... +info: Entering event queue @ 816000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 817000004000. Starting simulation... +info: Entering event queue @ 817000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 818000004000. Starting simulation... +info: Entering event queue @ 818000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 819000004000. Starting simulation... +info: Entering event queue @ 819000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 820000004000. Starting simulation... +info: Entering event queue @ 820000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 821000004000. Starting simulation... +info: Entering event queue @ 821000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 822000004000. Starting simulation... +info: Entering event queue @ 822000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 823000004000. Starting simulation... +info: Entering event queue @ 823000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 824000004000. Starting simulation... +info: Entering event queue @ 824000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 825000004000. Starting simulation... +info: Entering event queue @ 825000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 826000004000. Starting simulation... +info: Entering event queue @ 826000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 827000004000. Starting simulation... +info: Entering event queue @ 827000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 828000004000. Starting simulation... +info: Entering event queue @ 828000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 829000004000. Starting simulation... +info: Entering event queue @ 829000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 830000004000. Starting simulation... +info: Entering event queue @ 830000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 831000004000. Starting simulation... +info: Entering event queue @ 831000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 832000004000. Starting simulation... +info: Entering event queue @ 832000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 833000004000. Starting simulation... +info: Entering event queue @ 833000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 834000004000. Starting simulation... +info: Entering event queue @ 834000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 835000004000. Starting simulation... +info: Entering event queue @ 835000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 836000004000. Starting simulation... +info: Entering event queue @ 836000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 837000004000. Starting simulation... +info: Entering event queue @ 837000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 838000004000. Starting simulation... +info: Entering event queue @ 838000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 839000004000. Starting simulation... +info: Entering event queue @ 839000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 840000004000. Starting simulation... +info: Entering event queue @ 840000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 841000004000. Starting simulation... +info: Entering event queue @ 841000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 842000004000. Starting simulation... +info: Entering event queue @ 842000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 843000004000. Starting simulation... +info: Entering event queue @ 843000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 844000004000. Starting simulation... +info: Entering event queue @ 844000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 845000004000. Starting simulation... +info: Entering event queue @ 845000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 846000004000. Starting simulation... +info: Entering event queue @ 846000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 847000004000. Starting simulation... +info: Entering event queue @ 847000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 848000004000. Starting simulation... +info: Entering event queue @ 848000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 849000004000. Starting simulation... +info: Entering event queue @ 849000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 850000004000. Starting simulation... +info: Entering event queue @ 850000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 851000004000. Starting simulation... +info: Entering event queue @ 851000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 852000004000. Starting simulation... +info: Entering event queue @ 852000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 853000004000. Starting simulation... +info: Entering event queue @ 853000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 854000004000. Starting simulation... +info: Entering event queue @ 854000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 855000004000. Starting simulation... +info: Entering event queue @ 855000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 856000004000. Starting simulation... +info: Entering event queue @ 856000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 857000004000. Starting simulation... +info: Entering event queue @ 857000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 858000004000. Starting simulation... +info: Entering event queue @ 858000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 859000004000. Starting simulation... +info: Entering event queue @ 859000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 860000004000. Starting simulation... +info: Entering event queue @ 860000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 861000004000. Starting simulation... +info: Entering event queue @ 861000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 862000004000. Starting simulation... +info: Entering event queue @ 862000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 863000004000. Starting simulation... +info: Entering event queue @ 863000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 864000004000. Starting simulation... +info: Entering event queue @ 864000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 865000004000. Starting simulation... +info: Entering event queue @ 865000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 866000004000. Starting simulation... +info: Entering event queue @ 866000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 867000004000. Starting simulation... +info: Entering event queue @ 867000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 868000004000. Starting simulation... +info: Entering event queue @ 868000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 869000004000. Starting simulation... +info: Entering event queue @ 869000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 870000004000. Starting simulation... +info: Entering event queue @ 870000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 871000004000. Starting simulation... +info: Entering event queue @ 871000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 872000004000. Starting simulation... +info: Entering event queue @ 872000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 873000004000. Starting simulation... +info: Entering event queue @ 873000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 874000004000. Starting simulation... +info: Entering event queue @ 874000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 875000004000. Starting simulation... +info: Entering event queue @ 875000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 876000004000. Starting simulation... +info: Entering event queue @ 876000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 877000004000. Starting simulation... +info: Entering event queue @ 877000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 878000004000. Starting simulation... +info: Entering event queue @ 878000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 879000004000. Starting simulation... +info: Entering event queue @ 879000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 880000004000. Starting simulation... +info: Entering event queue @ 880000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 881000004000. Starting simulation... +info: Entering event queue @ 881000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 882000004000. Starting simulation... +info: Entering event queue @ 882000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 883000004000. Starting simulation... +info: Entering event queue @ 883000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 884000004000. Starting simulation... +info: Entering event queue @ 884000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 885000004000. Starting simulation... +info: Entering event queue @ 885000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 886000004000. Starting simulation... +info: Entering event queue @ 886000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 887000004000. Starting simulation... +info: Entering event queue @ 887000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 888000004000. Starting simulation... +info: Entering event queue @ 888000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 889000004000. Starting simulation... +info: Entering event queue @ 889000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 890000004000. Starting simulation... +info: Entering event queue @ 890000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 891000004000. Starting simulation... +info: Entering event queue @ 891000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 892000004000. Starting simulation... +info: Entering event queue @ 892000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 893000004000. Starting simulation... +info: Entering event queue @ 893000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 894000004000. Starting simulation... +info: Entering event queue @ 894000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 895000004000. Starting simulation... +info: Entering event queue @ 895000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 896000004000. Starting simulation... +info: Entering event queue @ 896000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 897000004000. Starting simulation... +info: Entering event queue @ 897000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 898000004000. Starting simulation... +info: Entering event queue @ 898000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 899000004000. Starting simulation... +info: Entering event queue @ 899000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 900000004000. Starting simulation... +info: Entering event queue @ 900000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 901000004000. Starting simulation... +info: Entering event queue @ 901000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 902000004000. Starting simulation... +info: Entering event queue @ 902000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 903000004000. Starting simulation... +info: Entering event queue @ 903000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 904000004000. Starting simulation... +info: Entering event queue @ 904000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 905000004000. Starting simulation... +info: Entering event queue @ 905000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 906000004000. Starting simulation... +info: Entering event queue @ 906000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 907000004000. Starting simulation... +info: Entering event queue @ 907000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 908000004000. Starting simulation... +info: Entering event queue @ 908000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 909000004000. Starting simulation... +info: Entering event queue @ 909000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 910000004000. Starting simulation... +info: Entering event queue @ 910000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 911000004000. Starting simulation... +info: Entering event queue @ 911000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 912000004000. Starting simulation... +info: Entering event queue @ 912000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 913000004000. Starting simulation... +info: Entering event queue @ 913000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 914000004000. Starting simulation... +info: Entering event queue @ 914000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 915000004000. Starting simulation... +info: Entering event queue @ 915000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 916000004000. Starting simulation... +info: Entering event queue @ 916000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 917000004000. Starting simulation... +info: Entering event queue @ 917000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 918000004000. Starting simulation... +info: Entering event queue @ 918000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 919000004000. Starting simulation... +info: Entering event queue @ 919000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 920000004000. Starting simulation... +info: Entering event queue @ 920000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 921000004000. Starting simulation... +info: Entering event queue @ 921000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 922000004000. Starting simulation... +info: Entering event queue @ 922000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 923000004000. Starting simulation... +info: Entering event queue @ 923000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 924000004000. Starting simulation... +info: Entering event queue @ 924000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 925000004000. Starting simulation... +info: Entering event queue @ 925000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 926000004000. Starting simulation... +info: Entering event queue @ 926000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 927000004000. Starting simulation... +info: Entering event queue @ 927000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 928000004000. Starting simulation... +info: Entering event queue @ 928000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 929000004000. Starting simulation... +info: Entering event queue @ 929000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 930000004000. Starting simulation... +info: Entering event queue @ 930000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 931000004000. Starting simulation... +info: Entering event queue @ 931000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 932000004000. Starting simulation... +info: Entering event queue @ 932000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 933000004000. Starting simulation... +info: Entering event queue @ 933000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 934000004000. Starting simulation... +info: Entering event queue @ 934000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 935000004000. Starting simulation... +info: Entering event queue @ 935000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 936000004000. Starting simulation... +info: Entering event queue @ 936000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 937000004000. Starting simulation... +info: Entering event queue @ 937000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 938000004000. Starting simulation... +info: Entering event queue @ 938000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 939000004000. Starting simulation... +info: Entering event queue @ 939000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 940000004000. Starting simulation... +info: Entering event queue @ 940000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 941000004000. Starting simulation... +info: Entering event queue @ 941000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 942000004000. Starting simulation... +info: Entering event queue @ 942000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 943000004000. Starting simulation... +info: Entering event queue @ 943000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 944000004000. Starting simulation... +info: Entering event queue @ 944000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 945000004000. Starting simulation... +info: Entering event queue @ 945000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 946000004000. Starting simulation... +info: Entering event queue @ 946000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 947000004000. Starting simulation... +info: Entering event queue @ 947000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 948000004000. Starting simulation... +info: Entering event queue @ 948000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 949000004000. Starting simulation... +info: Entering event queue @ 949000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 950000004000. Starting simulation... +info: Entering event queue @ 950000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 951000004000. Starting simulation... +info: Entering event queue @ 951000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 952000004000. Starting simulation... +info: Entering event queue @ 952000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 953000004000. Starting simulation... +info: Entering event queue @ 953000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 954000004000. Starting simulation... +info: Entering event queue @ 954000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 955000004000. Starting simulation... +info: Entering event queue @ 955000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 956000004000. Starting simulation... +info: Entering event queue @ 956000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 957000004000. Starting simulation... +info: Entering event queue @ 957000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 958000004000. Starting simulation... +info: Entering event queue @ 958000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 959000004000. Starting simulation... +info: Entering event queue @ 959000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 960000004000. Starting simulation... +info: Entering event queue @ 960000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 961000004000. Starting simulation... +info: Entering event queue @ 961000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 962000004000. Starting simulation... +info: Entering event queue @ 962000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 963000004000. Starting simulation... +info: Entering event queue @ 963000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 964000004000. Starting simulation... +info: Entering event queue @ 964000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 965000004000. Starting simulation... +info: Entering event queue @ 965000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 966000004000. Starting simulation... +info: Entering event queue @ 966000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 967000004000. Starting simulation... +info: Entering event queue @ 967000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 968000004000. Starting simulation... +info: Entering event queue @ 968000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 969000004000. Starting simulation... +info: Entering event queue @ 969000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 970000004000. Starting simulation... +info: Entering event queue @ 970000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 971000004000. Starting simulation... +info: Entering event queue @ 971000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 972000004000. Starting simulation... +info: Entering event queue @ 972000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 973000004000. Starting simulation... +info: Entering event queue @ 973000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 974000004000. Starting simulation... +info: Entering event queue @ 974000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 975000004000. Starting simulation... +info: Entering event queue @ 975000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 976000004000. Starting simulation... +info: Entering event queue @ 976000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 977000004000. Starting simulation... +info: Entering event queue @ 977000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 978000004000. Starting simulation... +info: Entering event queue @ 978000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 979000004000. Starting simulation... +info: Entering event queue @ 979000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 980000004000. Starting simulation... +info: Entering event queue @ 980000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 981000004000. Starting simulation... +info: Entering event queue @ 981000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 982000004000. Starting simulation... +info: Entering event queue @ 982000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 983000004000. Starting simulation... +info: Entering event queue @ 983000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 984000004000. Starting simulation... +info: Entering event queue @ 984000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 985000004000. Starting simulation... +info: Entering event queue @ 985000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 986000004000. Starting simulation... +info: Entering event queue @ 986000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 987000004000. Starting simulation... +info: Entering event queue @ 987000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 988000004000. Starting simulation... +info: Entering event queue @ 988000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 989000004000. Starting simulation... +info: Entering event queue @ 989000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 990000004000. Starting simulation... +info: Entering event queue @ 990000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 991000004000. Starting simulation... +info: Entering event queue @ 991000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 992000004000. Starting simulation... +info: Entering event queue @ 992000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 993000004000. Starting simulation... +info: Entering event queue @ 993000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 994000004000. Starting simulation... +info: Entering event queue @ 994000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 995000004000. Starting simulation... +info: Entering event queue @ 995000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 996000004000. Starting simulation... +info: Entering event queue @ 996000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 997000004000. Starting simulation... +info: Entering event queue @ 997000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 998000004000. Starting simulation... +info: Entering event queue @ 998000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 999000004000. Starting simulation... +info: Entering event queue @ 999000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1000000004000. Starting simulation... +info: Entering event queue @ 1000000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1001000004000. Starting simulation... +info: Entering event queue @ 1001000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1002000004000. Starting simulation... +info: Entering event queue @ 1002000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1003000004000. Starting simulation... +info: Entering event queue @ 1003000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1004000004000. Starting simulation... +info: Entering event queue @ 1004000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1005000004000. Starting simulation... +info: Entering event queue @ 1005000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1006000004000. Starting simulation... +info: Entering event queue @ 1006000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1007000004000. Starting simulation... +info: Entering event queue @ 1007000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1008000004000. Starting simulation... +info: Entering event queue @ 1008000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1009000004000. Starting simulation... +info: Entering event queue @ 1009000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1010000004000. Starting simulation... +info: Entering event queue @ 1010000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1011000004000. Starting simulation... +info: Entering event queue @ 1011000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1012000004000. Starting simulation... +info: Entering event queue @ 1012000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1013000004000. Starting simulation... +info: Entering event queue @ 1013000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1014000004000. Starting simulation... +info: Entering event queue @ 1014000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1015000004000. Starting simulation... +info: Entering event queue @ 1015000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1016000004000. Starting simulation... +info: Entering event queue @ 1016000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1017000004000. Starting simulation... +info: Entering event queue @ 1017000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1018000004000. Starting simulation... +info: Entering event queue @ 1018000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1019000004000. Starting simulation... +info: Entering event queue @ 1019000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1020000004000. Starting simulation... +info: Entering event queue @ 1020000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1021000004000. Starting simulation... +info: Entering event queue @ 1021000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1022000004000. Starting simulation... +info: Entering event queue @ 1022000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1023000004000. Starting simulation... +info: Entering event queue @ 1023000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1024000004000. Starting simulation... +info: Entering event queue @ 1024000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1025000004000. Starting simulation... +info: Entering event queue @ 1025000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1026000004000. Starting simulation... +info: Entering event queue @ 1026000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1027000004000. Starting simulation... +info: Entering event queue @ 1027000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1028000004000. Starting simulation... +info: Entering event queue @ 1028000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1029000004000. Starting simulation... +info: Entering event queue @ 1029000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1030000004000. Starting simulation... +info: Entering event queue @ 1030000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1031000004000. Starting simulation... +info: Entering event queue @ 1031000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1032000004000. Starting simulation... +info: Entering event queue @ 1032000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1033000004000. Starting simulation... +info: Entering event queue @ 1033000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1034000004000. Starting simulation... +info: Entering event queue @ 1034000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1035000004000. Starting simulation... +info: Entering event queue @ 1035000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1036000004000. Starting simulation... +info: Entering event queue @ 1036000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1037000004000. Starting simulation... +info: Entering event queue @ 1037000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1038000004000. Starting simulation... +info: Entering event queue @ 1038000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1039000004000. Starting simulation... +info: Entering event queue @ 1039000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1040000004000. Starting simulation... +info: Entering event queue @ 1040000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1041000004000. Starting simulation... +info: Entering event queue @ 1041000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1042000004000. Starting simulation... +info: Entering event queue @ 1042000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1043000004000. Starting simulation... +info: Entering event queue @ 1043000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1044000004000. Starting simulation... +info: Entering event queue @ 1044000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1045000004000. Starting simulation... +info: Entering event queue @ 1045000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1046000004000. Starting simulation... +info: Entering event queue @ 1046000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1047000004000. Starting simulation... +info: Entering event queue @ 1047000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1048000004000. Starting simulation... +info: Entering event queue @ 1048000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1049000004000. Starting simulation... +info: Entering event queue @ 1049000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1050000004000. Starting simulation... +info: Entering event queue @ 1050000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1051000004000. Starting simulation... +info: Entering event queue @ 1051000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1052000004000. Starting simulation... +info: Entering event queue @ 1052000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1053000004000. Starting simulation... +info: Entering event queue @ 1053000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1054000004000. Starting simulation... +info: Entering event queue @ 1054000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1055000004000. Starting simulation... +info: Entering event queue @ 1055000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1056000004000. Starting simulation... +info: Entering event queue @ 1056000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1057000004000. Starting simulation... +info: Entering event queue @ 1057000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1058000004000. Starting simulation... +info: Entering event queue @ 1058000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1059000004000. Starting simulation... +info: Entering event queue @ 1059000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1060000004000. Starting simulation... +info: Entering event queue @ 1060000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1061000004000. Starting simulation... +info: Entering event queue @ 1061000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1062000004000. Starting simulation... +info: Entering event queue @ 1062000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1063000004000. Starting simulation... +info: Entering event queue @ 1063000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1064000004000. Starting simulation... +info: Entering event queue @ 1064000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1065000004000. Starting simulation... +info: Entering event queue @ 1065000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1066000004000. Starting simulation... +info: Entering event queue @ 1066000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1067000004000. Starting simulation... +info: Entering event queue @ 1067000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1068000004000. Starting simulation... +info: Entering event queue @ 1068000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1069000004000. Starting simulation... +info: Entering event queue @ 1069000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1070000004000. Starting simulation... +info: Entering event queue @ 1070000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1071000004000. Starting simulation... +info: Entering event queue @ 1071000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1072000004000. Starting simulation... +info: Entering event queue @ 1072000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1073000004000. Starting simulation... +info: Entering event queue @ 1073000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1074000004000. Starting simulation... +info: Entering event queue @ 1074000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1075000004000. Starting simulation... +info: Entering event queue @ 1075000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1076000004000. Starting simulation... +info: Entering event queue @ 1076000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1077000004000. Starting simulation... +info: Entering event queue @ 1077000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1078000004000. Starting simulation... +info: Entering event queue @ 1078000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1079000004000. Starting simulation... +info: Entering event queue @ 1079000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1080000004000. Starting simulation... +info: Entering event queue @ 1080000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1081000004000. Starting simulation... +info: Entering event queue @ 1081000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1082000004000. Starting simulation... +info: Entering event queue @ 1082000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1083000004000. Starting simulation... +info: Entering event queue @ 1083000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1084000004000. Starting simulation... +info: Entering event queue @ 1084000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1085000004000. Starting simulation... +info: Entering event queue @ 1085000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1086000004000. Starting simulation... +info: Entering event queue @ 1086000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1087000004000. Starting simulation... +info: Entering event queue @ 1087000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1088000004000. Starting simulation... +info: Entering event queue @ 1088000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1089000004000. Starting simulation... +info: Entering event queue @ 1089000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1090000004000. Starting simulation... +info: Entering event queue @ 1090000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1091000004000. Starting simulation... +info: Entering event queue @ 1091000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1092000004000. Starting simulation... +info: Entering event queue @ 1092000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1093000004000. Starting simulation... +info: Entering event queue @ 1093000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1094000004000. Starting simulation... +info: Entering event queue @ 1094000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1095000004000. Starting simulation... +info: Entering event queue @ 1095000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1096000004000. Starting simulation... +info: Entering event queue @ 1096000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1097000004000. Starting simulation... +info: Entering event queue @ 1097000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1098000004000. Starting simulation... +info: Entering event queue @ 1098000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1099000004000. Starting simulation... +info: Entering event queue @ 1099000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1100000004000. Starting simulation... +info: Entering event queue @ 1100000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1101000004000. Starting simulation... +info: Entering event queue @ 1101000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1102000004000. Starting simulation... +info: Entering event queue @ 1102000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1103000004000. Starting simulation... +info: Entering event queue @ 1103000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1104000004000. Starting simulation... +info: Entering event queue @ 1104000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1105000004000. Starting simulation... +info: Entering event queue @ 1105000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1106000004000. Starting simulation... +info: Entering event queue @ 1106000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1107000004000. Starting simulation... +info: Entering event queue @ 1107000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1108000004000. Starting simulation... +info: Entering event queue @ 1108000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1109000004000. Starting simulation... +info: Entering event queue @ 1109000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1110000004000. Starting simulation... +info: Entering event queue @ 1110000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1111000004000. Starting simulation... +info: Entering event queue @ 1111000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1112000004000. Starting simulation... +info: Entering event queue @ 1112000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1113000004000. Starting simulation... +info: Entering event queue @ 1113000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1114000004000. Starting simulation... +info: Entering event queue @ 1114000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1115000004000. Starting simulation... +info: Entering event queue @ 1115000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1116000004000. Starting simulation... +info: Entering event queue @ 1116000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1117000004000. Starting simulation... +info: Entering event queue @ 1117000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1118000004000. Starting simulation... +info: Entering event queue @ 1118000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1119000004000. Starting simulation... +info: Entering event queue @ 1119000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1120000004000. Starting simulation... +info: Entering event queue @ 1120000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1121000004000. Starting simulation... +info: Entering event queue @ 1121000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1122000004000. Starting simulation... +info: Entering event queue @ 1122000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1123000004000. Starting simulation... +info: Entering event queue @ 1123000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1124000004000. Starting simulation... +info: Entering event queue @ 1124000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1125000004000. Starting simulation... +info: Entering event queue @ 1125000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1126000004000. Starting simulation... +info: Entering event queue @ 1126000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1127000004000. Starting simulation... +info: Entering event queue @ 1127000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1128000004000. Starting simulation... +info: Entering event queue @ 1128000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1129000004000. Starting simulation... +info: Entering event queue @ 1129000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1130000004000. Starting simulation... +info: Entering event queue @ 1130000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1131000004000. Starting simulation... +info: Entering event queue @ 1131000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1132000004000. Starting simulation... +info: Entering event queue @ 1132000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1133000004000. Starting simulation... +info: Entering event queue @ 1133000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1134000004000. Starting simulation... +info: Entering event queue @ 1134000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1135000004000. Starting simulation... +info: Entering event queue @ 1135000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1136000004000. Starting simulation... +info: Entering event queue @ 1136000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1137000004000. Starting simulation... +info: Entering event queue @ 1137000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1138000004000. Starting simulation... +info: Entering event queue @ 1138000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1139000004000. Starting simulation... +info: Entering event queue @ 1139000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1140000004000. Starting simulation... +info: Entering event queue @ 1140000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1141000004000. Starting simulation... +info: Entering event queue @ 1141000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1142000004000. Starting simulation... +info: Entering event queue @ 1142000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1143000004000. Starting simulation... +info: Entering event queue @ 1143000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1144000004000. Starting simulation... +info: Entering event queue @ 1144000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1145000004000. Starting simulation... +info: Entering event queue @ 1145000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1146000004000. Starting simulation... +info: Entering event queue @ 1146000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1147000004000. Starting simulation... +info: Entering event queue @ 1147000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1148000004000. Starting simulation... +info: Entering event queue @ 1148000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1149000004000. Starting simulation... +info: Entering event queue @ 1149000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1150000004000. Starting simulation... +info: Entering event queue @ 1150000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1151000004000. Starting simulation... +info: Entering event queue @ 1151000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1152000004000. Starting simulation... +info: Entering event queue @ 1152000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1153000004000. Starting simulation... +info: Entering event queue @ 1153000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1154000004000. Starting simulation... +info: Entering event queue @ 1154000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1155000004000. Starting simulation... +info: Entering event queue @ 1155000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1156000004000. Starting simulation... +info: Entering event queue @ 1156000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1157000004000. Starting simulation... +info: Entering event queue @ 1157000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1158000004000. Starting simulation... +info: Entering event queue @ 1158000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1159000004000. Starting simulation... +info: Entering event queue @ 1159000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1160000004000. Starting simulation... +info: Entering event queue @ 1160000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1161000004000. Starting simulation... +info: Entering event queue @ 1161000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1162000004000. Starting simulation... +info: Entering event queue @ 1162000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1163000004000. Starting simulation... +info: Entering event queue @ 1163000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1164000004000. Starting simulation... +info: Entering event queue @ 1164000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1165000004000. Starting simulation... +info: Entering event queue @ 1165000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1166000004000. Starting simulation... +info: Entering event queue @ 1166000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1167000004000. Starting simulation... +info: Entering event queue @ 1167000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1168000004000. Starting simulation... +info: Entering event queue @ 1168000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1169000004000. Starting simulation... +info: Entering event queue @ 1169000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1170000004000. Starting simulation... +info: Entering event queue @ 1170000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1171000004000. Starting simulation... +info: Entering event queue @ 1171000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1172000004000. Starting simulation... +info: Entering event queue @ 1172000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1173000004000. Starting simulation... +info: Entering event queue @ 1173000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1174000004000. Starting simulation... +info: Entering event queue @ 1174000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1175000004000. Starting simulation... +info: Entering event queue @ 1175000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1176000004000. Starting simulation... +info: Entering event queue @ 1176000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1177000004000. Starting simulation... +info: Entering event queue @ 1177000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1178000004000. Starting simulation... +info: Entering event queue @ 1178000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1179000004000. Starting simulation... +info: Entering event queue @ 1179000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1180000004000. Starting simulation... +info: Entering event queue @ 1180000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1181000004000. Starting simulation... +info: Entering event queue @ 1181000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1182000004000. Starting simulation... +info: Entering event queue @ 1182000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1183000004000. Starting simulation... +info: Entering event queue @ 1183000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1184000004000. Starting simulation... +info: Entering event queue @ 1184000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1185000004000. Starting simulation... +info: Entering event queue @ 1185000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1186000004000. Starting simulation... +info: Entering event queue @ 1186000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1187000004000. Starting simulation... +info: Entering event queue @ 1187000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1188000004000. Starting simulation... +info: Entering event queue @ 1188000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1189000004000. Starting simulation... +info: Entering event queue @ 1189000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1190000004000. Starting simulation... +info: Entering event queue @ 1190000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1191000004000. Starting simulation... +info: Entering event queue @ 1191000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1192000004000. Starting simulation... +info: Entering event queue @ 1192000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1193000004000. Starting simulation... +info: Entering event queue @ 1193000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1194000004000. Starting simulation... +info: Entering event queue @ 1194000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1195000004000. Starting simulation... +info: Entering event queue @ 1195000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1196000004000. Starting simulation... +info: Entering event queue @ 1196000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1197000004000. Starting simulation... +info: Entering event queue @ 1197000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1198000004000. Starting simulation... +info: Entering event queue @ 1198000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1199000004000. Starting simulation... +info: Entering event queue @ 1199000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1200000004000. Starting simulation... +info: Entering event queue @ 1200000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1201000004000. Starting simulation... +info: Entering event queue @ 1201000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1202000004000. Starting simulation... +info: Entering event queue @ 1202000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1203000004000. Starting simulation... +info: Entering event queue @ 1203000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1204000004000. Starting simulation... +info: Entering event queue @ 1204000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1205000004000. Starting simulation... +info: Entering event queue @ 1205000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1206000004000. Starting simulation... +info: Entering event queue @ 1206000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1207000004000. Starting simulation... +info: Entering event queue @ 1207000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1208000004000. Starting simulation... +info: Entering event queue @ 1208000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1209000004000. Starting simulation... +info: Entering event queue @ 1209000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1210000004000. Starting simulation... +info: Entering event queue @ 1210000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1211000004000. Starting simulation... +info: Entering event queue @ 1211000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1212000004000. Starting simulation... +info: Entering event queue @ 1212000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1213000004000. Starting simulation... +info: Entering event queue @ 1213000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1214000004000. Starting simulation... +info: Entering event queue @ 1214000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1215000004000. Starting simulation... +info: Entering event queue @ 1215000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1216000004000. Starting simulation... +info: Entering event queue @ 1216000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1217000004000. Starting simulation... +info: Entering event queue @ 1217000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1218000004000. Starting simulation... +info: Entering event queue @ 1218000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1219000004000. Starting simulation... +info: Entering event queue @ 1219000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1220000004000. Starting simulation... +info: Entering event queue @ 1220000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1221000004000. Starting simulation... +info: Entering event queue @ 1221000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1222000004000. Starting simulation... +info: Entering event queue @ 1222000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1223000004000. Starting simulation... +info: Entering event queue @ 1223000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1224000004000. Starting simulation... +info: Entering event queue @ 1224000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1225000004000. Starting simulation... +info: Entering event queue @ 1225000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1226000004000. Starting simulation... +info: Entering event queue @ 1226000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1227000004000. Starting simulation... +info: Entering event queue @ 1227000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1228000004000. Starting simulation... +info: Entering event queue @ 1228000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1229000004000. Starting simulation... +info: Entering event queue @ 1229000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1230000004000. Starting simulation... +info: Entering event queue @ 1230000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1231000004000. Starting simulation... +info: Entering event queue @ 1231000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1232000004000. Starting simulation... +info: Entering event queue @ 1232000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1233000004000. Starting simulation... +info: Entering event queue @ 1233000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1234000004000. Starting simulation... +info: Entering event queue @ 1234000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1235000004000. Starting simulation... +info: Entering event queue @ 1235000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1236000004000. Starting simulation... +info: Entering event queue @ 1236000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1237000004000. Starting simulation... +info: Entering event queue @ 1237000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1238000004000. Starting simulation... +info: Entering event queue @ 1238000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1239000004000. Starting simulation... +info: Entering event queue @ 1239000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1240000004000. Starting simulation... +info: Entering event queue @ 1240000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1241000004000. Starting simulation... +info: Entering event queue @ 1241000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1242000004000. Starting simulation... +info: Entering event queue @ 1242000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1243000004000. Starting simulation... +info: Entering event queue @ 1243000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1244000004000. Starting simulation... +info: Entering event queue @ 1244000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1245000004000. Starting simulation... +info: Entering event queue @ 1245000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1246000004000. Starting simulation... +info: Entering event queue @ 1246000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1247000004000. Starting simulation... +info: Entering event queue @ 1247000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1248000004000. Starting simulation... +info: Entering event queue @ 1248000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1249000004000. Starting simulation... +info: Entering event queue @ 1249000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1250000004000. Starting simulation... +info: Entering event queue @ 1250000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1251000004000. Starting simulation... +info: Entering event queue @ 1251000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1252000004000. Starting simulation... +info: Entering event queue @ 1252000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1253000004000. Starting simulation... +info: Entering event queue @ 1253000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1254000004000. Starting simulation... +info: Entering event queue @ 1254000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1255000004000. Starting simulation... +info: Entering event queue @ 1255000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1256000004000. Starting simulation... +info: Entering event queue @ 1256000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1257000004000. Starting simulation... +info: Entering event queue @ 1257000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1258000004000. Starting simulation... +info: Entering event queue @ 1258000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1259000004000. Starting simulation... +info: Entering event queue @ 1259000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1260000004000. Starting simulation... +info: Entering event queue @ 1260000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1261000004000. Starting simulation... +info: Entering event queue @ 1261000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1262000004000. Starting simulation... +info: Entering event queue @ 1262000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1263000004000. Starting simulation... +info: Entering event queue @ 1263000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1264000004000. Starting simulation... +info: Entering event queue @ 1264000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1265000004000. Starting simulation... +info: Entering event queue @ 1265000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1266000004000. Starting simulation... +info: Entering event queue @ 1266000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1267000004000. Starting simulation... +info: Entering event queue @ 1267000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1268000004000. Starting simulation... +info: Entering event queue @ 1268000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1269000004000. Starting simulation... +info: Entering event queue @ 1269000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1270000004000. Starting simulation... +info: Entering event queue @ 1270000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1271000004000. Starting simulation... +info: Entering event queue @ 1271000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1272000004000. Starting simulation... +info: Entering event queue @ 1272000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1273000004000. Starting simulation... +info: Entering event queue @ 1273000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1274000004000. Starting simulation... +info: Entering event queue @ 1274000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1275000004000. Starting simulation... +info: Entering event queue @ 1275000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1276000004000. Starting simulation... +info: Entering event queue @ 1276000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1277000004000. Starting simulation... +info: Entering event queue @ 1277000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1278000004000. Starting simulation... +info: Entering event queue @ 1278000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1279000004000. Starting simulation... +info: Entering event queue @ 1279000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1280000004000. Starting simulation... +info: Entering event queue @ 1280000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1281000004000. Starting simulation... +info: Entering event queue @ 1281000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1282000004000. Starting simulation... +info: Entering event queue @ 1282000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1283000004000. Starting simulation... +info: Entering event queue @ 1283000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1284000004000. Starting simulation... +info: Entering event queue @ 1284000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1285000004000. Starting simulation... +info: Entering event queue @ 1285000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1286000004000. Starting simulation... +info: Entering event queue @ 1286000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1287000004000. Starting simulation... +info: Entering event queue @ 1287000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1288000004000. Starting simulation... +info: Entering event queue @ 1288000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1289000004000. Starting simulation... +info: Entering event queue @ 1289000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1290000004000. Starting simulation... +info: Entering event queue @ 1290000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1291000004000. Starting simulation... +info: Entering event queue @ 1291000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1292000004000. Starting simulation... +info: Entering event queue @ 1292000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1293000004000. Starting simulation... +info: Entering event queue @ 1293000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1294000004000. Starting simulation... +info: Entering event queue @ 1294000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1295000004000. Starting simulation... +info: Entering event queue @ 1295000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1296000004000. Starting simulation... +info: Entering event queue @ 1296000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1297000004000. Starting simulation... +info: Entering event queue @ 1297000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1298000004000. Starting simulation... +info: Entering event queue @ 1298000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1299000004000. Starting simulation... +info: Entering event queue @ 1299000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1300000004000. Starting simulation... +info: Entering event queue @ 1300000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1301000004000. Starting simulation... +info: Entering event queue @ 1301000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1302000004000. Starting simulation... +info: Entering event queue @ 1302000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1303000004000. Starting simulation... +info: Entering event queue @ 1303000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1304000004000. Starting simulation... +info: Entering event queue @ 1304000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1305000004000. Starting simulation... +info: Entering event queue @ 1305000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1306000004000. Starting simulation... +info: Entering event queue @ 1306000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1307000004000. Starting simulation... +info: Entering event queue @ 1307000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1308000004000. Starting simulation... +info: Entering event queue @ 1308000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1309000004000. Starting simulation... +info: Entering event queue @ 1309000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1310000004000. Starting simulation... +info: Entering event queue @ 1310000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1311000004000. Starting simulation... +info: Entering event queue @ 1311000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1312000004000. Starting simulation... +info: Entering event queue @ 1312000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1313000004000. Starting simulation... +info: Entering event queue @ 1313000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1314000004000. Starting simulation... +info: Entering event queue @ 1314000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1315000004000. Starting simulation... +info: Entering event queue @ 1315000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1316000004000. Starting simulation... +info: Entering event queue @ 1316000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1317000004000. Starting simulation... +info: Entering event queue @ 1317000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1318000004000. Starting simulation... +info: Entering event queue @ 1318000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1319000004000. Starting simulation... +info: Entering event queue @ 1319000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1320000004000. Starting simulation... +info: Entering event queue @ 1320000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1321000004000. Starting simulation... +info: Entering event queue @ 1321000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1322000004000. Starting simulation... +info: Entering event queue @ 1322000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1323000004000. Starting simulation... +info: Entering event queue @ 1323000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1324000004000. Starting simulation... +info: Entering event queue @ 1324000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1325000004000. Starting simulation... +info: Entering event queue @ 1325000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1326000004000. Starting simulation... +info: Entering event queue @ 1326000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1327000004000. Starting simulation... +info: Entering event queue @ 1327000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1328000004000. Starting simulation... +info: Entering event queue @ 1328000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1329000004000. Starting simulation... +info: Entering event queue @ 1329000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1330000004000. Starting simulation... +info: Entering event queue @ 1330000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1331000004000. Starting simulation... +info: Entering event queue @ 1331000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1332000004000. Starting simulation... +info: Entering event queue @ 1332000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1333000004000. Starting simulation... +info: Entering event queue @ 1333000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1334000004000. Starting simulation... +info: Entering event queue @ 1334000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1335000004000. Starting simulation... +info: Entering event queue @ 1335000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1336000004000. Starting simulation... +info: Entering event queue @ 1336000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1337000004000. Starting simulation... +info: Entering event queue @ 1337000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1338000004000. Starting simulation... +info: Entering event queue @ 1338000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1339000004000. Starting simulation... +info: Entering event queue @ 1339000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1340000004000. Starting simulation... +info: Entering event queue @ 1340000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1341000004000. Starting simulation... +info: Entering event queue @ 1341000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1342000004000. Starting simulation... +info: Entering event queue @ 1342000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1343000004000. Starting simulation... +info: Entering event queue @ 1343000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1344000004000. Starting simulation... +info: Entering event queue @ 1344000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1345000004000. Starting simulation... +info: Entering event queue @ 1345000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1346000004000. Starting simulation... +info: Entering event queue @ 1346000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1347000004000. Starting simulation... +info: Entering event queue @ 1347000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1348000004000. Starting simulation... +info: Entering event queue @ 1348000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1349000004000. Starting simulation... +info: Entering event queue @ 1349000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1350000004000. Starting simulation... +info: Entering event queue @ 1350000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1351000004000. Starting simulation... +info: Entering event queue @ 1351000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1352000004000. Starting simulation... +info: Entering event queue @ 1352000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1353000004000. Starting simulation... +info: Entering event queue @ 1353000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1354000004000. Starting simulation... +info: Entering event queue @ 1354000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1355000004000. Starting simulation... +info: Entering event queue @ 1355000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1356000004000. Starting simulation... +info: Entering event queue @ 1356000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1357000004000. Starting simulation... +info: Entering event queue @ 1357000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1358000004000. Starting simulation... +info: Entering event queue @ 1358000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1359000004000. Starting simulation... +info: Entering event queue @ 1359000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1360000004000. Starting simulation... +info: Entering event queue @ 1360000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1361000004000. Starting simulation... +info: Entering event queue @ 1361000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1362000004000. Starting simulation... +info: Entering event queue @ 1362000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1363000004000. Starting simulation... +info: Entering event queue @ 1363000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1364000004000. Starting simulation... +info: Entering event queue @ 1364000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1365000004000. Starting simulation... +info: Entering event queue @ 1365000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1366000004000. Starting simulation... +info: Entering event queue @ 1366000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1367000004000. Starting simulation... +info: Entering event queue @ 1367000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1368000004000. Starting simulation... +info: Entering event queue @ 1368000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1369000004000. Starting simulation... +info: Entering event queue @ 1369000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1370000004000. Starting simulation... +info: Entering event queue @ 1370000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1371000004000. Starting simulation... +info: Entering event queue @ 1371000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1372000004000. Starting simulation... +info: Entering event queue @ 1372000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1373000004000. Starting simulation... +info: Entering event queue @ 1373000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1374000004000. Starting simulation... +info: Entering event queue @ 1374000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1375000004000. Starting simulation... +info: Entering event queue @ 1375000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1376000004000. Starting simulation... +info: Entering event queue @ 1376000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1377000004000. Starting simulation... +info: Entering event queue @ 1377000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1378000004000. Starting simulation... +info: Entering event queue @ 1378000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1379000004000. Starting simulation... +info: Entering event queue @ 1379000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1380000004000. Starting simulation... +info: Entering event queue @ 1380000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1381000004000. Starting simulation... +info: Entering event queue @ 1381000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1382000004000. Starting simulation... +info: Entering event queue @ 1382000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1383000004000. Starting simulation... +info: Entering event queue @ 1383000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1384000004000. Starting simulation... +info: Entering event queue @ 1384000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1385000004000. Starting simulation... +info: Entering event queue @ 1385000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1386000004000. Starting simulation... +info: Entering event queue @ 1386000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1387000004000. Starting simulation... +info: Entering event queue @ 1387000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1388000004000. Starting simulation... +info: Entering event queue @ 1388000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1389000004000. Starting simulation... +info: Entering event queue @ 1389000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1390000004000. Starting simulation... +info: Entering event queue @ 1390000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1391000004000. Starting simulation... +info: Entering event queue @ 1391000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1392000004000. Starting simulation... +info: Entering event queue @ 1392000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1393000004000. Starting simulation... +info: Entering event queue @ 1393000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1394000004000. Starting simulation... +info: Entering event queue @ 1394000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1395000004000. Starting simulation... +info: Entering event queue @ 1395000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1396000004000. Starting simulation... +info: Entering event queue @ 1396000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1397000004000. Starting simulation... +info: Entering event queue @ 1397000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1398000004000. Starting simulation... +info: Entering event queue @ 1398000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1399000004000. Starting simulation... +info: Entering event queue @ 1399000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1400000004000. Starting simulation... +info: Entering event queue @ 1400000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1401000004000. Starting simulation... +info: Entering event queue @ 1401000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1402000004000. Starting simulation... +info: Entering event queue @ 1402000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1403000004000. Starting simulation... +info: Entering event queue @ 1403000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1404000004000. Starting simulation... +info: Entering event queue @ 1404000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1405000004000. Starting simulation... +info: Entering event queue @ 1405000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1406000004000. Starting simulation... +info: Entering event queue @ 1406000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1407000004000. Starting simulation... +info: Entering event queue @ 1407000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1408000004000. Starting simulation... +info: Entering event queue @ 1408000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1409000004000. Starting simulation... +info: Entering event queue @ 1409000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1410000004000. Starting simulation... +info: Entering event queue @ 1410000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1411000004000. Starting simulation... +info: Entering event queue @ 1411000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1412000004000. Starting simulation... +info: Entering event queue @ 1412000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1413000004000. Starting simulation... +info: Entering event queue @ 1413000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1414000004000. Starting simulation... +info: Entering event queue @ 1414000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1415000004000. Starting simulation... +info: Entering event queue @ 1415000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1416000004000. Starting simulation... +info: Entering event queue @ 1416000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1417000004000. Starting simulation... +info: Entering event queue @ 1417000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1418000004000. Starting simulation... +info: Entering event queue @ 1418000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1419000004000. Starting simulation... +info: Entering event queue @ 1419000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1420000004000. Starting simulation... +info: Entering event queue @ 1420000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1421000004000. Starting simulation... +info: Entering event queue @ 1421000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1422000004000. Starting simulation... +info: Entering event queue @ 1422000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1423000004000. Starting simulation... +info: Entering event queue @ 1423000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1424000004000. Starting simulation... +info: Entering event queue @ 1424000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1425000004000. Starting simulation... +info: Entering event queue @ 1425000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1426000004000. Starting simulation... +info: Entering event queue @ 1426000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1427000004000. Starting simulation... +info: Entering event queue @ 1427000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1428000004000. Starting simulation... +info: Entering event queue @ 1428000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1429000004000. Starting simulation... +info: Entering event queue @ 1429000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1430000004000. Starting simulation... +info: Entering event queue @ 1430000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1431000004000. Starting simulation... +info: Entering event queue @ 1431000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1432000004000. Starting simulation... +info: Entering event queue @ 1432000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1433000004000. Starting simulation... +info: Entering event queue @ 1433000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1434000004000. Starting simulation... +info: Entering event queue @ 1434000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1435000004000. Starting simulation... +info: Entering event queue @ 1435000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1436000004000. Starting simulation... +info: Entering event queue @ 1436000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1437000004000. Starting simulation... +info: Entering event queue @ 1437000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1438000004000. Starting simulation... +info: Entering event queue @ 1438000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1439000004000. Starting simulation... +info: Entering event queue @ 1439000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1440000004000. Starting simulation... +info: Entering event queue @ 1440000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1441000004000. Starting simulation... +info: Entering event queue @ 1441000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1442000004000. Starting simulation... +info: Entering event queue @ 1442000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1443000004000. Starting simulation... +info: Entering event queue @ 1443000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1444000004000. Starting simulation... +info: Entering event queue @ 1444000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1445000004000. Starting simulation... +info: Entering event queue @ 1445000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1446000004000. Starting simulation... +info: Entering event queue @ 1446000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1447000004000. Starting simulation... +info: Entering event queue @ 1447000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1448000004000. Starting simulation... +info: Entering event queue @ 1448000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1449000004000. Starting simulation... +info: Entering event queue @ 1449000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1450000004000. Starting simulation... +info: Entering event queue @ 1450000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1451000004000. Starting simulation... +info: Entering event queue @ 1451000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1452000004000. Starting simulation... +info: Entering event queue @ 1452000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1453000004000. Starting simulation... +info: Entering event queue @ 1453000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1454000004000. Starting simulation... +info: Entering event queue @ 1454000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1455000004000. Starting simulation... +info: Entering event queue @ 1455000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1456000004000. Starting simulation... +info: Entering event queue @ 1456000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1457000004000. Starting simulation... +info: Entering event queue @ 1457000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1458000004000. Starting simulation... +info: Entering event queue @ 1458000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1459000004000. Starting simulation... +info: Entering event queue @ 1459000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1460000004000. Starting simulation... +info: Entering event queue @ 1460000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1461000004000. Starting simulation... +info: Entering event queue @ 1461000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1462000004000. Starting simulation... +info: Entering event queue @ 1462000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1463000004000. Starting simulation... +info: Entering event queue @ 1463000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1464000004000. Starting simulation... +info: Entering event queue @ 1464000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1465000004000. Starting simulation... +info: Entering event queue @ 1465000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1466000004000. Starting simulation... +info: Entering event queue @ 1466000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1467000004000. Starting simulation... +info: Entering event queue @ 1467000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1468000004000. Starting simulation... +info: Entering event queue @ 1468000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1469000004000. Starting simulation... +info: Entering event queue @ 1469000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1470000004000. Starting simulation... +info: Entering event queue @ 1470000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1471000004000. Starting simulation... +info: Entering event queue @ 1471000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1472000004000. Starting simulation... +info: Entering event queue @ 1472000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1473000004000. Starting simulation... +info: Entering event queue @ 1473000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1474000004000. Starting simulation... +info: Entering event queue @ 1474000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1475000004000. Starting simulation... +info: Entering event queue @ 1475000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1476000004000. Starting simulation... +info: Entering event queue @ 1476000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1477000004000. Starting simulation... +info: Entering event queue @ 1477000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1478000004000. Starting simulation... +info: Entering event queue @ 1478000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1479000004000. Starting simulation... +info: Entering event queue @ 1479000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1480000004000. Starting simulation... +info: Entering event queue @ 1480000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1481000004000. Starting simulation... +info: Entering event queue @ 1481000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1482000004000. Starting simulation... +info: Entering event queue @ 1482000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1483000004000. Starting simulation... +info: Entering event queue @ 1483000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1484000004000. Starting simulation... +info: Entering event queue @ 1484000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1485000004000. Starting simulation... +info: Entering event queue @ 1485000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1486000004000. Starting simulation... +info: Entering event queue @ 1486000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1487000004000. Starting simulation... +info: Entering event queue @ 1487000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1488000004000. Starting simulation... +info: Entering event queue @ 1488000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1489000004000. Starting simulation... +info: Entering event queue @ 1489000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1490000004000. Starting simulation... +info: Entering event queue @ 1490000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1491000004000. Starting simulation... +info: Entering event queue @ 1491000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1492000004000. Starting simulation... +info: Entering event queue @ 1492000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1493000004000. Starting simulation... +info: Entering event queue @ 1493000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1494000004000. Starting simulation... +info: Entering event queue @ 1494000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1495000004000. Starting simulation... +info: Entering event queue @ 1495000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1496000004000. Starting simulation... +info: Entering event queue @ 1496000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1497000004000. Starting simulation... +info: Entering event queue @ 1497000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1498000004000. Starting simulation... +info: Entering event queue @ 1498000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1499000004000. Starting simulation... +info: Entering event queue @ 1499000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1500000004000. Starting simulation... +info: Entering event queue @ 1500000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1501000004000. Starting simulation... +info: Entering event queue @ 1501000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1502000004000. Starting simulation... +info: Entering event queue @ 1502000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1503000004000. Starting simulation... +info: Entering event queue @ 1503000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1504000004000. Starting simulation... +info: Entering event queue @ 1504000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1505000004000. Starting simulation... +info: Entering event queue @ 1505000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1506000004000. Starting simulation... +info: Entering event queue @ 1506000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1507000004000. Starting simulation... +info: Entering event queue @ 1507000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1508000004000. Starting simulation... +info: Entering event queue @ 1508000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1509000004000. Starting simulation... +info: Entering event queue @ 1509000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1510000004000. Starting simulation... +info: Entering event queue @ 1510000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1511000004000. Starting simulation... +info: Entering event queue @ 1511000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1512000004000. Starting simulation... +info: Entering event queue @ 1512000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1513000004000. Starting simulation... +info: Entering event queue @ 1513000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1514000004000. Starting simulation... +info: Entering event queue @ 1514000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1515000004000. Starting simulation... +info: Entering event queue @ 1515000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1516000004000. Starting simulation... +info: Entering event queue @ 1516000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1517000004000. Starting simulation... +info: Entering event queue @ 1517000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1518000004000. Starting simulation... +info: Entering event queue @ 1518000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1519000004000. Starting simulation... +info: Entering event queue @ 1519000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1520000004000. Starting simulation... +info: Entering event queue @ 1520000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1521000004000. Starting simulation... +info: Entering event queue @ 1521000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1522000004000. Starting simulation... +info: Entering event queue @ 1522000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1523000004000. Starting simulation... +info: Entering event queue @ 1523000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1524000004000. Starting simulation... +info: Entering event queue @ 1524000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1525000004000. Starting simulation... +info: Entering event queue @ 1525000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1526000004000. Starting simulation... +info: Entering event queue @ 1526000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1527000004000. Starting simulation... +info: Entering event queue @ 1527000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1528000004000. Starting simulation... +info: Entering event queue @ 1528000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1529000004000. Starting simulation... +info: Entering event queue @ 1529000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1530000004000. Starting simulation... +info: Entering event queue @ 1530000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1531000004000. Starting simulation... +info: Entering event queue @ 1531000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1532000004000. Starting simulation... +info: Entering event queue @ 1532000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1533000004000. Starting simulation... +info: Entering event queue @ 1533000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1534000004000. Starting simulation... +info: Entering event queue @ 1534000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1535000004000. Starting simulation... +info: Entering event queue @ 1535000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1536000004000. Starting simulation... +info: Entering event queue @ 1536000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1537000004000. Starting simulation... +info: Entering event queue @ 1537000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1538000004000. Starting simulation... +info: Entering event queue @ 1538000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1539000004000. Starting simulation... +info: Entering event queue @ 1539000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1540000004000. Starting simulation... +info: Entering event queue @ 1540000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1541000004000. Starting simulation... +info: Entering event queue @ 1541000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1542000004000. Starting simulation... +info: Entering event queue @ 1542000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1543000004000. Starting simulation... +info: Entering event queue @ 1543000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1544000004000. Starting simulation... +info: Entering event queue @ 1544000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1545000004000. Starting simulation... +info: Entering event queue @ 1545000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1546000004000. Starting simulation... +info: Entering event queue @ 1546000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1547000004000. Starting simulation... +info: Entering event queue @ 1547000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1548000004000. Starting simulation... +info: Entering event queue @ 1548000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1549000004000. Starting simulation... +info: Entering event queue @ 1549000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1550000004000. Starting simulation... +info: Entering event queue @ 1550000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1551000004000. Starting simulation... +info: Entering event queue @ 1551000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1552000004000. Starting simulation... +info: Entering event queue @ 1552000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1553000004000. Starting simulation... +info: Entering event queue @ 1553000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1554000004000. Starting simulation... +info: Entering event queue @ 1554000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1555000004000. Starting simulation... +info: Entering event queue @ 1555000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1556000004000. Starting simulation... +info: Entering event queue @ 1556000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1557000004000. Starting simulation... +info: Entering event queue @ 1557000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1558000004000. Starting simulation... +info: Entering event queue @ 1558000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1559000004000. Starting simulation... +info: Entering event queue @ 1559000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1560000004000. Starting simulation... +info: Entering event queue @ 1560000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1561000004000. Starting simulation... +info: Entering event queue @ 1561000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1562000004000. Starting simulation... +info: Entering event queue @ 1562000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1563000004000. Starting simulation... +info: Entering event queue @ 1563000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1564000004000. Starting simulation... +info: Entering event queue @ 1564000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1565000004000. Starting simulation... +info: Entering event queue @ 1565000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1566000004000. Starting simulation... +info: Entering event queue @ 1566000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1567000004000. Starting simulation... +info: Entering event queue @ 1567000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1568000004000. Starting simulation... +info: Entering event queue @ 1568000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1569000004000. Starting simulation... +info: Entering event queue @ 1569000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1570000004000. Starting simulation... +info: Entering event queue @ 1570000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1571000004000. Starting simulation... +info: Entering event queue @ 1571000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1572000004000. Starting simulation... +info: Entering event queue @ 1572000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1573000004000. Starting simulation... +info: Entering event queue @ 1573000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1574000004000. Starting simulation... +info: Entering event queue @ 1574000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1575000004000. Starting simulation... +info: Entering event queue @ 1575000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1576000004000. Starting simulation... +info: Entering event queue @ 1576000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1577000004000. Starting simulation... +info: Entering event queue @ 1577000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1578000004000. Starting simulation... +info: Entering event queue @ 1578000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1579000004000. Starting simulation... +info: Entering event queue @ 1579000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1580000004000. Starting simulation... +info: Entering event queue @ 1580000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1581000004000. Starting simulation... +info: Entering event queue @ 1581000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1582000004000. Starting simulation... +info: Entering event queue @ 1582000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1583000004000. Starting simulation... +info: Entering event queue @ 1583000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1584000004000. Starting simulation... +info: Entering event queue @ 1584000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1585000004000. Starting simulation... +info: Entering event queue @ 1585000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1586000004000. Starting simulation... +info: Entering event queue @ 1586000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1587000004000. Starting simulation... +info: Entering event queue @ 1587000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1588000004000. Starting simulation... +info: Entering event queue @ 1588000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1589000004000. Starting simulation... +info: Entering event queue @ 1589000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1590000004000. Starting simulation... +info: Entering event queue @ 1590000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1591000004000. Starting simulation... +info: Entering event queue @ 1591000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1592000004000. Starting simulation... +info: Entering event queue @ 1592000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1593000004000. Starting simulation... +info: Entering event queue @ 1593000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1594000004000. Starting simulation... +info: Entering event queue @ 1594000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1595000004000. Starting simulation... +info: Entering event queue @ 1595000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1596000004000. Starting simulation... +info: Entering event queue @ 1596000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1597000004000. Starting simulation... +info: Entering event queue @ 1597000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1598000004000. Starting simulation... +info: Entering event queue @ 1598000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1599000004000. Starting simulation... +info: Entering event queue @ 1599000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1600000004000. Starting simulation... +info: Entering event queue @ 1600000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1601000004000. Starting simulation... +info: Entering event queue @ 1601000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1602000004000. Starting simulation... +info: Entering event queue @ 1602000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1603000004000. Starting simulation... +info: Entering event queue @ 1603000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1604000004000. Starting simulation... +info: Entering event queue @ 1604000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1605000004000. Starting simulation... +info: Entering event queue @ 1605000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1606000004000. Starting simulation... +info: Entering event queue @ 1606000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1607000004000. Starting simulation... +info: Entering event queue @ 1607000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1608000004000. Starting simulation... +info: Entering event queue @ 1608000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1609000004000. Starting simulation... +info: Entering event queue @ 1609000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1610000004000. Starting simulation... +info: Entering event queue @ 1610000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1611000004000. Starting simulation... +info: Entering event queue @ 1611000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1612000004000. Starting simulation... +info: Entering event queue @ 1612000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1613000004000. Starting simulation... +info: Entering event queue @ 1613000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1614000004000. Starting simulation... +info: Entering event queue @ 1614000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1615000004000. Starting simulation... +info: Entering event queue @ 1615000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1616000004000. Starting simulation... +info: Entering event queue @ 1616000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1617000004000. Starting simulation... +info: Entering event queue @ 1617000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1618000004000. Starting simulation... +info: Entering event queue @ 1618000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1619000004000. Starting simulation... +info: Entering event queue @ 1619000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1620000004000. Starting simulation... +info: Entering event queue @ 1620000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1621000004000. Starting simulation... +info: Entering event queue @ 1621000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1622000004000. Starting simulation... +info: Entering event queue @ 1622000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1623000004000. Starting simulation... +info: Entering event queue @ 1623000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1624000004000. Starting simulation... +info: Entering event queue @ 1624000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1625000004000. Starting simulation... +info: Entering event queue @ 1625000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1626000004000. Starting simulation... +info: Entering event queue @ 1626000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1627000004000. Starting simulation... +info: Entering event queue @ 1627000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1628000004000. Starting simulation... +info: Entering event queue @ 1628000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1629000004000. Starting simulation... +info: Entering event queue @ 1629000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1630000004000. Starting simulation... +info: Entering event queue @ 1630000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1631000004000. Starting simulation... +info: Entering event queue @ 1631000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1632000004000. Starting simulation... +info: Entering event queue @ 1632000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1633000004000. Starting simulation... +info: Entering event queue @ 1633000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1634000004000. Starting simulation... +info: Entering event queue @ 1634000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1635000004000. Starting simulation... +info: Entering event queue @ 1635000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1636000004000. Starting simulation... +info: Entering event queue @ 1636000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1637000004000. Starting simulation... +info: Entering event queue @ 1637000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1638000004000. Starting simulation... +info: Entering event queue @ 1638000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1639000004000. Starting simulation... +info: Entering event queue @ 1639000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1640000004000. Starting simulation... +info: Entering event queue @ 1640000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1641000004000. Starting simulation... +info: Entering event queue @ 1641000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1642000004000. Starting simulation... +info: Entering event queue @ 1642000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1643000004000. Starting simulation... +info: Entering event queue @ 1643000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1644000004000. Starting simulation... +info: Entering event queue @ 1644000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1645000004000. Starting simulation... +info: Entering event queue @ 1645000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1646000004000. Starting simulation... +info: Entering event queue @ 1646000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1647000004000. Starting simulation... +info: Entering event queue @ 1647000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1648000004000. Starting simulation... +info: Entering event queue @ 1648000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1649000004000. Starting simulation... +info: Entering event queue @ 1649000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1650000004000. Starting simulation... +info: Entering event queue @ 1650000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1651000004000. Starting simulation... +info: Entering event queue @ 1651000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1652000004000. Starting simulation... +info: Entering event queue @ 1652000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1653000004000. Starting simulation... +info: Entering event queue @ 1653000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1654000004000. Starting simulation... +info: Entering event queue @ 1654000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1655000004000. Starting simulation... +info: Entering event queue @ 1655000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1656000004000. Starting simulation... +info: Entering event queue @ 1656000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1657000004000. Starting simulation... +info: Entering event queue @ 1657000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1658000004000. Starting simulation... +info: Entering event queue @ 1658000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1659000004000. Starting simulation... +info: Entering event queue @ 1659000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1660000004000. Starting simulation... +info: Entering event queue @ 1660000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1661000004000. Starting simulation... +info: Entering event queue @ 1661000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1662000004000. Starting simulation... +info: Entering event queue @ 1662000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1663000004000. Starting simulation... +info: Entering event queue @ 1663000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1664000004000. Starting simulation... +info: Entering event queue @ 1664000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1665000004000. Starting simulation... +info: Entering event queue @ 1665000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1666000004000. Starting simulation... +info: Entering event queue @ 1666000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1667000004000. Starting simulation... +info: Entering event queue @ 1667000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1668000004000. Starting simulation... +info: Entering event queue @ 1668000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1669000004000. Starting simulation... +info: Entering event queue @ 1669000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1670000004000. Starting simulation... +info: Entering event queue @ 1670000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1671000004000. Starting simulation... +info: Entering event queue @ 1671000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1672000004000. Starting simulation... +info: Entering event queue @ 1672000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1673000004000. Starting simulation... +info: Entering event queue @ 1673000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1674000004000. Starting simulation... +info: Entering event queue @ 1674000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1675000004000. Starting simulation... +info: Entering event queue @ 1675000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1676000004000. Starting simulation... +info: Entering event queue @ 1676000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1677000004000. Starting simulation... +info: Entering event queue @ 1677000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1678000004000. Starting simulation... +info: Entering event queue @ 1678000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1679000004000. Starting simulation... +info: Entering event queue @ 1679000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1680000004000. Starting simulation... +info: Entering event queue @ 1680000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1681000004000. Starting simulation... +info: Entering event queue @ 1681000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1682000004000. Starting simulation... +info: Entering event queue @ 1682000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1683000004000. Starting simulation... +info: Entering event queue @ 1683000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1684000004000. Starting simulation... +info: Entering event queue @ 1684000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1685000004000. Starting simulation... +info: Entering event queue @ 1685000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1686000004000. Starting simulation... +info: Entering event queue @ 1686000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1687000004000. Starting simulation... +info: Entering event queue @ 1687000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1688000004000. Starting simulation... +info: Entering event queue @ 1688000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1689000004000. Starting simulation... +info: Entering event queue @ 1689000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1690000004000. Starting simulation... +info: Entering event queue @ 1690000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1691000004000. Starting simulation... +info: Entering event queue @ 1691000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1692000004000. Starting simulation... +info: Entering event queue @ 1692000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1693000004000. Starting simulation... +info: Entering event queue @ 1693000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1694000004000. Starting simulation... +info: Entering event queue @ 1694000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1695000004000. Starting simulation... +info: Entering event queue @ 1695000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1696000004000. Starting simulation... +info: Entering event queue @ 1696000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1697000004000. Starting simulation... +info: Entering event queue @ 1697000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1698000004000. Starting simulation... +info: Entering event queue @ 1698000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1699000004000. Starting simulation... +info: Entering event queue @ 1699000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1700000004000. Starting simulation... +info: Entering event queue @ 1700000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1701000004000. Starting simulation... +info: Entering event queue @ 1701000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1702000004000. Starting simulation... +info: Entering event queue @ 1702000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1703000004000. Starting simulation... +info: Entering event queue @ 1703000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1704000004000. Starting simulation... +info: Entering event queue @ 1704000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1705000004000. Starting simulation... +info: Entering event queue @ 1705000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1706000004000. Starting simulation... +info: Entering event queue @ 1706000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1707000004000. Starting simulation... +info: Entering event queue @ 1707000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1708000004000. Starting simulation... +info: Entering event queue @ 1708000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1709000004000. Starting simulation... +info: Entering event queue @ 1709000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1710000004000. Starting simulation... +info: Entering event queue @ 1710000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1711000004000. Starting simulation... +info: Entering event queue @ 1711000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1712000004000. Starting simulation... +info: Entering event queue @ 1712000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1713000004000. Starting simulation... +info: Entering event queue @ 1713000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1714000004000. Starting simulation... +info: Entering event queue @ 1714000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1715000004000. Starting simulation... +info: Entering event queue @ 1715000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1716000004000. Starting simulation... +info: Entering event queue @ 1716000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1717000004000. Starting simulation... +info: Entering event queue @ 1717000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1718000004000. Starting simulation... +info: Entering event queue @ 1718000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1719000004000. Starting simulation... +info: Entering event queue @ 1719000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1720000004000. Starting simulation... +info: Entering event queue @ 1720000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1721000004000. Starting simulation... +info: Entering event queue @ 1721000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1722000004000. Starting simulation... +info: Entering event queue @ 1722000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1723000004000. Starting simulation... +info: Entering event queue @ 1723000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1724000004000. Starting simulation... +info: Entering event queue @ 1724000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1725000004000. Starting simulation... +info: Entering event queue @ 1725000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1726000004000. Starting simulation... +info: Entering event queue @ 1726000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1727000004000. Starting simulation... +info: Entering event queue @ 1727000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1728000004000. Starting simulation... +info: Entering event queue @ 1728000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1729000004000. Starting simulation... +info: Entering event queue @ 1729000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1730000004000. Starting simulation... +info: Entering event queue @ 1730000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1731000004000. Starting simulation... +info: Entering event queue @ 1731000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1732000004000. Starting simulation... +info: Entering event queue @ 1732000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1733000004000. Starting simulation... +info: Entering event queue @ 1733000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1734000004000. Starting simulation... +info: Entering event queue @ 1734000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1735000004000. Starting simulation... +info: Entering event queue @ 1735000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1736000004000. Starting simulation... +info: Entering event queue @ 1736000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1737000004000. Starting simulation... +info: Entering event queue @ 1737000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1738000004000. Starting simulation... +info: Entering event queue @ 1738000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1739000004000. Starting simulation... +info: Entering event queue @ 1739000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1740000004000. Starting simulation... +info: Entering event queue @ 1740000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1741000004000. Starting simulation... +info: Entering event queue @ 1741000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1742000004000. Starting simulation... +info: Entering event queue @ 1742000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1743000004000. Starting simulation... +info: Entering event queue @ 1743000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1744000004000. Starting simulation... +info: Entering event queue @ 1744000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1745000004000. Starting simulation... +info: Entering event queue @ 1745000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1746000004000. Starting simulation... +info: Entering event queue @ 1746000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1747000004000. Starting simulation... +info: Entering event queue @ 1747000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1748000004000. Starting simulation... +info: Entering event queue @ 1748000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1749000004000. Starting simulation... +info: Entering event queue @ 1749000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1750000004000. Starting simulation... +info: Entering event queue @ 1750000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1751000004000. Starting simulation... +info: Entering event queue @ 1751000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1752000004000. Starting simulation... +info: Entering event queue @ 1752000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1753000004000. Starting simulation... +info: Entering event queue @ 1753000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1754000004000. Starting simulation... +info: Entering event queue @ 1754000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1755000004000. Starting simulation... +info: Entering event queue @ 1755000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1756000004000. Starting simulation... +info: Entering event queue @ 1756000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1757000004000. Starting simulation... +info: Entering event queue @ 1757000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1758000004000. Starting simulation... +info: Entering event queue @ 1758000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1759000004000. Starting simulation... +info: Entering event queue @ 1759000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1760000004000. Starting simulation... +info: Entering event queue @ 1760000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1761000004000. Starting simulation... +info: Entering event queue @ 1761000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1762000004000. Starting simulation... +info: Entering event queue @ 1762000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1763000004000. Starting simulation... +info: Entering event queue @ 1763000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1764000004000. Starting simulation... +info: Entering event queue @ 1764000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1765000004000. Starting simulation... +info: Entering event queue @ 1765000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1766000004000. Starting simulation... +info: Entering event queue @ 1766000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1767000004000. Starting simulation... +info: Entering event queue @ 1767000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1768000004000. Starting simulation... +info: Entering event queue @ 1768000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1769000004000. Starting simulation... +info: Entering event queue @ 1769000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1770000004000. Starting simulation... +info: Entering event queue @ 1770000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1771000004000. Starting simulation... +info: Entering event queue @ 1771000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1772000004000. Starting simulation... +info: Entering event queue @ 1772000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1773000004000. Starting simulation... +info: Entering event queue @ 1773000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1774000004000. Starting simulation... +info: Entering event queue @ 1774000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1775000004000. Starting simulation... +info: Entering event queue @ 1775000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1776000004000. Starting simulation... +info: Entering event queue @ 1776000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1777000004000. Starting simulation... +info: Entering event queue @ 1777000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1778000004000. Starting simulation... +info: Entering event queue @ 1778000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1779000004000. Starting simulation... +info: Entering event queue @ 1779000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1780000004000. Starting simulation... +info: Entering event queue @ 1780000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1781000004000. Starting simulation... +info: Entering event queue @ 1781000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1782000004000. Starting simulation... +info: Entering event queue @ 1782000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1783000004000. Starting simulation... +info: Entering event queue @ 1783000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1784000004000. Starting simulation... +info: Entering event queue @ 1784000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1785000004000. Starting simulation... +info: Entering event queue @ 1785000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1786000004000. Starting simulation... +info: Entering event queue @ 1786000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1787000004000. Starting simulation... +info: Entering event queue @ 1787000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1788000004000. Starting simulation... +info: Entering event queue @ 1788000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1789000004000. Starting simulation... +info: Entering event queue @ 1789000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1790000004000. Starting simulation... +info: Entering event queue @ 1790000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1791000004000. Starting simulation... +info: Entering event queue @ 1791000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1792000004000. Starting simulation... +info: Entering event queue @ 1792000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1793000004000. Starting simulation... +info: Entering event queue @ 1793000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1794000004000. Starting simulation... +info: Entering event queue @ 1794000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1795000004000. Starting simulation... +info: Entering event queue @ 1795000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1796000004000. Starting simulation... +info: Entering event queue @ 1796000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1797000004000. Starting simulation... +info: Entering event queue @ 1797000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1798000004000. Starting simulation... +info: Entering event queue @ 1798000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1799000004000. Starting simulation... +info: Entering event queue @ 1799000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1800000004000. Starting simulation... +info: Entering event queue @ 1800000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1801000004000. Starting simulation... +info: Entering event queue @ 1801000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1802000004000. Starting simulation... +info: Entering event queue @ 1802000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1803000004000. Starting simulation... +info: Entering event queue @ 1803000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1804000004000. Starting simulation... +info: Entering event queue @ 1804000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1805000004000. Starting simulation... +info: Entering event queue @ 1805000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1806000004000. Starting simulation... +info: Entering event queue @ 1806000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1807000004000. Starting simulation... +info: Entering event queue @ 1807000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1808000004000. Starting simulation... +info: Entering event queue @ 1808000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1809000004000. Starting simulation... +info: Entering event queue @ 1809000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1810000004000. Starting simulation... +info: Entering event queue @ 1810000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1811000004000. Starting simulation... +info: Entering event queue @ 1811000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1812000004000. Starting simulation... +info: Entering event queue @ 1812000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1813000004000. Starting simulation... +info: Entering event queue @ 1813000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1814000004000. Starting simulation... +info: Entering event queue @ 1814000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1815000004000. Starting simulation... +info: Entering event queue @ 1815000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1816000004000. Starting simulation... +info: Entering event queue @ 1816000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1817000004000. Starting simulation... +info: Entering event queue @ 1817000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1818000004000. Starting simulation... +info: Entering event queue @ 1818000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1819000004000. Starting simulation... +info: Entering event queue @ 1819000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1820000004000. Starting simulation... +info: Entering event queue @ 1820000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1821000004000. Starting simulation... +info: Entering event queue @ 1821000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1822000004000. Starting simulation... +info: Entering event queue @ 1822000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1823000004000. Starting simulation... +info: Entering event queue @ 1823000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1824000004000. Starting simulation... +info: Entering event queue @ 1824000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1825000004000. Starting simulation... +info: Entering event queue @ 1825000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1826000004000. Starting simulation... +info: Entering event queue @ 1826000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1827000004000. Starting simulation... +info: Entering event queue @ 1827000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1828000004000. Starting simulation... +info: Entering event queue @ 1828000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1829000004000. Starting simulation... +info: Entering event queue @ 1829000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1830000004000. Starting simulation... +info: Entering event queue @ 1830000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1831000004000. Starting simulation... +info: Entering event queue @ 1831000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1832000004000. Starting simulation... +info: Entering event queue @ 1832000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1833000004000. Starting simulation... +info: Entering event queue @ 1833000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1834000004000. Starting simulation... +info: Entering event queue @ 1834000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1835000004000. Starting simulation... +info: Entering event queue @ 1835000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1836000004000. Starting simulation... +info: Entering event queue @ 1836000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1837000004000. Starting simulation... +info: Entering event queue @ 1837000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1838000004000. Starting simulation... +info: Entering event queue @ 1838000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1839000004000. Starting simulation... +info: Entering event queue @ 1839000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1840000004000. Starting simulation... +info: Entering event queue @ 1840000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1841000004000. Starting simulation... +info: Entering event queue @ 1841000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1842000004000. Starting simulation... +info: Entering event queue @ 1842000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1843000004000. Starting simulation... +info: Entering event queue @ 1843000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1844000004000. Starting simulation... +info: Entering event queue @ 1844000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1845000004000. Starting simulation... +info: Entering event queue @ 1845000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1846000004000. Starting simulation... +info: Entering event queue @ 1846000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1847000004000. Starting simulation... +info: Entering event queue @ 1847000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1848000004000. Starting simulation... +info: Entering event queue @ 1848000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1849000004000. Starting simulation... +info: Entering event queue @ 1849000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1850000004000. Starting simulation... +info: Entering event queue @ 1850000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1851000004000. Starting simulation... +info: Entering event queue @ 1851000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1852000004000. Starting simulation... +info: Entering event queue @ 1852000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1853000004000. Starting simulation... +info: Entering event queue @ 1853000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1854000004000. Starting simulation... +info: Entering event queue @ 1854000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1855000004000. Starting simulation... +info: Entering event queue @ 1855000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1856000004000. Starting simulation... +info: Entering event queue @ 1856000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1857000004000. Starting simulation... +info: Entering event queue @ 1857000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1858000004000. Starting simulation... +info: Entering event queue @ 1858000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1859000004000. Starting simulation... +info: Entering event queue @ 1859000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1860000004000. Starting simulation... +info: Entering event queue @ 1860000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1861000004000. Starting simulation... +info: Entering event queue @ 1861000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1862000004000. Starting simulation... +info: Entering event queue @ 1862000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1863000004000. Starting simulation... +info: Entering event queue @ 1863000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1864000004000. Starting simulation... +info: Entering event queue @ 1864000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1865000004000. Starting simulation... +info: Entering event queue @ 1865000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1866000004000. Starting simulation... +info: Entering event queue @ 1866000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1867000004000. Starting simulation... +info: Entering event queue @ 1867000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1868000004000. Starting simulation... +info: Entering event queue @ 1868000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1869000004000. Starting simulation... +info: Entering event queue @ 1869000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1870000004000. Starting simulation... +info: Entering event queue @ 1870000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1871000004000. Starting simulation... +info: Entering event queue @ 1871000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1872000004000. Starting simulation... +info: Entering event queue @ 1872000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1873000004000. Starting simulation... +info: Entering event queue @ 1873000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1874000004000. Starting simulation... +info: Entering event queue @ 1874000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1875000004000. Starting simulation... +info: Entering event queue @ 1875000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1876000004000. Starting simulation... +info: Entering event queue @ 1876000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1877000004000. Starting simulation... +info: Entering event queue @ 1877000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1878000004000. Starting simulation... +info: Entering event queue @ 1878000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1879000004000. Starting simulation... +info: Entering event queue @ 1879000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1880000004000. Starting simulation... +info: Entering event queue @ 1880000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1881000004000. Starting simulation... +info: Entering event queue @ 1881000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1882000004000. Starting simulation... +info: Entering event queue @ 1882000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1883000004000. Starting simulation... +info: Entering event queue @ 1883000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1884000004000. Starting simulation... +info: Entering event queue @ 1884000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1885000004000. Starting simulation... +info: Entering event queue @ 1885000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1886000004000. Starting simulation... +info: Entering event queue @ 1886000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1887000004000. Starting simulation... +info: Entering event queue @ 1887000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1888000004000. Starting simulation... +info: Entering event queue @ 1888000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1889000004000. Starting simulation... +info: Entering event queue @ 1889000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1890000004000. Starting simulation... +info: Entering event queue @ 1890000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1891000004000. Starting simulation... +info: Entering event queue @ 1891000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1892000004000. Starting simulation... +info: Entering event queue @ 1892000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1893000004000. Starting simulation... +info: Entering event queue @ 1893000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1894000004000. Starting simulation... +info: Entering event queue @ 1894000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1895000004000. Starting simulation... +info: Entering event queue @ 1895000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1896000004000. Starting simulation... +info: Entering event queue @ 1896000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1897000004000. Starting simulation... +info: Entering event queue @ 1897000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1898000004000. Starting simulation... +info: Entering event queue @ 1898000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1899000004000. Starting simulation... +info: Entering event queue @ 1899000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1900000004000. Starting simulation... +info: Entering event queue @ 1900000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1901000004000. Starting simulation... +info: Entering event queue @ 1901000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1902000004000. Starting simulation... +info: Entering event queue @ 1902000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1903000004000. Starting simulation... +info: Entering event queue @ 1903000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1904000004000. Starting simulation... +info: Entering event queue @ 1904000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1905000004000. Starting simulation... +info: Entering event queue @ 1905000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1906000004000. Starting simulation... +info: Entering event queue @ 1906000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1907000004000. Starting simulation... +info: Entering event queue @ 1907000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1908000004000. Starting simulation... +info: Entering event queue @ 1908000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1909000004000. Starting simulation... +info: Entering event queue @ 1909000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1910000004000. Starting simulation... +info: Entering event queue @ 1910000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1911000004000. Starting simulation... +info: Entering event queue @ 1911000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1912000004000. Starting simulation... +info: Entering event queue @ 1912000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1913000004000. Starting simulation... +info: Entering event queue @ 1913000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1914000004000. Starting simulation... +info: Entering event queue @ 1914000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1915000004000. Starting simulation... +info: Entering event queue @ 1915000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1916000004000. Starting simulation... +info: Entering event queue @ 1916000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1917000004000. Starting simulation... +info: Entering event queue @ 1917000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1918000004000. Starting simulation... +info: Entering event queue @ 1918000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1919000004000. Starting simulation... +info: Entering event queue @ 1919000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1920000004000. Starting simulation... +info: Entering event queue @ 1920000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1921000004000. Starting simulation... +info: Entering event queue @ 1921000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1922000004000. Starting simulation... +info: Entering event queue @ 1922000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1923000004000. Starting simulation... +info: Entering event queue @ 1923000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1924000004000. Starting simulation... +info: Entering event queue @ 1924000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1925000004000. Starting simulation... +info: Entering event queue @ 1925000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1926000004000. Starting simulation... +info: Entering event queue @ 1926000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1927000004000. Starting simulation... +info: Entering event queue @ 1927000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1928000004000. Starting simulation... +info: Entering event queue @ 1928000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1929000004000. Starting simulation... +info: Entering event queue @ 1929000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1930000004000. Starting simulation... +info: Entering event queue @ 1930000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1931000004000. Starting simulation... +info: Entering event queue @ 1931000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1932000004000. Starting simulation... +info: Entering event queue @ 1932000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1933000004000. Starting simulation... +info: Entering event queue @ 1933000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1934000004000. Starting simulation... +info: Entering event queue @ 1934000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1935000004000. Starting simulation... +info: Entering event queue @ 1935000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1936000004000. Starting simulation... +info: Entering event queue @ 1936000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1937000004000. Starting simulation... +info: Entering event queue @ 1937000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1938000004000. Starting simulation... +info: Entering event queue @ 1938000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1939000004000. Starting simulation... +info: Entering event queue @ 1939000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1940000004000. Starting simulation... +info: Entering event queue @ 1940000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1941000004000. Starting simulation... +info: Entering event queue @ 1941000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1942000004000. Starting simulation... +info: Entering event queue @ 1942000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1943000004000. Starting simulation... +info: Entering event queue @ 1943000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1944000004000. Starting simulation... +info: Entering event queue @ 1944000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1945000004000. Starting simulation... +info: Entering event queue @ 1945000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1946000004000. Starting simulation... +info: Entering event queue @ 1946000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1947000004000. Starting simulation... +info: Entering event queue @ 1947000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1948000004000. Starting simulation... +info: Entering event queue @ 1948000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1949000004000. Starting simulation... +info: Entering event queue @ 1949000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1950000004000. Starting simulation... +info: Entering event queue @ 1950000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1951000004000. Starting simulation... +info: Entering event queue @ 1951000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1952000004000. Starting simulation... +info: Entering event queue @ 1952000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1953000004000. Starting simulation... +info: Entering event queue @ 1953000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1954000004000. Starting simulation... +info: Entering event queue @ 1954000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1955000004000. Starting simulation... +info: Entering event queue @ 1955000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1956000004000. Starting simulation... +info: Entering event queue @ 1956000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1957000004000. Starting simulation... +info: Entering event queue @ 1957000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1958000004000. Starting simulation... +info: Entering event queue @ 1958000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1959000004000. Starting simulation... +info: Entering event queue @ 1959000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1960000004000. Starting simulation... +info: Entering event queue @ 1960000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1961000004000. Starting simulation... +info: Entering event queue @ 1961000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1962000004000. Starting simulation... +info: Entering event queue @ 1962000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1963000004000. Starting simulation... +info: Entering event queue @ 1963000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1964000004000. Starting simulation... +info: Entering event queue @ 1964000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1965000004000. Starting simulation... +info: Entering event queue @ 1965000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1966000004000. Starting simulation... +info: Entering event queue @ 1966000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1967000004000. Starting simulation... +info: Entering event queue @ 1967000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1968000004000. Starting simulation... +info: Entering event queue @ 1968000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1969000004000. Starting simulation... +info: Entering event queue @ 1969000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1970000004000. Starting simulation... +info: Entering event queue @ 1970000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1971000004000. Starting simulation... +info: Entering event queue @ 1971000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1972000004000. Starting simulation... +info: Entering event queue @ 1972000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1973000004000. Starting simulation... +info: Entering event queue @ 1973000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1974000004000. Starting simulation... +info: Entering event queue @ 1974000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1975000004000. Starting simulation... +info: Entering event queue @ 1975000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1976000004000. Starting simulation... +info: Entering event queue @ 1976000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1977000004000. Starting simulation... +info: Entering event queue @ 1977000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1978000004000. Starting simulation... +info: Entering event queue @ 1978000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1979000004000. Starting simulation... +info: Entering event queue @ 1979000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1980000004000. Starting simulation... +info: Entering event queue @ 1980000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1981000004000. Starting simulation... +info: Entering event queue @ 1981000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1982000004000. Starting simulation... +info: Entering event queue @ 1982000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1983000004000. Starting simulation... +info: Entering event queue @ 1983000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1984000004000. Starting simulation... +info: Entering event queue @ 1984000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1985000004000. Starting simulation... +info: Entering event queue @ 1985000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1986000004000. Starting simulation... +info: Entering event queue @ 1986000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1987000004000. Starting simulation... +info: Entering event queue @ 1987000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1988000004000. Starting simulation... +info: Entering event queue @ 1988000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1989000004000. Starting simulation... +info: Entering event queue @ 1989000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1990000004000. Starting simulation... +info: Entering event queue @ 1990000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1991000004000. Starting simulation... +info: Entering event queue @ 1991000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1992000004000. Starting simulation... +info: Entering event queue @ 1992000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1993000004000. Starting simulation... +info: Entering event queue @ 1993000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1994000004000. Starting simulation... +info: Entering event queue @ 1994000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1995000004000. Starting simulation... +info: Entering event queue @ 1995000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1996000004000. Starting simulation... +info: Entering event queue @ 1996000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1997000004000. Starting simulation... +info: Entering event queue @ 1997000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1998000004000. Starting simulation... +info: Entering event queue @ 1998000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 1999000004000. Starting simulation... +info: Entering event queue @ 1999000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2000000004000. Starting simulation... +info: Entering event queue @ 2000000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2001000004000. Starting simulation... +info: Entering event queue @ 2001000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2002000004000. Starting simulation... +info: Entering event queue @ 2002000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2003000004000. Starting simulation... +info: Entering event queue @ 2003000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2004000004000. Starting simulation... +info: Entering event queue @ 2004000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2005000004000. Starting simulation... +info: Entering event queue @ 2005000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2006000004000. Starting simulation... +info: Entering event queue @ 2006000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2007000004000. Starting simulation... +info: Entering event queue @ 2007000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2008000004000. Starting simulation... +info: Entering event queue @ 2008000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2009000004000. Starting simulation... +info: Entering event queue @ 2009000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2010000004000. Starting simulation... +info: Entering event queue @ 2010000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2011000004000. Starting simulation... +info: Entering event queue @ 2011000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2012000004000. Starting simulation... +info: Entering event queue @ 2012000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2013000004000. Starting simulation... +info: Entering event queue @ 2013000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2014000004000. Starting simulation... +info: Entering event queue @ 2014000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2015000004000. Starting simulation... +info: Entering event queue @ 2015000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2016000004000. Starting simulation... +info: Entering event queue @ 2016000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2017000004000. Starting simulation... +info: Entering event queue @ 2017000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2018000004000. Starting simulation... +info: Entering event queue @ 2018000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2019000004000. Starting simulation... +info: Entering event queue @ 2019000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2020000004000. Starting simulation... +info: Entering event queue @ 2020000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2021000004000. Starting simulation... +info: Entering event queue @ 2021000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2022000004000. Starting simulation... +info: Entering event queue @ 2022000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2023000004000. Starting simulation... +info: Entering event queue @ 2023000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2024000004000. Starting simulation... +info: Entering event queue @ 2024000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2025000004000. Starting simulation... +info: Entering event queue @ 2025000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2026000004000. Starting simulation... +info: Entering event queue @ 2026000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2027000004000. Starting simulation... +info: Entering event queue @ 2027000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2028000004000. Starting simulation... +info: Entering event queue @ 2028000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2029000004000. Starting simulation... +info: Entering event queue @ 2029000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2030000004000. Starting simulation... +info: Entering event queue @ 2030000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2031000004000. Starting simulation... +info: Entering event queue @ 2031000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2032000004000. Starting simulation... +info: Entering event queue @ 2032000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2033000004000. Starting simulation... +info: Entering event queue @ 2033000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2034000004000. Starting simulation... +info: Entering event queue @ 2034000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2035000004000. Starting simulation... +info: Entering event queue @ 2035000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2036000004000. Starting simulation... +info: Entering event queue @ 2036000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2037000004000. Starting simulation... +info: Entering event queue @ 2037000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2038000004000. Starting simulation... +info: Entering event queue @ 2038000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2039000004000. Starting simulation... +info: Entering event queue @ 2039000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2040000004000. Starting simulation... +info: Entering event queue @ 2040000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2041000004000. Starting simulation... +info: Entering event queue @ 2041000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2042000004000. Starting simulation... +info: Entering event queue @ 2042000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2043000004000. Starting simulation... +info: Entering event queue @ 2043000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2044000004000. Starting simulation... +info: Entering event queue @ 2044000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2045000004000. Starting simulation... +info: Entering event queue @ 2045000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2046000004000. Starting simulation... +info: Entering event queue @ 2046000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2047000004000. Starting simulation... +info: Entering event queue @ 2047000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2048000004000. Starting simulation... +info: Entering event queue @ 2048000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2049000004000. Starting simulation... +info: Entering event queue @ 2049000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2050000004000. Starting simulation... +info: Entering event queue @ 2050000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2051000004000. Starting simulation... +info: Entering event queue @ 2051000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2052000004000. Starting simulation... +info: Entering event queue @ 2052000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2053000004000. Starting simulation... +info: Entering event queue @ 2053000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2054000004000. Starting simulation... +info: Entering event queue @ 2054000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2055000004000. Starting simulation... +info: Entering event queue @ 2055000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2056000004000. Starting simulation... +info: Entering event queue @ 2056000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2057000004000. Starting simulation... +info: Entering event queue @ 2057000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2058000004000. Starting simulation... +info: Entering event queue @ 2058000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2059000004000. Starting simulation... +info: Entering event queue @ 2059000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2060000004000. Starting simulation... +info: Entering event queue @ 2060000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2061000004000. Starting simulation... +info: Entering event queue @ 2061000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2062000004000. Starting simulation... +info: Entering event queue @ 2062000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2063000004000. Starting simulation... +info: Entering event queue @ 2063000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2064000004000. Starting simulation... +info: Entering event queue @ 2064000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2065000004000. Starting simulation... +info: Entering event queue @ 2065000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2066000004000. Starting simulation... +info: Entering event queue @ 2066000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2067000004000. Starting simulation... +info: Entering event queue @ 2067000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2068000004000. Starting simulation... +info: Entering event queue @ 2068000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2069000004000. Starting simulation... +info: Entering event queue @ 2069000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2070000004000. Starting simulation... +info: Entering event queue @ 2070000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2071000004000. Starting simulation... +info: Entering event queue @ 2071000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2072000004000. Starting simulation... +info: Entering event queue @ 2072000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2073000004000. Starting simulation... +info: Entering event queue @ 2073000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2074000004000. Starting simulation... +info: Entering event queue @ 2074000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2075000004000. Starting simulation... +info: Entering event queue @ 2075000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2076000004000. Starting simulation... +info: Entering event queue @ 2076000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2077000004000. Starting simulation... +info: Entering event queue @ 2077000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2078000004000. Starting simulation... +info: Entering event queue @ 2078000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2079000004000. Starting simulation... +info: Entering event queue @ 2079000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2080000004000. Starting simulation... +info: Entering event queue @ 2080000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2081000004000. Starting simulation... +info: Entering event queue @ 2081000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2082000004000. Starting simulation... +info: Entering event queue @ 2082000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2083000004000. Starting simulation... +info: Entering event queue @ 2083000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2084000004000. Starting simulation... +info: Entering event queue @ 2084000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2085000004000. Starting simulation... +info: Entering event queue @ 2085000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2086000004000. Starting simulation... +info: Entering event queue @ 2086000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2087000004000. Starting simulation... +info: Entering event queue @ 2087000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2088000004000. Starting simulation... +info: Entering event queue @ 2088000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2089000004000. Starting simulation... +info: Entering event queue @ 2089000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2090000004000. Starting simulation... +info: Entering event queue @ 2090000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2091000004000. Starting simulation... +info: Entering event queue @ 2091000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2092000004000. Starting simulation... +info: Entering event queue @ 2092000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2093000004000. Starting simulation... +info: Entering event queue @ 2093000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2094000004000. Starting simulation... +info: Entering event queue @ 2094000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2095000004000. Starting simulation... +info: Entering event queue @ 2095000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2096000004000. Starting simulation... +info: Entering event queue @ 2096000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2097000004000. Starting simulation... +info: Entering event queue @ 2097000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2098000004000. Starting simulation... +info: Entering event queue @ 2098000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2099000004000. Starting simulation... +info: Entering event queue @ 2099000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2100000004000. Starting simulation... +info: Entering event queue @ 2100000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2101000004000. Starting simulation... +info: Entering event queue @ 2101000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2102000004000. Starting simulation... +info: Entering event queue @ 2102000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2103000004000. Starting simulation... +info: Entering event queue @ 2103000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2104000004000. Starting simulation... +info: Entering event queue @ 2104000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2105000004000. Starting simulation... +info: Entering event queue @ 2105000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2106000004000. Starting simulation... +info: Entering event queue @ 2106000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2107000004000. Starting simulation... +info: Entering event queue @ 2107000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2108000004000. Starting simulation... +info: Entering event queue @ 2108000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2109000004000. Starting simulation... +info: Entering event queue @ 2109000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2110000004000. Starting simulation... +info: Entering event queue @ 2110000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2111000004000. Starting simulation... +info: Entering event queue @ 2111000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2112000004000. Starting simulation... +info: Entering event queue @ 2112000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2113000004000. Starting simulation... +info: Entering event queue @ 2113000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2114000004000. Starting simulation... +info: Entering event queue @ 2114000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2115000004000. Starting simulation... +info: Entering event queue @ 2115000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2116000004000. Starting simulation... +info: Entering event queue @ 2116000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2117000004000. Starting simulation... +info: Entering event queue @ 2117000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2118000004000. Starting simulation... +info: Entering event queue @ 2118000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2119000004000. Starting simulation... +info: Entering event queue @ 2119000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2120000004000. Starting simulation... +info: Entering event queue @ 2120000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2121000004000. Starting simulation... +info: Entering event queue @ 2121000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2122000004000. Starting simulation... +info: Entering event queue @ 2122000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2123000004000. Starting simulation... +info: Entering event queue @ 2123000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2124000004000. Starting simulation... +info: Entering event queue @ 2124000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2125000004000. Starting simulation... +info: Entering event queue @ 2125000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2126000004000. Starting simulation... +info: Entering event queue @ 2126000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2127000004000. Starting simulation... +info: Entering event queue @ 2127000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2128000004000. Starting simulation... +info: Entering event queue @ 2128000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2129000004000. Starting simulation... +info: Entering event queue @ 2129000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2130000004000. Starting simulation... +info: Entering event queue @ 2130000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2131000004000. Starting simulation... +info: Entering event queue @ 2131000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2132000004000. Starting simulation... +info: Entering event queue @ 2132000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2133000004000. Starting simulation... +info: Entering event queue @ 2133000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2134000004000. Starting simulation... +info: Entering event queue @ 2134000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2135000004000. Starting simulation... +info: Entering event queue @ 2135000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2136000004000. Starting simulation... +info: Entering event queue @ 2136000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2137000004000. Starting simulation... +info: Entering event queue @ 2137000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2138000004000. Starting simulation... +info: Entering event queue @ 2138000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2139000004000. Starting simulation... +info: Entering event queue @ 2139000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2140000004000. Starting simulation... +info: Entering event queue @ 2140000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2141000004000. Starting simulation... +info: Entering event queue @ 2141000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2142000004000. Starting simulation... +info: Entering event queue @ 2142000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2143000004000. Starting simulation... +info: Entering event queue @ 2143000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2144000004000. Starting simulation... +info: Entering event queue @ 2144000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2145000004000. Starting simulation... +info: Entering event queue @ 2145000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2146000004000. Starting simulation... +info: Entering event queue @ 2146000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2147000004000. Starting simulation... +info: Entering event queue @ 2147000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2148000004000. Starting simulation... +info: Entering event queue @ 2148000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2149000004000. Starting simulation... +info: Entering event queue @ 2149000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2150000004000. Starting simulation... +info: Entering event queue @ 2150000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2151000004000. Starting simulation... +info: Entering event queue @ 2151000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2152000004000. Starting simulation... +info: Entering event queue @ 2152000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2153000004000. Starting simulation... +info: Entering event queue @ 2153000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2154000004000. Starting simulation... +info: Entering event queue @ 2154000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2155000004000. Starting simulation... +info: Entering event queue @ 2155000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2156000004000. Starting simulation... +info: Entering event queue @ 2156000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2157000004000. Starting simulation... +info: Entering event queue @ 2157000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2158000004000. Starting simulation... +info: Entering event queue @ 2158000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2159000004000. Starting simulation... +info: Entering event queue @ 2159000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2160000004000. Starting simulation... +info: Entering event queue @ 2160000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2161000004000. Starting simulation... +info: Entering event queue @ 2161000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2162000004000. Starting simulation... +info: Entering event queue @ 2162000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2163000004000. Starting simulation... +info: Entering event queue @ 2163000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2164000004000. Starting simulation... +info: Entering event queue @ 2164000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2165000004000. Starting simulation... +info: Entering event queue @ 2165000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2166000004000. Starting simulation... +info: Entering event queue @ 2166000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2167000004000. Starting simulation... +info: Entering event queue @ 2167000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2168000004000. Starting simulation... +info: Entering event queue @ 2168000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2169000004000. Starting simulation... +info: Entering event queue @ 2169000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2170000004000. Starting simulation... +info: Entering event queue @ 2170000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2171000004000. Starting simulation... +info: Entering event queue @ 2171000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2172000004000. Starting simulation... +info: Entering event queue @ 2172000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2173000004000. Starting simulation... +info: Entering event queue @ 2173000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2174000004000. Starting simulation... +info: Entering event queue @ 2174000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2175000004000. Starting simulation... +info: Entering event queue @ 2175000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2176000004000. Starting simulation... +info: Entering event queue @ 2176000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2177000004000. Starting simulation... +info: Entering event queue @ 2177000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2178000004000. Starting simulation... +info: Entering event queue @ 2178000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2179000004000. Starting simulation... +info: Entering event queue @ 2179000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2180000004000. Starting simulation... +info: Entering event queue @ 2180000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2181000004000. Starting simulation... +info: Entering event queue @ 2181000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2182000004000. Starting simulation... +info: Entering event queue @ 2182000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2183000004000. Starting simulation... +info: Entering event queue @ 2183000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2184000004000. Starting simulation... +info: Entering event queue @ 2184000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2185000004000. Starting simulation... +info: Entering event queue @ 2185000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2186000004000. Starting simulation... +info: Entering event queue @ 2186000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2187000004000. Starting simulation... +info: Entering event queue @ 2187000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2188000004000. Starting simulation... +info: Entering event queue @ 2188000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2189000004000. Starting simulation... +info: Entering event queue @ 2189000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2190000004000. Starting simulation... +info: Entering event queue @ 2190000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2191000004000. Starting simulation... +info: Entering event queue @ 2191000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2192000004000. Starting simulation... +info: Entering event queue @ 2192000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2193000004000. Starting simulation... +info: Entering event queue @ 2193000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2194000004000. Starting simulation... +info: Entering event queue @ 2194000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2195000004000. Starting simulation... +info: Entering event queue @ 2195000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2196000004000. Starting simulation... +info: Entering event queue @ 2196000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2197000004000. Starting simulation... +info: Entering event queue @ 2197000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2198000004000. Starting simulation... +info: Entering event queue @ 2198000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2199000004000. Starting simulation... +info: Entering event queue @ 2199000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2200000004000. Starting simulation... +info: Entering event queue @ 2200000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2201000004000. Starting simulation... +info: Entering event queue @ 2201000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2202000004000. Starting simulation... +info: Entering event queue @ 2202000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2203000004000. Starting simulation... +info: Entering event queue @ 2203000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2204000004000. Starting simulation... +info: Entering event queue @ 2204000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2205000004000. Starting simulation... +info: Entering event queue @ 2205000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2206000004000. Starting simulation... +info: Entering event queue @ 2206000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2207000004000. Starting simulation... +info: Entering event queue @ 2207000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2208000004000. Starting simulation... +info: Entering event queue @ 2208000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2209000004000. Starting simulation... +info: Entering event queue @ 2209000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2210000004000. Starting simulation... +info: Entering event queue @ 2210000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2211000004000. Starting simulation... +info: Entering event queue @ 2211000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2212000004000. Starting simulation... +info: Entering event queue @ 2212000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2213000004000. Starting simulation... +info: Entering event queue @ 2213000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2214000004000. Starting simulation... +info: Entering event queue @ 2214000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2215000004000. Starting simulation... +info: Entering event queue @ 2215000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2216000004000. Starting simulation... +info: Entering event queue @ 2216000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2217000004000. Starting simulation... +info: Entering event queue @ 2217000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2218000004000. Starting simulation... +info: Entering event queue @ 2218000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2219000004000. Starting simulation... +info: Entering event queue @ 2219000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2220000004000. Starting simulation... +info: Entering event queue @ 2220000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2221000004000. Starting simulation... +info: Entering event queue @ 2221000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2222000004000. Starting simulation... +info: Entering event queue @ 2222000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2223000004000. Starting simulation... +info: Entering event queue @ 2223000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2224000004000. Starting simulation... +info: Entering event queue @ 2224000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2225000004000. Starting simulation... +info: Entering event queue @ 2225000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2226000004000. Starting simulation... +info: Entering event queue @ 2226000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2227000004000. Starting simulation... +info: Entering event queue @ 2227000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2228000004000. Starting simulation... +info: Entering event queue @ 2228000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2229000004000. Starting simulation... +info: Entering event queue @ 2229000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2230000004000. Starting simulation... +info: Entering event queue @ 2230000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2231000004000. Starting simulation... +info: Entering event queue @ 2231000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2232000004000. Starting simulation... +info: Entering event queue @ 2232000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2233000004000. Starting simulation... +info: Entering event queue @ 2233000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2234000004000. Starting simulation... +info: Entering event queue @ 2234000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2235000004000. Starting simulation... +info: Entering event queue @ 2235000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2236000004000. Starting simulation... +info: Entering event queue @ 2236000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2237000004000. Starting simulation... +info: Entering event queue @ 2237000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2238000004000. Starting simulation... +info: Entering event queue @ 2238000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2239000004000. Starting simulation... +info: Entering event queue @ 2239000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2240000004000. Starting simulation... +info: Entering event queue @ 2240000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2241000004000. Starting simulation... +info: Entering event queue @ 2241000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2242000004000. Starting simulation... +info: Entering event queue @ 2242000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2243000004000. Starting simulation... +info: Entering event queue @ 2243000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2244000004000. Starting simulation... +info: Entering event queue @ 2244000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2245000004000. Starting simulation... +info: Entering event queue @ 2245000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2246000004000. Starting simulation... +info: Entering event queue @ 2246000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2247000004000. Starting simulation... +info: Entering event queue @ 2247000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2248000004000. Starting simulation... +info: Entering event queue @ 2248000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2249000004000. Starting simulation... +info: Entering event queue @ 2249000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2250000004000. Starting simulation... +info: Entering event queue @ 2250000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2251000004000. Starting simulation... +info: Entering event queue @ 2251000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2252000004000. Starting simulation... +info: Entering event queue @ 2252000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2253000004000. Starting simulation... +info: Entering event queue @ 2253000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2254000004000. Starting simulation... +info: Entering event queue @ 2254000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2255000004000. Starting simulation... +info: Entering event queue @ 2255000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2256000004000. Starting simulation... +info: Entering event queue @ 2256000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2257000004000. Starting simulation... +info: Entering event queue @ 2257000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2258000004000. Starting simulation... +info: Entering event queue @ 2258000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2259000004000. Starting simulation... +info: Entering event queue @ 2259000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2260000004000. Starting simulation... +info: Entering event queue @ 2260000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2261000004000. Starting simulation... +info: Entering event queue @ 2261000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2262000004000. Starting simulation... +info: Entering event queue @ 2262000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2263000004000. Starting simulation... +info: Entering event queue @ 2263000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2264000004000. Starting simulation... +info: Entering event queue @ 2264000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2265000004000. Starting simulation... +info: Entering event queue @ 2265000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2266000004000. Starting simulation... +info: Entering event queue @ 2266000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2267000004000. Starting simulation... +info: Entering event queue @ 2267000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2268000004000. Starting simulation... +info: Entering event queue @ 2268000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2269000004000. Starting simulation... +info: Entering event queue @ 2269000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2270000004000. Starting simulation... +info: Entering event queue @ 2270000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2271000004000. Starting simulation... +info: Entering event queue @ 2271000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2272000004000. Starting simulation... +info: Entering event queue @ 2272000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2273000004000. Starting simulation... +info: Entering event queue @ 2273000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2274000004000. Starting simulation... +info: Entering event queue @ 2274000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2275000004000. Starting simulation... +info: Entering event queue @ 2275000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2276000004000. Starting simulation... +info: Entering event queue @ 2276000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2277000004000. Starting simulation... +info: Entering event queue @ 2277000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2278000004000. Starting simulation... +info: Entering event queue @ 2278000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2279000004000. Starting simulation... +info: Entering event queue @ 2279000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2280000004000. Starting simulation... +info: Entering event queue @ 2280000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2281000004000. Starting simulation... +info: Entering event queue @ 2281000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2282000004000. Starting simulation... +info: Entering event queue @ 2282000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2283000004000. Starting simulation... +info: Entering event queue @ 2283000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2284000004000. Starting simulation... +info: Entering event queue @ 2284000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2285000004000. Starting simulation... +info: Entering event queue @ 2285000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2286000004000. Starting simulation... +info: Entering event queue @ 2286000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2287000004000. Starting simulation... +info: Entering event queue @ 2287000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2288000004000. Starting simulation... +info: Entering event queue @ 2288000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2289000004000. Starting simulation... +info: Entering event queue @ 2289000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2290000004000. Starting simulation... +info: Entering event queue @ 2290000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2291000004000. Starting simulation... +info: Entering event queue @ 2291000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2292000004000. Starting simulation... +info: Entering event queue @ 2292000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2293000004000. Starting simulation... +info: Entering event queue @ 2293000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2294000004000. Starting simulation... +info: Entering event queue @ 2294000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2295000004000. Starting simulation... switching cpus -info: Entering event queue @ 2295000006000. Starting simulation... +info: Entering event queue @ 2295000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2296000006000. Starting simulation... +info: Entering event queue @ 2296000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2297000006000. Starting simulation... +info: Entering event queue @ 2297000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2298000006000. Starting simulation... +info: Entering event queue @ 2298000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2299000006000. Starting simulation... +info: Entering event queue @ 2299000013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2300000013500. Starting simulation... switching cpus -info: Entering event queue @ 2300000006000. Starting simulation... +info: Entering event queue @ 2300000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2301000006000. Starting simulation... +info: Entering event queue @ 2301000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2302000006000. Starting simulation... +info: Entering event queue @ 2302000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2303000006000. Starting simulation... +info: Entering event queue @ 2303000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2304000006000. Starting simulation... +info: Entering event queue @ 2304000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2305000006000. Starting simulation... +info: Entering event queue @ 2305000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2306000006000. Starting simulation... +info: Entering event queue @ 2306000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2307000006000. Starting simulation... +info: Entering event queue @ 2307000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2308000006000. Starting simulation... +info: Entering event queue @ 2308000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2309000006000. Starting simulation... +info: Entering event queue @ 2309000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2310000006000. Starting simulation... +info: Entering event queue @ 2310000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2311000006000. Starting simulation... +info: Entering event queue @ 2311000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2312000006000. Starting simulation... +info: Entering event queue @ 2312000016000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2313000006000. Starting simulation... +info: Entering event queue @ 2313000016000. Starting simulation... switching cpus -info: Entering event queue @ 2313000010500. Starting simulation... +info: Entering event queue @ 2313000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2314000010500. Starting simulation... +info: Entering event queue @ 2314000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2315000010500. Starting simulation... +info: Entering event queue @ 2315000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2316000010500. Starting simulation... +info: Entering event queue @ 2316000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2317000010500. Starting simulation... +info: Entering event queue @ 2317000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2318000010500. Starting simulation... +info: Entering event queue @ 2318000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2319000010500. Starting simulation... +info: Entering event queue @ 2319000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2320000010500. Starting simulation... +info: Entering event queue @ 2320000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2321000010500. Starting simulation... +info: Entering event queue @ 2321000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2322000010500. Starting simulation... +info: Entering event queue @ 2322000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2323000010500. Starting simulation... +info: Entering event queue @ 2323000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2324000010500. Starting simulation... +info: Entering event queue @ 2324000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2325000010500. Starting simulation... +info: Entering event queue @ 2325000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2326000010500. Starting simulation... +info: Entering event queue @ 2326000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2327000010500. Starting simulation... +info: Entering event queue @ 2327000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2328000010500. Starting simulation... +info: Entering event queue @ 2328000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2329000010500. Starting simulation... +info: Entering event queue @ 2329000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2330000010500. Starting simulation... +info: Entering event queue @ 2330000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU switching cpus -info: Entering event queue @ 2331000010500. Starting simulation... +info: Entering event queue @ 2331000020000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2332000020000. Starting simulation... switching cpus -info: Entering event queue @ 2332000010500. Starting simulation... +info: Entering event queue @ 2332000020500. Starting simulation... diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 33d5e9d03..e70b188fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table +children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -53,7 +54,7 @@ oem_table_id= [system.apicbridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=11529215046068469760:11529215046068473855 req_size=16 @@ -63,20 +64,24 @@ slave=system.iobus.master[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 master=system.iobus.slave[0] -slave=system.membus.master[1] +slave=system.membus.master[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer -branchPred=Null +children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -95,6 +100,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -105,12 +114,17 @@ workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain + [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -121,12 +135,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=X86TLB children=walker @@ -135,16 +158,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -155,18 +179,27 @@ prefetcher=Null response_latency=2 size=1024 system=system +tags=system.cpu.dtb_walker_cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port mem_side=system.cpu.toL2Bus.slave[3] +[system.cpu.dtb_walker_cache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=1024 + [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -177,22 +210,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=X86LocalApic -clock=8000 +clk_domain=system.cpu.apic_clk_domain int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system int_master=system.membus.slave[3] -int_slave=system.membus.master[3] -pio=system.membus.master[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.isa] type=X86ISA @@ -205,16 +247,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -225,18 +268,27 @@ prefetcher=Null response_latency=2 size=1024 system=system +tags=system.cpu.itb_walker_cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port mem_side=system.cpu.toL2Bus.slave[2] +[system.cpu.itb_walker_cache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=1024 + [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -247,16 +299,24 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -267,6 +327,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 @@ -638,8 +703,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -649,10 +713,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -663,28 +727,36 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] mem_side=system.membus.slave[4] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -707,7 +779,7 @@ system=system [system.pc.behind_pci] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -725,7 +797,7 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal -clock=1000 +clk_domain=system.clk_domain pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -749,7 +821,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -766,7 +838,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -783,7 +855,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -800,7 +872,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -817,7 +889,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -835,7 +907,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.pc size=16777216 @@ -858,7 +931,7 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin -clock=1000 +clk_domain=system.clk_domain int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -871,7 +944,7 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 -clock=1000 +clk_domain=system.clk_domain pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -918,7 +991,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 @@ -950,7 +1023,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -970,7 +1043,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1053,7 +1126,7 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 -clock=1000 +clk_domain=system.clk_domain external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1065,7 +1138,7 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin -clock=1000 +clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin @@ -1084,7 +1157,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output -clock=1000 +clk_domain=system.clk_domain mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1099,7 +1172,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output -clock=1000 +clk_domain=system.clk_domain mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1114,7 +1187,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin -clock=1000 +clk_domain=system.clk_domain int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1126,7 +1199,7 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker -clock=1000 +clk_domain=system.clk_domain i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1136,19 +1209,24 @@ pio=system.iobus.master[9] [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -1159,8 +1237,7 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[0] +port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable @@ -1183,3 +1260,7 @@ starting_addr_segment=0 vendor= version= +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 451dd9824..2013fc7c1 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 18 2013 13:37:41 -gem5 started Apr 18 2013 14:20:21 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 07:08:04 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112099861500 because m5_exit instruction encountered +Exiting @ tick 5112102211000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 640918742..032606990 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table +children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -53,7 +54,7 @@ oem_table_id= [system.apicbridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=11529215046068469760:11529215046068473855 req_size=16 @@ -63,20 +64,24 @@ slave=system.iobus.master[0] [system.bridge] type=Bridge -clock=1000 +clk_domain=system.clk_domain delay=50000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 master=system.iobus.slave[0] -slave=system.membus.master[1] +slave=system.membus.master[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer -branchPred=Null +children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -94,6 +99,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -101,12 +107,17 @@ workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain + [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -117,12 +128,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.dtb] type=X86TLB children=walker @@ -131,16 +151,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -151,18 +172,27 @@ prefetcher=Null response_latency=2 size=1024 system=system +tags=system.cpu.dtb_walker_cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port mem_side=system.cpu.toL2Bus.slave[3] +[system.cpu.dtb_walker_cache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=1024 + [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -173,22 +203,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu.interrupts] type=X86LocalApic -clock=8000 +clk_domain=system.cpu.apic_clk_domain int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system int_master=system.membus.slave[3] -int_slave=system.membus.master[3] -pio=system.membus.master[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.isa] type=X86ISA @@ -201,16 +240,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -221,18 +261,27 @@ prefetcher=Null response_latency=2 size=1024 system=system +tags=system.cpu.itb_walker_cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port mem_side=system.cpu.toL2Bus.slave[2] +[system.cpu.itb_walker_cache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=1024 + [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -243,16 +292,24 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -263,6 +320,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 @@ -634,8 +696,7 @@ sys=system [system.iobus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=true width=8 @@ -645,10 +706,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge [system.iocache] type=BaseCache +children=tags addr_ranges=0:134217727 assoc=8 -block_size=64 -clock=1000 +clk_domain=system.clk_domain forward_snoops=false hit_latency=50 is_top_level=true @@ -659,28 +720,36 @@ prefetcher=Null response_latency=50 size=1024 system=system +tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] mem_side=system.membus.slave[4] +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +hit_latency=50 +size=1024 + [system.membus] type=CoherentBus children=badaddr_responder -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=0 pio_latency=100000 @@ -703,7 +772,7 @@ system=system [system.pc.behind_pci] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -721,7 +790,7 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal -clock=1000 +clk_domain=system.clk_domain pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -745,7 +814,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -762,7 +831,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -779,7 +848,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -796,7 +865,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -813,7 +882,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake -clock=1000 +clk_domain=system.clk_domain fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -831,7 +900,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -clock=1000 +clk_domain=system.clk_domain +pio_addr=0 pio_latency=30000 platform=system.pc size=16777216 @@ -854,7 +924,7 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin -clock=1000 +clk_domain=system.clk_domain int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -867,7 +937,7 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 -clock=1000 +clk_domain=system.clk_domain pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -914,7 +984,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1000 +clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 @@ -946,7 +1016,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -966,7 +1036,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1049,7 +1119,7 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 -clock=1000 +clk_domain=system.clk_domain external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1061,7 +1131,7 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin -clock=1000 +clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin @@ -1080,7 +1150,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output -clock=1000 +clk_domain=system.clk_domain mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1095,7 +1165,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output -clock=1000 +clk_domain=system.clk_domain mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1110,7 +1180,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin -clock=1000 +clk_domain=system.clk_domain int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1122,7 +1192,7 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker -clock=1000 +clk_domain=system.clk_domain i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1132,19 +1202,24 @@ pio=system.iobus.master[9] [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -1155,8 +1230,7 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false -port=system.membus.master[0] +port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable @@ -1179,3 +1253,7 @@ starting_addr_segment=0 vendor= version= +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index c33799826..00f397a8d 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 18 2013 13:37:41 -gem5 started Apr 18 2013 13:43:22 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 06:25:04 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5187335906000 because m5_exit instruction encountered +Exiting @ tick 5196173457000 because m5_exit instruction encountered -- cgit v1.2.3