From fa1fbcf020ee9aacdd4a7a09e81a633e09bad97a Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 1 Sep 2014 16:55:52 -0500
Subject: stats: updates due to recent ruby and x86 changes Also updates many
 out of date config files.

---
 .../ref/alpha/linux/inorder-timing/config.ini      | 43 ++++++++++++++++------
 1 file changed, 32 insertions(+), 11 deletions(-)

(limited to 'tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini')

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 38d5b70ef..24e61bda7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -36,7 +38,9 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -78,6 +82,7 @@ numThreads=1
 profile=0
 progress_interval=0
 simpoint_start_insts=
+socket_id=0
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -253,7 +258,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/test-progs/hello/bin/alpha/linux/hello
+executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -267,9 +272,19 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
@@ -282,9 +297,9 @@ master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -295,27 +310,33 @@ device_rowbuffer_size=1024
 devices_per_rank=8
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCK=1250
 tCL=13750
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[0]
 
 [system.voltage_domain]
-- 
cgit v1.2.3