From 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 24 Jan 2013 12:29:00 -0600 Subject: regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables. --- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 57 +++++++++------------- .../se/00.hello/ref/alpha/linux/o3-timing/simout | 8 +-- .../00.hello/ref/alpha/linux/o3-timing/stats.txt | 27 +++++----- 3 files changed, 43 insertions(+), 49 deletions(-) (limited to 'tests/quick/se/00.hello/ref/alpha/linux/o3-timing') diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 8465ac1d0..beec6d00f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -56,7 +53,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -116,6 +103,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -125,6 +113,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -132,21 +138,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +427,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -463,21 +459,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -504,7 +495,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 9cdc62046..acb604328 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:02:14 -gem5 started Oct 30 2012 11:20:12 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 14:07:24 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 56f807ea0..a295cf48e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 15802500 # Number of ticks simulated final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38730 # Simulator instruction rate (inst/s) -host_op_rate 38726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96032767 # Simulator tick rate (ticks/s) -host_mem_usage 214332 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 36566 # Simulator instruction rate (inst/s) +host_op_rate 36562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90663114 # Simulator tick rate (ticks/s) +host_mem_usage 270656 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 32145.79 # Average gap between requests +system.cpu.branchPred.lookups 2927 # Number of BP lookups +system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups +system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 31606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2927 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered -- cgit v1.2.3