From 19cc023cf51268f3c4f3a83d95319f37660d94f7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 28 Jul 2012 13:48:04 -0400 Subject: stats: fix some miss-committed changes from the icache change --- .../simple-timing-ruby-MOESI_hammer/config.ini | 63 +++++++++++++++------- .../linux/simple-timing-ruby-MOESI_hammer/simout | 4 +- .../simple-timing-ruby-MOESI_hammer/stats.txt | 34 ++++++++++-- 3 files changed, 74 insertions(+), 27 deletions(-) (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer') diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index c7cccc96e..f5efe89cb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -138,11 +138,16 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=1 replacement_policy=PSEUDO_LRU +resourceStalls=false size=1024 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0] type=L1Cache_Controller @@ -167,29 +172,44 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU +resourceStalls=false size=256 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU +resourceStalls=false size=256 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU +resourceStalls=false size=512 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -242,61 +262,64 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_links0 int_links1 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 +routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b [system.ruby.network.topology.ext_links0] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 +int_node=system.ruby.network.topology.ext_links0.int_node latency=1 link_id=0 weight=1 +[system.ruby.network.topology.ext_links0.int_node] +type=BasicRouter +router_id=0 + [system.ruby.network.topology.ext_links1] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers1 +int_node=system.ruby.network.topology.ext_links1.int_node latency=1 link_id=1 weight=1 +[system.ruby.network.topology.ext_links1.int_node] +type=BasicRouter +router_id=1 + [system.ruby.network.topology.int_links0] type=SimpleIntLink +children=node_b bandwidth_factor=16 latency=1 link_id=2 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers2 +node_a=system.ruby.network.topology.ext_links0.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 +[system.ruby.network.topology.int_links0.node_b] +type=BasicRouter +router_id=2 + [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers2 +node_a=system.ruby.network.topology.ext_links1.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index f1ba4ed84..8ab878859 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:51:44 -gem5 started Jun 4 2012 13:41:27 +gem5 compiled Jul 28 2012 11:27:37 +gem5 started Jul 28 2012 11:35:39 gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 842792d27..8d2f9d8f8 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 52133 # Simulator instruction rate (inst/s) -host_op_rate 52125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1696034 # Simulator tick rate (ticks/s) -host_mem_usage 224184 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 49772 # Simulator instruction rate (inst/s) +host_op_rate 49764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1619227 # Simulator tick rate (ticks/s) +host_mem_usage 231924 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,6 +33,30 @@ system.physmem.bw_write::total 32130518 # Wr system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s) +system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads +system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes +system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads +system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes +system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array +system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv -- cgit v1.2.3