From 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 15 Aug 2012 10:38:05 -0400 Subject: stats: Update stats for syscall emulation Linux kernel changes. --- .../ref/alpha/linux/simple-timing/config.ini | 2 +- .../00.hello/ref/alpha/linux/simple-timing/simout | 8 +- .../ref/alpha/linux/simple-timing/stats.txt | 200 ++++++++++----------- 3 files changed, 105 insertions(+), 105 deletions(-) (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing') diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 4b13e207f..b5ef1f793 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 776a435c2..891277ac4 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:08:22 +gem5 compiled Aug 13 2012 16:51:51 +gem5 started Aug 13 2012 17:17:12 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 34425000 because target called exit() +Exiting @ tick 34409000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index a9d405edb..6a791ec60 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 34425000 # Number of ticks simulated -final_tick 34425000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34409000 # Number of ticks simulated +final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 6722 # Simulator instruction rate (inst/s) -host_op_rate 6722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36133024 # Simulator tick rate (ticks/s) -host_mem_usage 217168 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host -sim_insts 6404 # Number of instructions simulated -sim_ops 6404 # Number of ops (including micro ops) simulated +host_inst_rate 55813 # Simulator instruction rate (inst/s) +host_op_rate 55804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 300451871 # Simulator tick rate (ticks/s) +host_mem_usage 222640 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +sim_insts 6390 # Number of instructions simulated +sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 516833696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312331155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 829164851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516833696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516833696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516833696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312331155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 829164851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_hits 1183 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.read_accesses 1190 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_hits 2048 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.fetch_accesses 6418 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,43 +60,43 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 68850 # number of cpu cycles simulated +system.cpu.numCycles 68818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6404 # Number of instructions committed -system.cpu.committedOps 6404 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls -system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8304 # number of times the integer registers were read -system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 68850 # Number of busy cycles +system.cpu.num_busy_cycles 68818 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 128.155444 # Cycle average of tags in use -system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use +system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 128.155444 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062576 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062576 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits -system.cpu.icache.overall_hits::total 6136 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits +system.cpu.icache.overall_hits::total 6122 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses @@ -109,18 +109,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 15582000 system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency @@ -147,12 +147,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency @@ -161,22 +161,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.856385 # Cycle average of tags in use -system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use +system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.856385 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025356 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025356 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits -system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits +system.cpu.dcache.overall_hits::total 1880 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses @@ -193,22 +193,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 9408000 system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -241,14 +241,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.699061 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.168283 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.530778 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001725 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005637 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -- cgit v1.2.3