From 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Thu, 24 Jan 2013 12:29:00 -0600
Subject: regressions: update stats due to branch predictor changes The actual
 statistical values are being updated for only two tests belonging to sparc
 architecture and inorder cpu: 00.hello and 02.insttest. For others the patch
 updates config.ini and name changes to statistical variables.

---
 .../se/00.hello/ref/alpha/tru64/simple-atomic/config.ini   | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

(limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini')

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 325eb7b2e..81a4de4d4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
-clock=1
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -67,6 +70,9 @@ size=64
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
+[system.cpu.isa]
+type=AlphaISA
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -106,7 +112,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1
+clock=1000
 conf_table_reported=false
 in_addr_map=true
 latency=30000
-- 
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