From fa1fbcf020ee9aacdd4a7a09e81a633e09bad97a Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 1 Sep 2014 16:55:52 -0500 Subject: stats: updates due to recent ruby and x86 changes Also updates many out of date config files. --- .../ref/alpha/tru64/simple-atomic/config.ini | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini') diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index aca9f495e..79159fdc0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000 [system] type=System -children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 init_param=0 kernel= +kernel_addr_check=true load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -36,12 +38,15 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -69,6 +74,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu.tracer @@ -109,7 +115,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -123,9 +129,19 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + [system.membus] type=CoherentBus clk_domain=system.clk_domain -- cgit v1.2.3