From 247e4e9ab41bafcfcbde725bb40e6a7b5628f1de Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 10 Jun 2013 06:46:20 -0500 Subject: stats: updates due to changes to ruby Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated. --- .../simple-timing-ruby-MOESI_hammer/ruby.stats | 781 +-------------------- .../simple-timing-ruby-MOESI_hammer/stats.txt | 84 ++- 2 files changed, 95 insertions(+), 770 deletions(-) (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer') diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 665871e67..38023d4ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:34:50 +Real time: Jun/08/2013 13:28:07 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 Ruby_current_time: 35432 Ruby_start_time: 0 Ruby_cycles: 35432 -mbytes_resident: 52.5391 -mbytes_total: 144.84 -resident_ratio: 0.362793 - -ruby_cycles_executed: [ 35433 ] +mbytes_resident: 53.8984 +mbytes_total: 141.902 +resident_ratio: 0.379883 Busy Controller Counts: L1Cache-0:0 @@ -68,7 +66,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -89,11 +86,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10230 -page_faults: 0 +page_reclaims: 15042 +page_faults: 6 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 936 +block_outputs: 16712 Network Stats ------------- @@ -144,749 +141,3 @@ links_utilized_percent_switch_2: 4.77887 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [422 ] 422 -Ifetch [2591 ] 2591 -Store [298 ] 298 -L2_Replacement [425 ] 425 -L1_to_L2 [502 ] 502 -Trigger_L2_to_L1D [47 ] 47 -Trigger_L2_to_L1I [22 ] 22 -Complete_L2_to_L1 [69 ] 69 -Other_GETX [0 ] 0 -Other_GETS [0 ] 0 -Merged_GETS [0 ] 0 -Other_GETS_No_Mig [0 ] 0 -NC_DMA_GETS [0 ] 0 -Invalidate [0 ] 0 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Data [0 ] 0 -Shared_Data [0 ] 0 -Exclusive_Data [441 ] 441 -Writeback_Ack [425 ] 425 -Writeback_Nack [0 ] 0 -All_acks [0 ] 0 -All_acks_no_sharers [441 ] 441 -Flush_line [0 ] 0 -Block_Ack [0 ] 0 - - - Transitions - -I Load [146 ] 146 -I Ifetch [248 ] 248 -I Store [47 ] 47 -I L2_Replacement [0 ] 0 -I L1_to_L2 [0 ] 0 -I Trigger_L2_to_L1D [0 ] 0 -I Trigger_L2_to_L1I [0 ] 0 -I Other_GETX [0 ] 0 -I Other_GETS [0 ] 0 -I Other_GETS_No_Mig [0 ] 0 -I NC_DMA_GETS [0 ] 0 -I Invalidate [0 ] 0 -I Flush_line [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L2_Replacement [0 ] 0 -S L1_to_L2 [0 ] 0 -S Trigger_L2_to_L1D [0 ] 0 -S Trigger_L2_to_L1I [0 ] 0 -S Other_GETX [0 ] 0 -S Other_GETS [0 ] 0 -S Other_GETS_No_Mig [0 ] 0 -S NC_DMA_GETS [0 ] 0 -S Invalidate [0 ] 0 -S Flush_line [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L2_Replacement [0 ] 0 -O L1_to_L2 [0 ] 0 -O Trigger_L2_to_L1D [0 ] 0 -O Trigger_L2_to_L1I [0 ] 0 -O Other_GETX [0 ] 0 -O Other_GETS [0 ] 0 -O Merged_GETS [0 ] 0 -O Other_GETS_No_Mig [0 ] 0 -O NC_DMA_GETS [0 ] 0 -O Invalidate [0 ] 0 -O Flush_line [0 ] 0 - -M Load [109 ] 109 -M Ifetch [2315 ] 2315 -M Store [35 ] 35 -M L2_Replacement [344 ] 344 -M L1_to_L2 [397 ] 397 -M Trigger_L2_to_L1D [23 ] 23 -M Trigger_L2_to_L1I [22 ] 22 -M Other_GETX [0 ] 0 -M Other_GETS [0 ] 0 -M Merged_GETS [0 ] 0 -M Other_GETS_No_Mig [0 ] 0 -M NC_DMA_GETS [0 ] 0 -M Invalidate [0 ] 0 -M Flush_line [0 ] 0 - -MM Load [124 ] 124 -MM Ifetch [0 ] 0 -MM Store [201 ] 201 -MM L2_Replacement [81 ] 81 -MM L1_to_L2 [105 ] 105 -MM Trigger_L2_to_L1D [24 ] 24 -MM Trigger_L2_to_L1I [0 ] 0 -MM Other_GETX [0 ] 0 -MM Other_GETS [0 ] 0 -MM Merged_GETS [0 ] 0 -MM Other_GETS_No_Mig [0 ] 0 -MM NC_DMA_GETS [0 ] 0 -MM Invalidate [0 ] 0 -MM Flush_line [0 ] 0 - -IR Load [0 ] 0 -IR Ifetch [0 ] 0 -IR Store [0 ] 0 -IR L1_to_L2 [0 ] 0 -IR Flush_line [0 ] 0 - -SR Load [0 ] 0 -SR Ifetch [0 ] 0 -SR Store [0 ] 0 -SR L1_to_L2 [0 ] 0 -SR Flush_line [0 ] 0 - -OR Load [0 ] 0 -OR Ifetch [0 ] 0 -OR Store [0 ] 0 -OR L1_to_L2 [0 ] 0 -OR Flush_line [0 ] 0 - -MR Load [22 ] 22 -MR Ifetch [22 ] 22 -MR Store [1 ] 1 -MR L1_to_L2 [0 ] 0 -MR Flush_line [0 ] 0 - -MMR Load [14 ] 14 -MMR Ifetch [0 ] 0 -MMR Store [10 ] 10 -MMR L1_to_L2 [0 ] 0 -MMR Flush_line [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L1_to_L2 [0 ] 0 -IM Other_GETX [0 ] 0 -IM Other_GETS [0 ] 0 -IM Other_GETS_No_Mig [0 ] 0 -IM NC_DMA_GETS [0 ] 0 -IM Invalidate [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [47 ] 47 -IM Flush_line [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L2_Replacement [0 ] 0 -SM L1_to_L2 [0 ] 0 -SM Other_GETX [0 ] 0 -SM Other_GETS [0 ] 0 -SM Other_GETS_No_Mig [0 ] 0 -SM NC_DMA_GETS [0 ] 0 -SM Invalidate [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 -SM Flush_line [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L2_Replacement [0 ] 0 -OM L1_to_L2 [0 ] 0 -OM Other_GETX [0 ] 0 -OM Other_GETS [0 ] 0 -OM Merged_GETS [0 ] 0 -OM Other_GETS_No_Mig [0 ] 0 -OM NC_DMA_GETS [0 ] 0 -OM Invalidate [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [0 ] 0 -OM All_acks_no_sharers [0 ] 0 -OM Flush_line [0 ] 0 - -ISM Load [0 ] 0 -ISM Ifetch [0 ] 0 -ISM Store [0 ] 0 -ISM L2_Replacement [0 ] 0 -ISM L1_to_L2 [0 ] 0 -ISM Ack [0 ] 0 -ISM All_acks_no_sharers [0 ] 0 -ISM Flush_line [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [0 ] 0 -M_W Ack [0 ] 0 -M_W All_acks_no_sharers [394 ] 394 -M_W Flush_line [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [0 ] 0 -MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [0 ] 0 -MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [47 ] 47 -MM_W Flush_line [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L1_to_L2 [0 ] 0 -IS Other_GETX [0 ] 0 -IS Other_GETS [0 ] 0 -IS Other_GETS_No_Mig [0 ] 0 -IS NC_DMA_GETS [0 ] 0 -IS Invalidate [0 ] 0 -IS Ack [0 ] 0 -IS Shared_Ack [0 ] 0 -IS Data [0 ] 0 -IS Shared_Data [0 ] 0 -IS Exclusive_Data [394 ] 394 -IS Flush_line [0 ] 0 - -SS Load [0 ] 0 -SS Ifetch [0 ] 0 -SS Store [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L1_to_L2 [0 ] 0 -SS Ack [0 ] 0 -SS Shared_Ack [0 ] 0 -SS All_acks [0 ] 0 -SS All_acks_no_sharers [0 ] 0 -SS Flush_line [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L2_Replacement [0 ] 0 -OI L1_to_L2 [0 ] 0 -OI Other_GETX [0 ] 0 -OI Other_GETS [0 ] 0 -OI Merged_GETS [0 ] 0 -OI Other_GETS_No_Mig [0 ] 0 -OI NC_DMA_GETS [0 ] 0 -OI Invalidate [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Flush_line [0 ] 0 - -MI Load [7 ] 7 -MI Ifetch [6 ] 6 -MI Store [4 ] 4 -MI L2_Replacement [0 ] 0 -MI L1_to_L2 [0 ] 0 -MI Other_GETX [0 ] 0 -MI Other_GETS [0 ] 0 -MI Merged_GETS [0 ] 0 -MI Other_GETS_No_Mig [0 ] 0 -MI NC_DMA_GETS [0 ] 0 -MI Invalidate [0 ] 0 -MI Writeback_Ack [425 ] 425 -MI Flush_line [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L2_Replacement [0 ] 0 -II L1_to_L2 [0 ] 0 -II Other_GETX [0 ] 0 -II Other_GETS [0 ] 0 -II Other_GETS_No_Mig [0 ] 0 -II NC_DMA_GETS [0 ] 0 -II Invalidate [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Nack [0 ] 0 -II Flush_line [0 ] 0 - -IT Load [0 ] 0 -IT Ifetch [0 ] 0 -IT Store [0 ] 0 -IT L2_Replacement [0 ] 0 -IT L1_to_L2 [0 ] 0 -IT Complete_L2_to_L1 [0 ] 0 - -ST Load [0 ] 0 -ST Ifetch [0 ] 0 -ST Store [0 ] 0 -ST L2_Replacement [0 ] 0 -ST L1_to_L2 [0 ] 0 -ST Complete_L2_to_L1 [0 ] 0 - -OT Load [0 ] 0 -OT Ifetch [0 ] 0 -OT Store [0 ] 0 -OT L2_Replacement [0 ] 0 -OT L1_to_L2 [0 ] 0 -OT Complete_L2_to_L1 [0 ] 0 - -MT Load [0 ] 0 -MT Ifetch [0 ] 0 -MT Store [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L1_to_L2 [0 ] 0 -MT Complete_L2_to_L1 [45 ] 45 - -MMT Load [0 ] 0 -MMT Ifetch [0 ] 0 -MMT Store [0 ] 0 -MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [0 ] 0 -MMT Complete_L2_to_L1 [24 ] 24 - -MI_F Load [0 ] 0 -MI_F Ifetch [0 ] 0 -MI_F Store [0 ] 0 -MI_F L1_to_L2 [0 ] 0 -MI_F Writeback_Ack [0 ] 0 -MI_F Flush_line [0 ] 0 - -MM_F Load [0 ] 0 -MM_F Ifetch [0 ] 0 -MM_F Store [0 ] 0 -MM_F L1_to_L2 [0 ] 0 -MM_F Other_GETX [0 ] 0 -MM_F Other_GETS [0 ] 0 -MM_F Merged_GETS [0 ] 0 -MM_F Other_GETS_No_Mig [0 ] 0 -MM_F NC_DMA_GETS [0 ] 0 -MM_F Invalidate [0 ] 0 -MM_F Ack [0 ] 0 -MM_F All_acks [0 ] 0 -MM_F All_acks_no_sharers [0 ] 0 -MM_F Flush_line [0 ] 0 -MM_F Block_Ack [0 ] 0 - -IM_F Load [0 ] 0 -IM_F Ifetch [0 ] 0 -IM_F Store [0 ] 0 -IM_F L2_Replacement [0 ] 0 -IM_F L1_to_L2 [0 ] 0 -IM_F Other_GETX [0 ] 0 -IM_F Other_GETS [0 ] 0 -IM_F Other_GETS_No_Mig [0 ] 0 -IM_F NC_DMA_GETS [0 ] 0 -IM_F Invalidate [0 ] 0 -IM_F Ack [0 ] 0 -IM_F Data [0 ] 0 -IM_F Exclusive_Data [0 ] 0 -IM_F Flush_line [0 ] 0 - -ISM_F Load [0 ] 0 -ISM_F Ifetch [0 ] 0 -ISM_F Store [0 ] 0 -ISM_F L2_Replacement [0 ] 0 -ISM_F L1_to_L2 [0 ] 0 -ISM_F Ack [0 ] 0 -ISM_F All_acks_no_sharers [0 ] 0 -ISM_F Flush_line [0 ] 0 - -SM_F Load [0 ] 0 -SM_F Ifetch [0 ] 0 -SM_F Store [0 ] 0 -SM_F L2_Replacement [0 ] 0 -SM_F L1_to_L2 [0 ] 0 -SM_F Other_GETX [0 ] 0 -SM_F Other_GETS [0 ] 0 -SM_F Other_GETS_No_Mig [0 ] 0 -SM_F NC_DMA_GETS [0 ] 0 -SM_F Invalidate [0 ] 0 -SM_F Ack [0 ] 0 -SM_F Data [0 ] 0 -SM_F Exclusive_Data [0 ] 0 -SM_F Flush_line [0 ] 0 - -OM_F Load [0 ] 0 -OM_F Ifetch [0 ] 0 -OM_F Store [0 ] 0 -OM_F L2_Replacement [0 ] 0 -OM_F L1_to_L2 [0 ] 0 -OM_F Other_GETX [0 ] 0 -OM_F Other_GETS [0 ] 0 -OM_F Merged_GETS [0 ] 0 -OM_F Other_GETS_No_Mig [0 ] 0 -OM_F NC_DMA_GETS [0 ] 0 -OM_F Invalidate [0 ] 0 -OM_F Ack [0 ] 0 -OM_F All_acks [0 ] 0 -OM_F All_acks_no_sharers [0 ] 0 -OM_F Flush_line [0 ] 0 - -MM_WF Load [0 ] 0 -MM_WF Ifetch [0 ] 0 -MM_WF Store [0 ] 0 -MM_WF L2_Replacement [0 ] 0 -MM_WF L1_to_L2 [0 ] 0 -MM_WF Ack [0 ] 0 -MM_WF All_acks_no_sharers [0 ] 0 -MM_WF Flush_line [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 522 - memory_reads: 441 - memory_writes: 81 - memory_refreshes: 246 - memory_total_request_delays: 39 - memory_delays_per_request: 0.0747126 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 39 - memory_stalls_for_bank_busy: 15 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 5 - memory_stalls_for_bus: 15 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 - - --- Directory --- - - Event Counts - -GETX [51 ] 51 -GETS [410 ] 410 -PUT [425 ] 425 -Unblock [0 ] 0 -UnblockS [0 ] 0 -UnblockM [440 ] 440 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [344 ] 344 -Writeback_Exclusive_Dirty [81 ] 81 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [441 ] 441 -Memory_Ack [81 ] 81 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [0 ] 0 -GETF [0 ] 0 -PUTF [0 ] 0 - - - Transitions - -NX GETX [0 ] 0 -NX GETS [0 ] 0 -NX PUT [0 ] 0 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [0 ] 0 -NO GETS [0 ] 0 -NO PUT [425 ] 425 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [47 ] 47 -E GETS [394 ] 394 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [0 ] 0 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [0 ] 0 -NO_B GETS [0 ] 0 -NO_B PUT [0 ] 0 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [440 ] 440 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [0 ] 0 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [0 ] 0 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [0 ] 0 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [0 ] 0 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [0 ] 0 -O_B GETS [0 ] 0 -O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [0 ] 0 -NO_B_W GETS [0 ] 0 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [441 ] 441 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [4 ] 4 -WB GETS [14 ] 14 -WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [344 ] 344 -WB Writeback_Exclusive_Dirty [81 ] 81 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [0 ] 0 -WB_E_W GETS [2 ] 2 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [81 ] 81 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [0 ] 0 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index d3fbb9bcf..f1ed0212f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17259 # Simulator instruction rate (inst/s) -host_op_rate 17257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237238 # Simulator tick rate (ticks/s) -host_mem_usage 151196 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 14099 # Simulator instruction rate (inst/s) +host_op_rate 14097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193809 # Simulator tick rate (ticks/s) +host_mem_usage 145312 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 522 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 441 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 81 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 246 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 39 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 39 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.074713 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 15 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 15 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 5 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.45% 3.45% | 10 1.92% 5.36% | 0 0.00% 5.36% | 36 6.90% 12.26% | 20 3.83% 16.09% | 19 3.64% 19.73% | 31 5.94% 25.67% | 22 4.21% 29.89% | 5 0.96% 30.84% | 4 0.77% 31.61% | 7 1.34% 32.95% | 4 0.77% 33.72% | 22 4.21% 37.93% | 41 7.85% 45.79% | 22 4.21% 50.00% | 3 0.57% 50.57% | 4 0.77% 51.34% | 6 1.15% 52.49% | 7 1.34% 53.83% | 13 2.49% 56.32% | 10 1.92% 58.24% | 18 3.45% 61.69% | 14 2.68% 64.37% | 41 7.85% 72.22% | 16 3.07% 75.29% | 5 0.96% 76.25% | 5 0.96% 77.20% | 12 2.30% 79.50% | 13 2.49% 81.99% | 18 3.45% 85.44% | 14 2.68% 88.12% | 62 11.88% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 522 # Number of accesses per bank + system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -78,5 +92,65 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 35432 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 422 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2591 0.00% 0.00% +system.ruby.l1_cntrl0.Store 298 0.00% 0.00% +system.ruby.l1_cntrl0.L2_Replacement 425 0.00% 0.00% +system.ruby.l1_cntrl0.L1_to_L2 502 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1D 47 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1I 22 0.00% 0.00% +system.ruby.l1_cntrl0.Complete_L2_to_L1 69 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 441 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 425 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks_no_sharers 441 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 146 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 248 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 47 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 109 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 2315 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 35 0.00% 0.00% +system.ruby.l1_cntrl0.M.L2_Replacement 344 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_to_L2 397 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 23 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 22 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 124 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 201 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L2_Replacement 81 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_to_L2 105 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 24 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Load 22 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Ifetch 22 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Store 1 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Load 14 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Store 10 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 47 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 394 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 47 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 394 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Load 7 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Ifetch 6 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Store 4 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 425 0.00% 0.00% +system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 45 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 24 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 51 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 410 0.00% 0.00% +system.ruby.dir_cntrl0.PUT 425 0.00% 0.00% +system.ruby.dir_cntrl0.UnblockM 440 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 441 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 81 0.00% 0.00% +system.ruby.dir_cntrl0.NO.PUT 425 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETX 47 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETS 394 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETX 4 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETS 14 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- -- cgit v1.2.3