From 9f15510c2c0c346faf107a47486cc06d4921e7c9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 7 Jan 2013 13:05:54 -0500 Subject: stats: update stats for previous changes. --- .../se/00.hello/ref/arm/linux/o3-timing/config.ini | 42 +- .../se/00.hello/ref/arm/linux/o3-timing/simout | 8 +- .../se/00.hello/ref/arm/linux/o3-timing/stats.txt | 551 ++++++++++----------- 3 files changed, 302 insertions(+), 299 deletions(-) (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing') diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 675d12028..38f0d4bce 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 116fbeb57..b1b5545bf 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 18:52:17 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:26:30 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13371000 because target called exit() +Exiting @ tick 13372000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 11fc8e27b..5c779e5dd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13371000 # Number of ticks simulated -final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13372000 # Number of ticks simulated +final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36978 # Simulator instruction rate (inst/s) -host_op_rate 46127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107546339 # Simulator tick rate (ticks/s) -host_mem_usage 272728 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 20879 # Simulator instruction rate (inst/s) +host_op_rate 26045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60729168 # Simulator tick rate (ticks/s) +host_mem_usage 230484 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13312500 # Total gap between requests +system.physmem.totGap 13314500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.79 # Data bus utilization in percentage @@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33788.07 # Average gap between requests +system.physmem.avgGap 33793.15 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,7 +228,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26743 # number of cpu cycles simulated +system.cpu.numCycles 26745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2505 # Number of BP lookups @@ -239,22 +239,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) @@ -265,11 +264,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing @@ -282,17 +281,17 @@ system.cpu.rename.IdleCycles 7146 # Nu system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 44 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer @@ -307,13 +306,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle @@ -323,7 +322,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -393,10 +392,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.rate 0.336063 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -419,7 +418,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions @@ -437,13 +436,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1446 # Number of branches executed system.cpu.iew.exec_stores 1164 # Number of stores executed -system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.exec_rate 0.320209 # Inst execution rate system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8109 # cumulative count of insts written-back system.cpu.iew.wb_producers 3899 # num instructions producing a value system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit @@ -481,64 +480,64 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 22988 # The number of ROB reads system.cpu.rob.rob_writes 23599 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39369 # number of integer regfile reads system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits @@ -609,16 +742,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -641,16 +774,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -677,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3