From f71fa1715793c764ffa95411e87b73179a7c7b3f Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 30 Apr 2015 14:17:43 -0500 Subject: stats: arm: updates --- .../00.hello/ref/arm/linux/simple-timing/stats.txt | 132 ++++++++++----------- 1 file changed, 66 insertions(+), 66 deletions(-) (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing') diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 8573f117d..578791a49 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815500 # Number of ticks simulated -final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25816500 # Number of ticks simulated +final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263675 # Simulator instruction rate (inst/s) -host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1488783160 # Simulator tick rate (ticks/s) -host_mem_usage 306760 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 4565 # Number of instructions simulated -sim_ops 5329 # Number of ops (including micro ops) simulated +host_inst_rate 77759 # Simulator instruction rate (inst/s) +host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 439383785 # Simulator tick rate (ticks/s) +host_mem_usage 301384 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4566 # Number of instructions simulated +sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51631 # number of cpu cycles simulated +system.cpu.numCycles 51633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4565 # Number of instructions committed -system.cpu.committedOps 5329 # Number of ops (including micro ops) committed +system.cpu.committedInsts 4566 # Number of instructions committed +system.cpu.committedOps 5330 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured @@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 7573 # nu system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read +system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1007 # Number of branches fetched +system.cpu.Branches 1008 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction @@ -198,22 +198,22 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -320,26 +320,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9451 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits -system.cpu.icache.overall_hits::total 4364 # number of overall hits +system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9453 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits +system.cpu.icache.overall_hits::total 4365 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses @@ -352,18 +352,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12588500 system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency @@ -390,12 +390,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency @@ -404,13 +404,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy -- cgit v1.2.3