From c49e739352b6d6bd665c78c560602d0cff1e6a1a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 5 Jun 2012 01:23:16 -0400 Subject: all: Update stats for memory per master and total fix. --- .../ref/mips/linux/simple-timing/config.ini | 6 +- .../00.hello/ref/mips/linux/simple-timing/simout | 6 +- .../ref/mips/linux/simple-timing/stats.txt | 79 ++++++++++++++++++---- 3 files changed, 70 insertions(+), 21 deletions(-) (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing') diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index c6b1fd816..f7cc4efef 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 0276ca4b7..ac53df969 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:48 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 6c79a4c95..8f49928a9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273601 # Simulator instruction rate (inst/s) -host_op_rate 273420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504754975 # Simulator tick rate (ticks/s) -host_mem_usage 214572 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 540307 # Simulator instruction rate (inst/s) +host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2965678153 # Simulator tick rate (ticks/s) +host_mem_usage 215020 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 439 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 28096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -95,11 +102,17 @@ system.cpu.icache.demand_accesses::total 5829 # nu system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -121,11 +134,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15975000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use @@ -169,13 +188,21 @@ system.cpu.dcache.demand_accesses::total 2089 # nu system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -201,13 +228,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use @@ -261,18 +296,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,18 +348,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3