From f3585c841e964c98911784a187fc4f081a02a0a6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:33 -0600 Subject: stats: update stats for cache occupancy and clock domain changes --- .../ref/mips/linux/simple-timing/config.ini | 31 +++++++++++++++++++++- .../00.hello/ref/mips/linux/simple-timing/simerr | 1 - .../00.hello/ref/mips/linux/simple-timing/simout | 8 +++--- .../ref/mips/linux/simple-timing/stats.txt | 31 ++++++++++++++++++---- 4 files changed, 59 insertions(+), 12 deletions(-) (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing') diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index aa6f1a156..943508ee9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,19 +140,25 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -149,6 +167,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -157,6 +176,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -171,12 +191,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -186,6 +209,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -195,7 +219,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -209,11 +234,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -226,6 +253,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -235,5 +263,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index f65ffe2d1..fe019aadb 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:20 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:28:24 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d3256ea4d..bed740225 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304637 # Simulator instruction rate (inst/s) -host_op_rate 304230 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1653175117 # Simulator tick rate (ticks/s) -host_mem_usage 224940 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 65946 # Simulator instruction rate (inst/s) +host_op_rate 65935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 358688094 # Simulator tick rate (ticks/s) +host_mem_usage 230484 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 28096 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 439000 # La system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -92,6 +95,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.141602 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11935 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11935 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -172,6 +181,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011841 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3967 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3967 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -295,6 +310,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4314 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4314 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits -- cgit v1.2.3