From 85997e66a08b71d701e5b41462d1cfd42660b0c7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 6 Jun 2016 17:16:44 +0100 Subject: stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee --- .../se/00.hello/ref/mips/linux/o3-timing/stats.txt | 19 +++++++++++++++---- .../00.hello/ref/mips/linux/simple-atomic/stats.txt | 12 ++++++++---- .../ref/mips/linux/simple-timing-ruby/stats.txt | 20 ++++++++++++++++---- .../00.hello/ref/mips/linux/simple-timing/stats.txt | 19 +++++++++++++++---- 4 files changed, 54 insertions(+), 16 deletions(-) (limited to 'tests/quick/se/00.hello/ref/mips') diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 0194e3c6f..1d63b6535 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000023 # Nu sim_ticks 22532000 # Number of ticks simulated final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96442 # Simulator instruction rate (inst/s) -host_op_rate 96403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 434426491 # Simulator tick rate (ticks/s) -host_mem_usage 247240 # Number of bytes of host memory used +host_inst_rate 107418 # Simulator instruction rate (inst/s) +host_op_rate 107396 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 483974405 # Simulator tick rate (ticks/s) +host_mem_usage 292720 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 30016 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2183 # Number of BP lookups system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect @@ -282,6 +284,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 45065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -571,6 +574,7 @@ system.cpu.int_regfile_writes 5151 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 160 # number of misc regfile reads +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. @@ -586,6 +590,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits @@ -680,6 +685,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. @@ -695,6 +701,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 172 system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses system.cpu.icache.tags.data_accesses 4426 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits @@ -769,6 +776,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. @@ -786,6 +794,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -916,6 +925,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -946,6 +956,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 498000 # La system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index df8a010ee..873eb6862 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 876414 # Simulator instruction rate (inst/s) -host_op_rate 873362 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 435104956 # Simulator tick rate (ticks/s) -host_mem_usage 235716 # Number of bytes of host memory used +host_inst_rate 743339 # Simulator instruction rate (inst/s) +host_op_rate 742439 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370817863 # Simulator tick rate (ticks/s) +host_mem_usage 279644 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.physmem.bytes_read::total 26869 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1276723985 # Wr system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -55,6 +57,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2820500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5642 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -113,6 +116,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6777 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 194e91ae7..5b0097850 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000100 # Nu sim_ticks 100232 # Number of ticks simulated final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 97717 # Simulator instruction rate (inst/s) -host_op_rate 97699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1735645 # Simulator tick rate (ticks/s) -host_mem_usage 410048 # Number of bytes of host memory used +host_inst_rate 93908 # Simulator instruction rate (inst/s) +host_op_rate 93894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1668107 # Simulator tick rate (ticks/s) +host_mem_usage 455812 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory @@ -267,6 +268,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3120 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -287,6 +289,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states system.cpu.numCycles 100232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -346,6 +349,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2940 # delay histogram for all message @@ -382,10 +386,14 @@ system.ruby.miss_latency_hist_seqr::stdev 35.865583 system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1472 system.ruby.Directory.incomplete_times_seqr 1471 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.332987 system.ruby.network.routers0.msg_count.Control::2 1472 system.ruby.network.routers0.msg_count.Data::2 1468 @@ -395,6 +403,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776 system.ruby.network.routers0.msg_bytes.Data::2 105696 system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.332987 system.ruby.network.routers1.msg_count.Control::2 1472 system.ruby.network.routers1.msg_count.Data::2 1468 @@ -404,6 +413,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776 system.ruby.network.routers1.msg_bytes.Data::2 105696 system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.332987 system.ruby.network.routers2.msg_count.Control::2 1472 system.ruby.network.routers2.msg_count.Data::2 1468 @@ -413,6 +423,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11776 system.ruby.network.routers2.msg_bytes.Data::2 105696 system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 4416 system.ruby.network.msg_count.Data 4404 system.ruby.network.msg_count.Response_Data 4416 @@ -421,6 +432,7 @@ system.ruby.network.msg_byte.Control 35328 system.ruby.network.msg_byte.Data 317088 system.ruby.network.msg_byte.Response_Data 317952 system.ruby.network.msg_byte.Writeback_Control 35232 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.340969 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 0e87b1f2c..5a06a8f5e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000034 # Nu sim_ticks 33932500 # Number of ticks simulated final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 431758 # Simulator instruction rate (inst/s) -host_op_rate 430982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2588300068 # Simulator tick rate (ticks/s) -host_mem_usage 244424 # Number of bytes of host memory used +host_inst_rate 497160 # Simulator instruction rate (inst/s) +host_op_rate 496749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985875640 # Simulator tick rate (ticks/s) +host_mem_usage 289632 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.physmem.bytes_read::total 27520 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 552626538 # In system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,6 +51,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 67865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -107,6 +110,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. @@ -122,6 +126,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -208,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. @@ -223,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 177 system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses system.cpu.icache.tags.data_accesses 11581 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits @@ -291,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. @@ -308,6 +316,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits @@ -438,6 +447,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -468,6 +478,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution -- cgit v1.2.3