From d52adc4eb68c2733f9af4ac68834583c0a555f9d Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:12:21 -0400 Subject: Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. --- .../00.hello/ref/mips/linux/inorder-timing/stats.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'tests/quick/se/00.hello/ref/mips') diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1d71c4fe2..04aaa0ff5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20184000 # Number of ticks simulated final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50290 # Simulator instruction rate (inst/s) -host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174536927 # Simulator tick rate (ticks/s) -host_mem_usage 219492 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 91753 # Simulator instruction rate (inst/s) +host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318298211 # Simulator tick rate (ticks/s) +host_mem_usage 212944 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -160,11 +160,11 @@ system.cpu.icache.demand_avg_miss_latency::total 56098.837209 system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -256,11 +256,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -- cgit v1.2.3