From 5b08e211ab35fd6d936dafda45014c78b5e68300 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Sun, 22 Jun 2014 14:33:09 -0700
Subject: stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
---
 .../00.hello/ref/power/linux/o3-timing/config.ini  | 28 ++++++++++++++--------
 1 file changed, 18 insertions(+), 10 deletions(-)

(limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini')

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 31323532b..6b18ed844 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -18,6 +18,7 @@ eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -116,6 +117,7 @@ smtLSQThreshold=100
 smtNumFetchingThreads=1
 smtROBPolicy=Partitioned
 smtROBThreshold=100
+socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
@@ -599,7 +601,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/test-progs/hello/bin/power/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -628,9 +630,9 @@ master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -641,27 +643,33 @@ device_rowbuffer_size=1024
 devices_per_rank=8
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCK=1250
 tCL=13750
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[0]
 
 [system.voltage_domain]
-- 
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