From fda338f8d3ba6f6cb271e2c10cb880ff064edb61 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 9 Jul 2012 12:35:41 -0400 Subject: Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes. --- .../00.hello/ref/power/linux/o3-timing/config.ini | 4 +- .../se/00.hello/ref/power/linux/o3-timing/simout | 6 +- .../00.hello/ref/power/linux/o3-timing/stats.txt | 952 ++++++++++----------- 3 files changed, 481 insertions(+), 481 deletions(-) (limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing') diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 928f0469f..fe01ee3c1 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -480,7 +480,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -512,7 +512,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 584102e9c..4c16f50ba 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:53:15 +gem5 compiled Jul 2 2012 08:50:36 +gem5 started Jul 2 2012 11:29:39 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11179000 because target called exit() +Exiting @ tick 11812000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index f8f7991bd..0b8cd16ea 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11179000 # Number of ticks simulated -final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11812000 # Number of ticks simulated +final_tick 11812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61972 # Simulator instruction rate (inst/s) -host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119400246 # Simulator tick rate (ticks/s) -host_mem_usage 216052 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 59914 # Simulator instruction rate (inst/s) +host_op_rate 59903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121974515 # Simulator tick rate (ticks/s) +host_mem_usage 216016 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1907213004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541821876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2449034880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1907213004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541821876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2449034880 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22359 # number of cpu cycles simulated +system.cpu.numCycles 23625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2487 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits +system.cpu.BPredUnit.lookups 2490 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2041 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2061 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 629 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2490 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 791 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2421 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1432 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 932 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1897 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.238075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.668941 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9340 79.42% 79.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 172 1.46% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.42% 82.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 146 1.24% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 197 1.68% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 155 1.32% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 255 2.17% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.92% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 10.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.105397 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.616339 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1069 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 64 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 807 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 361 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2086 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 12930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 452 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 807 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7781 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2100 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 249 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12283 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10602 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 20025 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19970 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 5595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11001 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523023 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8303 70.60% 70.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1127 9.58% 80.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 767 6.52% 86.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 536 4.56% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.06% 95.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 324 2.75% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 139 1.18% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.42% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 38 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11761 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.87% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78 44.83% 47.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5709 61.51% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1861 20.05% 81.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1710 18.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9264 # Type of FU issued -system.cpu.iq.rate 0.414330 # Inst issue rate -system.cpu.iq.fu_busy_cnt 179 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9282 # Type of FU issued +system.cpu.iq.rate 0.392889 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018746 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30604 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16005 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8374 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9422 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1136 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 807 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11066 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8779 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_refs 3289 # number of memory reference insts executed system.cpu.iew.exec_branches 1382 # Number of branches executed -system.cpu.iew.exec_stores 1566 # Number of stores executed -system.cpu.iew.exec_rate 0.391654 # Inst execution rate -system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4334 # num instructions producing a value -system.cpu.iew.wb_consumers 6981 # num instructions consuming a value +system.cpu.iew.exec_stores 1573 # Number of stores executed +system.cpu.iew.exec_rate 0.371598 # Inst execution rate +system.cpu.iew.wb_sent 8575 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8401 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4358 # num instructions producing a value +system.cpu.iew.wb_consumers 6997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.355598 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5275 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 301 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308345 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8509 77.68% 77.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1052 9.60% 87.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 645 5.89% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.40% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.67% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.95% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.58% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.37% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21079 # The number of ROB reads -system.cpu.rob.rob_writes 22698 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21935 # The number of ROB reads +system.cpu.rob.rob_writes 22958 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13891 # number of integer regfile reads -system.cpu.int_regfile_writes 7248 # number of integer regfile writes +system.cpu.cpi 4.073276 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.073276 # CPI: Total CPI of All Threads +system.cpu.ipc 0.245503 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.245503 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13900 # number of integer regfile reads +system.cpu.int_regfile_writes 7266 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use -system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.776641 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.095238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits -system.cpu.icache.overall_hits::total 1455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses -system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.776641 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16386000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16386000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16386000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16386000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1897 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229309 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229309 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229309 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229309 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37668.965517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37668.965517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,70 +365,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 355 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188129 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188129 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188129 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 78 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 78 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13154500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13154500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use -system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.298936 # Cycle average of tags in use +system.cpu.dcache.total_refs 2197 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 100 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.970000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits -system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses -system.cpu.dcache.overall_misses::total 402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 63.298936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2197 # number of overall hits +system.cpu.dcache.overall_hits::total 2197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 421 # number of overall misses +system.cpu.dcache.overall_misses::total 421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12822500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12822500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16555000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16555000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -437,22 +437,22 @@ system.cpu.dcache.demand_accesses::cpu.data 2618 # system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160810 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160810 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160810 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160810 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39323.040380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3