From 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 2 Nov 2012 11:50:06 -0500
Subject: update stats for preceeding changes

---
 .../se/00.hello/ref/x86/linux/o3-timing/config.ini | 71 ++++++++++++++--------
 1 file changed, 44 insertions(+), 27 deletions(-)

(limited to 'tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini')

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 98b722b0c..85178b3d5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
-clock=1
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -78,6 +78,7 @@ iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -129,18 +130,18 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=1000
+response_latency=2
 size=262144
 subblock_size=0
 system=system
@@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -431,18 +432,18 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=1000
+response_latency=2
 size=131072
 subblock_size=0
 system=system
@@ -455,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=1
+clock=500
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -464,6 +465,9 @@ int_master=system.membus.slave[2]
 int_slave=system.membus.master[2]
 pio=system.membus.master[1]
 
+[system.cpu.isa]
+type=X86ISA
+
 [system.cpu.itb]
 type=X86TLB
 children=walker
@@ -472,31 +476,31 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=1000
+hit_latency=20
 is_top_level=false
 max_miss_count=0
-mshrs=10
+mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=1000
+response_latency=20
 size=2097152
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -506,10 +510,10 @@ mem_side=system.membus.slave[1]
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=1000
+clock=500
 header_cycles=1
 use_default_range=false
-width=8
+width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -524,7 +528,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -546,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
 conf_table_reported=false
 in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
 null=false
+page_policy=open
 range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
 zero=false
 port=system.membus.master[0]
 
-- 
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