From 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Thu, 24 Jan 2013 12:29:00 -0600
Subject: regressions: update stats due to branch predictor changes The actual
 statistical values are being updated for only two tests belonging to sparc
 architecture and inorder cpu: 00.hello and 02.insttest. For others the patch
 updates config.ini and name changes to statistical variables.

---
 .../ref/x86/linux/simple-timing/config.ini         | 27 ++++++++--------------
 1 file changed, 9 insertions(+), 18 deletions(-)

(limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini')

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index f8e4933ef..46354ed27 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=262144
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=131072
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
 int_slave=system.membus.master[2]
 pio=system.membus.master[1]
 
+[system.cpu.isa]
+type=X86ISA
+
 [system.cpu.itb]
 type=X86TLB
 children=walker
@@ -152,21 +148,16 @@ assoc=8
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=20
 is_top_level=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=20
 size=2097152
-subblock_size=0
 system=system
 tgts_per_mshr=12
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
-- 
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