From 53f697a6166a6fe2787882f3448e73a8ebb849aa Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 24 Feb 2014 20:50:06 -0600 Subject: stats: updates due to c0db268f811b --- .../00.hello/ref/x86/linux/simple-timing-ruby/config.ini | 16 ++++++++++++++-- .../00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | 12 +++++++----- 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'tests/quick/se/00.hello/ref/x86/linux') diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index b20ae7d88..b7b166102 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -166,6 +166,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network @@ -286,6 +296,9 @@ using_network_tester=false using_ruby_tester=false version=0 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.ruby.memctrl_clk_domain] @@ -380,7 +393,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 8fc84aed4..36b845624 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29778 # Simulator instruction rate (inst/s) -host_op_rate 53940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 673676 # Simulator tick rate (ticks/s) -host_mem_usage 193492 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 27489 # Simulator instruction rate (inst/s) +host_op_rate 49793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 621883 # Simulator tick rate (ticks/s) +host_mem_usage 193512 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -- cgit v1.2.3