From 040fa23d01109c68d194d2517df777844e4e2f13 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 19 Jul 2014 19:04:58 -0700 Subject: stats: update for syscall DPRINTF change Only printing one rather than two args for the ignored syscall warning means the count of register accesses has changed on a few runs. Oddly only Alpha Tru64 seems to have any ignored syscalls in the regression tests. --- .../quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini | 14 +++++++++++++- tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr | 2 +- tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout | 6 ++---- .../quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 12 ++++++------ 4 files changed, 22 insertions(+), 12 deletions(-) (limited to 'tests/quick/se/00.hello') diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 5d14be284..a04bfcdcc 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 [system] type=System -children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -37,7 +37,9 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu] @@ -615,9 +617,19 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + [system.membus] type=CoherentBus clk_domain=system.clk_domain diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr index 62976a831..025ac53d5 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,3 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 757b668d6..f39993dfb 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 10:38:16 +gem5 compiled Jul 19 2014 12:27:06 +gem5 started Jul 19 2014 12:27:28 gem5 executing on phenom command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 827c29bcd..477ffe800 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11975500 # Number of ticks simulated final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28986 # Simulator instruction rate (inst/s) -host_op_rate 28981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145369893 # Simulator tick rate (ticks/s) -host_mem_usage 220536 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 10130 # Simulator instruction rate (inst/s) +host_op_rate 10129 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50814142 # Simulator tick rate (ticks/s) +host_mem_usage 221260 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -573,7 +573,7 @@ system.cpu.cpi 10.034353 # CP system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4676 # number of integer regfile reads +system.cpu.int_regfile_reads 4675 # number of integer regfile reads system.cpu.int_regfile_writes 2829 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads -- cgit v1.2.3