From 2823982a3cbd60a1b21db1a73b78440468df158a Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 26 Nov 2013 17:05:25 -0600 Subject: stats: updates due to changes to ticksToCycles() --- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 75 +++++++++++++- .../00.hello/ref/alpha/linux/o3-timing/stats.txt | 46 ++++----- .../00.hello/ref/mips/linux/o3-timing/config.ini | 75 +++++++++++++- .../se/00.hello/ref/mips/linux/o3-timing/stats.txt | 112 ++++++++++----------- 4 files changed, 225 insertions(+), 83 deletions(-) (limited to 'tests/quick/se/00.hello') diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index b09aafac2..07eaff0f1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 0ff2f61a7..cfed15046 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21065000 # Number of ticks simulated final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31290 # Simulator instruction rate (inst/s) -host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103426086 # Simulator tick rate (ticks/s) -host_mem_usage 226120 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 36663 # Simulator instruction rate (inst/s) +host_op_rate 36659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121177991 # Simulator tick rate (ticks/s) +host_mem_usage 273132 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -214,8 +214,8 @@ system.membus.reqLayer0.occupancy 619000 # La system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu.branchPred.lookups 2884 # Number of BP lookups -system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2883 # Number of BP lookups +system.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups system.cpu.branchPred.BTBHits 756 # Number of BTB hits @@ -259,11 +259,11 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2883 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2963 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -271,24 +271,24 @@ system.cpu.fetch.PendingTrapStallCycles 747 # Nu system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.492986 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12150 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1255 8.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.068429 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.392894 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2764 # Number of cycles decode is running diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 8335373d5..90b395123 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,19 +518,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -484,6 +543,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -506,12 +566,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -521,6 +583,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -530,7 +593,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -544,11 +608,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -568,6 +634,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -579,17 +646,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 1c2de0612..3589948bc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21898500 # Number of ticks simulated final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64871 # Simulator instruction rate (inst/s) -host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275425114 # Simulator tick rate (ticks/s) -host_mem_usage 255508 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 34889 # Simulator instruction rate (inst/s) +host_op_rate 34885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148144968 # Simulator tick rate (ticks/s) +host_mem_usage 274956 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -208,9 +208,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.4 # Layer utilization (%) system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -272,31 +272,31 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3026 # Number of cycles decode is running +system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2899 # Number of cycles rename is running +system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer @@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 868 # Nu system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions @@ -538,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -556,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,32 +582,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy @@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -- cgit v1.2.3