From c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 Mon Sep 17 00:00:00 2001
From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Thu, 13 Oct 2016 23:21:40 +0100
Subject: stats: update references

---
 .../ref/alpha/linux/o3-timing-mt/config.ini        | 41 +++++++++++++---------
 1 file changed, 25 insertions(+), 16 deletions(-)

(limited to 'tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini')

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
index 83c5a15fe..965e2a045 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -600,7 +600,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -740,6 +740,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -751,7 +752,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -759,29 +760,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -801,6 +809,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -810,7 +819,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -832,9 +841,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
-- 
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