From 57e07ac2d2daaa7469241372510395e43ebe14c0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Jan 2012 07:24:45 -0800 Subject: SE/FS: Make both SE and FS tests available all the time. --HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => 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=> tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : 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=> tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => 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tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : 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=> tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : 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=> tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : 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tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py --- .../ref/alpha/linux/o3-timing/config.ini | 554 ++++++++++++++ .../ref/alpha/linux/o3-timing/simerr | 2 + .../ref/alpha/linux/o3-timing/simout | 14 + .../ref/alpha/linux/o3-timing/stats.txt | 800 +++++++++++++++++++++ 4 files changed, 1370 insertions(+) create mode 100644 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini create mode 100755 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr create mode 100755 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout create mode 100644 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt (limited to 'tests/quick/se/01.hello-2T-smt/ref/alpha/linux') diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..5ef0030d0 --- /dev/null +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,554 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1 +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=2 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload0 system.cpu.workload1 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload0] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu.workload1] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..ab4ed6a09 --- /dev/null +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:59:27 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Hello world! +Hello world! +Exiting @ tick 13202000 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt new file mode 100644 index 000000000..6ec84dd27 --- /dev/null +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -0,0 +1,800 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13202000 # Number of ticks simulated +final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 76140 # Simulator instruction rate (inst/s) +host_tick_rate 78688554 # Simulator tick rate (ticks/s) +host_mem_usage 208616 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +sim_insts 12773 # Number of instructions simulated +system.physmem.bytes_read 62144 # Number of bytes read from this memory +system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 971 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 4707165581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 3024996213 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4707165581 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 3722 # DTB read hits +system.cpu.dtb.read_misses 94 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 3816 # DTB read accesses +system.cpu.dtb.write_hits 1984 # DTB write hits +system.cpu.dtb.write_misses 61 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 2045 # DTB write accesses +system.cpu.dtb.data_hits 5706 # DTB hits +system.cpu.dtb.data_misses 155 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 5861 # DTB accesses +system.cpu.itb.fetch_hits 4091 # ITB hits +system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 4147 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload0.num_syscalls 17 # Number of system calls +system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.numCycles 26405 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4328 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4136 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9747 # Type of FU issued +system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::total 9688 # Type of FU issued +system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::total 19435 # Type of FU issued +system.cpu.iq.rate 0.736035 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed +system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp::0 0 # number of swp insts executed +system.cpu.iew.exec_swp::1 0 # number of swp insts executed +system.cpu.iew.exec_swp::total 0 # number of swp insts executed +system.cpu.iew.exec_nop::0 75 # number of nop insts executed +system.cpu.iew.exec_nop::1 65 # number of nop insts executed +system.cpu.iew.exec_nop::total 140 # number of nop insts executed +system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1521 # Number of branches executed +system.cpu.iew.exec_branches::1 1526 # Number of branches executed +system.cpu.iew.exec_branches::total 3047 # Number of branches executed +system.cpu.iew.exec_stores::0 1031 # Number of stores executed +system.cpu.iew.exec_stores::1 1027 # Number of stores executed +system.cpu.iew.exec_stores::total 2058 # Number of stores executed +system.cpu.iew.exec_rate 0.697785 # Inst execution rate +system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4555 # num instructions producing a value +system.cpu.iew.wb_producers::1 4549 # num instructions producing a value +system.cpu.iew.wb_producers::total 9104 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value +system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle +system.cpu.commit.count::0 6403 # Number of instructions committed +system.cpu.commit.count::1 6404 # Number of instructions committed +system.cpu.commit.count::total 12807 # Number of instructions committed +system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed +system.cpu.commit.refs::0 2050 # Number of memory references committed +system.cpu.commit.refs::1 2050 # Number of memory references committed +system.cpu.commit.refs::total 4100 # Number of memory references committed +system.cpu.commit.loads::0 1185 # Number of loads committed +system.cpu.commit.loads::1 1185 # Number of loads committed +system.cpu.commit.loads::total 2370 # Number of loads committed +system.cpu.commit.membars::0 0 # Number of memory barriers committed +system.cpu.commit.membars::1 0 # Number of memory barriers committed +system.cpu.commit.membars::total 0 # Number of memory barriers committed +system.cpu.commit.branches::0 1051 # Number of branches committed +system.cpu.commit.branches::1 1051 # Number of branches committed +system.cpu.commit.branches::total 2102 # Number of branches committed +system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. +system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. +system.cpu.commit.function_calls::0 127 # Number of function calls committed. +system.cpu.commit.function_calls::1 127 # Number of function calls committed. +system.cpu.commit.function_calls::total 254 # Number of function calls committed. +system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 101307 # The number of ROB reads +system.cpu.rob.rob_writes 46689 # The number of ROB writes +system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6386 # Number of Instructions Simulated +system.cpu.committedInsts::1 6387 # Number of Instructions Simulated +system.cpu.committedInsts_total 12773 # Number of Instructions Simulated +system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23374 # number of integer regfile reads +system.cpu.int_regfile_writes 13316 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.fp_regfile_writes 4 # number of floating regfile writes +system.cpu.misc_regfile_reads 2 # number of misc regfile reads +system.cpu.misc_regfile_writes 2 # number of misc regfile writes +system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::1 0 # number of replacements +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use +system.cpu.icache.total_refs 3236 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 314.165301 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.153401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3236 # number of ReadReq hits +system.cpu.icache.demand_hits 3236 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3236 # number of overall hits +system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses +system.cpu.icache.demand_misses 855 # number of demand (read+write) misses +system.cpu.icache.overall_misses 855 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::0 30710500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::0 30710500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::0 30710500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.208995 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.208995 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.208995 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 35918.713450 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35918.713450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 35918.713450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35918.713450 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::0 0 # number of writebacks +system.cpu.icache.writebacks::1 0 # number of writebacks +system.cpu.icache.writebacks::total 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::0 22267000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::0 22267000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::0 22267000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153019 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153019 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.153019 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153019 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.153019 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153019 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements +system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use +system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 216.133399 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.052767 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 3303 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits +system.cpu.dcache.demand_hits 4323 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 4323 # number of overall hits +system.cpu.dcache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses +system.cpu.dcache.demand_misses 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::0 11179500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 24106500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::0 35286000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::0 35286000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 5341 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 5341 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085295 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.190601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.190601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 36297.077922 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36297.077922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33952.816901 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33952.816901 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34662.082515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34662.082515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34662.082515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34662.082515 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::0 0 # number of writebacks +system.cpu.dcache.writebacks::1 0 # number of writebacks +system.cpu.dcache.writebacks::total 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::0 107 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::0 671 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::0 671 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::0 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::0 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::0 12674000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::0 12674000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.064969 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064969 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.064969 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064969 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements::0 0 # number of replacements +system.cpu.l2cache.replacements::1 0 # number of replacements +system.cpu.l2cache.replacements::total 0 # number of replacements +system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 435.235373 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.013282 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 971 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::0 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::0 33536000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::0 33536000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::0 0 # number of writebacks +system.cpu.l2cache.writebacks::1 0 # number of writebacks +system.cpu.l2cache.writebacks::total 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- -- cgit v1.2.3