From b006ad26d45dae3e336d7fc422adab0a330ba24a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 21 Apr 2016 04:48:24 -0400 Subject: stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding. --- .../mips/linux/learning-gem5-p1-two-level/stats.txt | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'tests/quick/se/03.learning-gem5/ref/mips') diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index c1870ce65..2c65c222a 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44023 # Simulator instruction rate (inst/s) -host_op_rate 44007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 459268108 # Simulator tick rate (ticks/s) -host_mem_usage 612532 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 350541 # Simulator instruction rate (inst/s) +host_op_rate 350101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3650563038 # Simulator tick rate (ticks/s) +host_mem_usage 636120 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -395,8 +395,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -429,7 +427,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 94 # number of replacements system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. @@ -487,8 +484,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses @@ -513,7 +508,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -633,8 +627,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses @@ -679,7 +671,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution -- cgit v1.2.3