From ed08dc31babd83c5c4a439b4d189599dfeea33d1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 23 Mar 2015 06:57:31 -0400 Subject: tests: Final reclassification of quick regressions A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). --HG-- rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/se/10.mcf/test.py => tests/quick/se/10.mcf/test.py rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/se/30.eon/test.py => tests/quick/se/30.eon/test.py --- .../ref/arm/linux/simple-atomic/chair.cook.ppm | 4 + .../10.mcf/ref/arm/linux/simple-atomic/config.ini | 270 ++++++ .../se/10.mcf/ref/arm/linux/simple-atomic/mcf.out | 999 +++++++++++++++++++++ .../se/10.mcf/ref/arm/linux/simple-atomic/simerr | 1 + .../se/10.mcf/ref/arm/linux/simple-atomic/simout | 27 + .../10.mcf/ref/arm/linux/simple-atomic/stats.txt | 245 +++++ 6 files changed, 1546 insertions(+) create mode 100644 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm create mode 100644 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini create mode 100644 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out create mode 100755 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr create mode 100755 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout create mode 100644 tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt (limited to 'tests/quick/se/10.mcf/ref/arm/linux/simple-atomic') diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm new file mode 100644 index 000000000..9ac19076f --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm @@ -0,0 +1,4 @@ +P6 +15 15 +255 +   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..392920ac8 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,270 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:268435455 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..1a4f96712 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..c759bbe65 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,27 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:11:38 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x63b66c0 +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 54240661000 because target called exit() diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..b143a6790 --- /dev/null +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,245 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.054141 # Number of seconds simulated +sim_ticks 54141000000 # Number of ticks simulated +final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1893120 # Simulator instruction rate (inst/s) +host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1131265211 # Simulator tick rate (ticks/s) +host_mem_usage 433636 # Number of bytes of host memory used +host_seconds 47.86 # Real time elapsed on the host +sim_insts 90602407 # Number of instructions simulated +sim_ops 91053638 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory +system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 108282001 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602407 # Number of instructions committed +system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions +system.cpu.num_store_insts 4744844 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram + +---------- End Simulation Statistics ---------- -- cgit v1.2.3