From 2136feaa55af60d407fe51df5309494dd9c374fb Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 10 May 2014 22:13:51 -0400 Subject: tests: update eio ref outputs for new stats Also committed reference config.json files for the eio tests. --- .../ref/alpha/eio/simple-atomic/config.ini | 2 + .../ref/alpha/eio/simple-atomic/config.json | 186 ++++++++++++ .../ref/alpha/eio/simple-atomic/simout | 6 +- .../ref/alpha/eio/simple-atomic/stats.txt | 45 ++- .../ref/alpha/eio/simple-timing/config.ini | 2 + .../ref/alpha/eio/simple-timing/config.json | 322 +++++++++++++++++++++ .../ref/alpha/eio/simple-timing/simout | 6 +- .../ref/alpha/eio/simple-timing/stats.txt | 45 ++- 8 files changed, 598 insertions(+), 16 deletions(-) create mode 100644 tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json create mode 100644 tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json (limited to 'tests/quick/se/20.eio-short') diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index fb0cfcac5..c59537dfb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -70,6 +71,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu.tracer diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json new file mode 100644 index 000000000..f16d8f1f9 --- /dev/null +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json @@ -0,0 +1,186 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout index 7f750f485..63ff01637 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:45 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:56:07 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index b531b1361..50004b5f6 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1916007 # Simulator instruction rate (inst/s) -host_op_rate 1915868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 957925931 # Simulator tick rate (ticks/s) -host_mem_usage 266944 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 2753718 # Simulator instruction rate (inst/s) +host_op_rate 2753463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1376691607 # Simulator tick rate (ticks/s) +host_mem_usage 219892 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 500032 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 59023 # Number of branches fetched +system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 500019 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 35221c77a..1136d541a 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -64,6 +65,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu.tracer diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json new file mode 100644 index 000000000..32695de47 --- /dev/null +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json @@ -0,0 +1,322 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 262144 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 0, + "eventq_index": 0, + "toL2Bus": { + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "name": "toL2Bus", + "header_cycles": 1, + "width": 32, + "eventq_index": 0, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.cpu.toL2Bus", + "type": "CoherentBus", + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 131072 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "l2cache": { + "assoc": 8, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "name": "l2cache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "hit_latency": 20, + "mshrs": 20, + "response_latency": 20, + "is_top_level": false, + "tgts_per_mshr": 12, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.l2cache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 2097152 + }, + "path": "system.cpu", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout index b4917adea..584e42e77 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:45 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:55:42 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 874d16910..b7fd6736b 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu sim_ticks 727072000 # Number of ticks simulated final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056088 # Simulator instruction rate (inst/s) -host_op_rate 1056045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1535580911 # Simulator tick rate (ticks/s) -host_mem_usage 276676 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host +host_inst_rate 1291108 # Simulator instruction rate (inst/s) +host_op_rate 1291046 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1877262486 # Simulator tick rate (ticks/s) +host_mem_usage 229624 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 1454144 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 59023 # Number of branches fetched +system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. -- cgit v1.2.3