From 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 24 Jan 2013 12:29:00 -0600 Subject: regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables. --- .../ref/sparc/linux/simple-atomic-mp/config.ini | 84 ++++++++-------------- .../ref/sparc/linux/simple-atomic-mp/simout | 8 ++- .../ref/sparc/linux/simple-atomic-mp/stats.txt | 10 +-- 3 files changed, 40 insertions(+), 62 deletions(-) (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp') diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 6cfde7057..606c05841 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -15,6 +15,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -43,6 +44,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -53,6 +55,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu0.tracer width=1 @@ -67,21 +70,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -98,21 +96,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -121,6 +114,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts +[system.cpu0.isa] +type=SparcISA + [system.cpu0.itb] type=SparcTLB size=64 @@ -136,7 +132,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -149,11 +145,11 @@ uid=100 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -162,6 +158,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -172,6 +169,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu1.tracer width=1 @@ -186,21 +184,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -217,21 +210,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -240,6 +228,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts +[system.cpu1.isa] +type=SparcISA + [system.cpu1.itb] type=SparcTLB size=64 @@ -249,11 +240,11 @@ type=ExeTracer [system.cpu2] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -262,6 +253,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -272,6 +264,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu2.tracer width=1 @@ -286,21 +279,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -317,21 +305,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -340,6 +323,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts +[system.cpu2.isa] +type=SparcISA + [system.cpu2.itb] type=SparcTLB size=64 @@ -349,11 +335,11 @@ type=ExeTracer [system.cpu3] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -362,6 +348,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -372,6 +359,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu3.tracer width=1 @@ -386,21 +374,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -417,21 +400,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -440,6 +418,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts +[system.cpu3.isa] +type=SparcISA + [system.cpu3.itb] type=SparcTLB size=64 @@ -454,21 +435,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index c63257902..e013c98f2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 2 2012 11:45:16 -gem5 started Nov 2 2012 11:45:52 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 15:49:24 +gem5 started Jan 23 2013 16:09:53 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index bb7e4e4f9..45b73a0af 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174734 # Simulator instruction rate (inst/s) -host_op_rate 174733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22625965 # Simulator tick rate (ticks/s) -host_mem_usage 1150028 # Number of bytes of host memory used -host_seconds 3.88 # Real time elapsed on the host +host_inst_rate 205117 # Simulator instruction rate (inst/s) +host_op_rate 205116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26560282 # Simulator tick rate (ticks/s) +host_mem_usage 1206900 # Number of bytes of host memory used +host_seconds 3.30 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -- cgit v1.2.3