From f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 29 Mar 2017 16:14:05 -0700 Subject: stats: Update some stats after simulated program exit behavior was changed. The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- .../ref/sparc/linux/simple-timing-mp/config.ini | 88 ++++++++++++++-------- 1 file changed, 56 insertions(+), 32 deletions(-) (limited to 'tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini') diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 524dea641..02e1544f6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -94,14 +95,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -206,7 +211,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -215,14 +220,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -260,6 +266,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer workload=system.cpu0.workload @@ -269,14 +276,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -290,6 +297,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -302,15 +310,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -320,14 +329,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -341,6 +350,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -353,15 +363,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -412,6 +423,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer workload=system.cpu0.workload @@ -421,14 +433,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -442,6 +454,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -454,15 +467,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -472,14 +486,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -493,6 +507,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -505,15 +520,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -564,6 +580,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer workload=system.cpu0.workload @@ -573,14 +590,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -594,6 +611,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -606,15 +624,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -624,14 +643,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -645,6 +664,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -657,15 +677,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -703,14 +724,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -724,6 +745,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -736,15 +758,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -783,6 +806,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -790,7 +814,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] -- cgit v1.2.3