From f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 29 Mar 2017 16:14:05 -0700 Subject: stats: Update some stats after simulated program exit behavior was changed. The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- .../ref/sparc/linux/o3-timing-mp/simout | 8 +- .../ref/sparc/linux/o3-timing-mp/stats.txt | 22 +- .../ref/sparc/linux/simple-atomic-mp/config.ini | 88 +- .../ref/sparc/linux/simple-atomic-mp/simerr | 1 + .../ref/sparc/linux/simple-atomic-mp/simout | 11 +- .../ref/sparc/linux/simple-atomic-mp/stats.txt | 2054 ++++++------ .../ref/sparc/linux/simple-timing-mp/config.ini | 88 +- .../ref/sparc/linux/simple-timing-mp/simerr | 1 + .../ref/sparc/linux/simple-timing-mp/simout | 69 +- .../ref/sparc/linux/simple-timing-mp/stats.txt | 3310 ++++++++++---------- 10 files changed, 2850 insertions(+), 2802 deletions(-) (limited to 'tests/quick/se/40.m5threads-test-atomic/ref') diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 8d377039e..7ee3ff550 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 29 2017 20:18:54 -gem5 started Mar 29 2017 20:19:04 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 121347 +gem5 compiled Mar 29 2017 21:12:17 +gem5 started Mar 29 2017 21:12:27 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 42630 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 126524000 because target called exit() +Exiting @ tick 126524000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index c550cf53f..a10174db1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000127 sim_ticks 126524000 final_tick 126524000 sim_freq 1000000000000 -host_inst_rate 214440 -host_op_rate 214440 -host_tick_rate 23217304 +host_inst_rate 211101 +host_op_rate 211100 +host_tick_rate 22855727 host_mem_usage 280860 -host_seconds 5.45 +host_seconds 5.54 sim_insts 1168600 sim_ops 1168600 system.voltage_domain.voltage 1 @@ -316,7 +316,7 @@ system.cpu0.fetch.Insts 585438 system.cpu0.fetch.Branches 99156 system.cpu0.fetch.predictedBranches 90042 system.cpu0.fetch.Cycles 194902 -system.cpu0.fetch.SquashCycles 3487 +system.cpu0.fetch.SquashCycles 3486 system.cpu0.fetch.MiscStallCycles 9 system.cpu0.fetch.PendingTrapStallCycles 2371 system.cpu0.fetch.IcacheWaitRetryStallCycles 8 @@ -373,7 +373,7 @@ system.cpu0.iq.iqInstsAdded 468496 system.cpu0.iq.iqNonSpecInstsAdded 1145 system.cpu0.iq.iqInstsIssued 464441 system.cpu0.iq.iqSquashedInstsIssued 106 -system.cpu0.iq.iqSquashedInstsExamined 16686 +system.cpu0.iq.iqSquashedInstsExamined 16685 system.cpu0.iq.iqSquashedOperandsExamined 13469 system.cpu0.iq.iqSquashedNonSpecRemoved 586 system.cpu0.iq.issued_per_cycle::samples 222303 @@ -474,7 +474,7 @@ system.cpu0.iq.rate 1.835380 system.cpu0.iq.fu_busy_cnt 333 system.cpu0.iq.fu_busy_rate 0.000717 system.cpu0.iq.int_inst_queue_reads 1151624 -system.cpu0.iq.int_inst_queue_writes 486379 +system.cpu0.iq.int_inst_queue_writes 486378 system.cpu0.iq.int_inst_queue_wakeup_accesses 461879 system.cpu0.iq.fp_inst_queue_reads 0 system.cpu0.iq.fp_inst_queue_writes 0 @@ -592,7 +592,7 @@ system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu0.commit.op_class_0::total 540180 system.cpu0.commit.bw_lim_events 456 system.cpu0.rob.rob_reads 774865 -system.cpu0.rob.rob_writes 1118644 +system.cpu0.rob.rob_writes 1118643 system.cpu0.timesIdled 329 system.cpu0.idleCycles 30746 system.cpu0.committedInsts 452871 @@ -1142,7 +1142,7 @@ system.cpu1.cpi 0.859746 system.cpu1.cpi_total 0.859746 system.cpu1.ipc 1.163134 system.cpu1.ipc_total 1.163134 -system.cpu1.int_regfile_reads 419202 +system.cpu1.int_regfile_reads 419203 system.cpu1.int_regfile_writes 195886 system.cpu1.fp_regfile_writes 64 system.cpu1.misc_regfile_reads 120419 @@ -1682,7 +1682,7 @@ system.cpu2.cpi 0.897099 system.cpu2.cpi_total 0.897099 system.cpu2.ipc 1.114704 system.cpu2.ipc_total 1.114704 -system.cpu2.int_regfile_reads 403345 +system.cpu2.int_regfile_reads 403346 system.cpu2.int_regfile_writes 188790 system.cpu2.fp_regfile_writes 64 system.cpu2.misc_regfile_reads 114754 @@ -2218,7 +2218,7 @@ system.cpu3.cpi 0.704137 system.cpu3.cpi_total 0.704137 system.cpu3.ipc 1.420178 system.cpu3.ipc_total 1.420178 -system.cpu3.int_regfile_reads 509137 +system.cpu3.int_regfile_reads 509138 system.cpu3.int_regfile_writes 236602 system.cpu3.fp_regfile_writes 64 system.cpu3.misc_regfile_reads 150205 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index d84a9f055..9aefbd6d1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer width=1 @@ -98,14 +99,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -119,6 +120,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -131,15 +133,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -149,14 +152,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -170,6 +173,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -182,15 +186,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -210,7 +215,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -219,14 +224,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -267,6 +273,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer width=1 @@ -277,14 +284,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -298,6 +305,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -310,15 +318,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -328,14 +337,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -349,6 +358,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -361,15 +371,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -423,6 +434,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer width=1 @@ -433,14 +445,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -454,6 +466,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -466,15 +479,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -484,14 +498,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -505,6 +519,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -517,15 +532,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -579,6 +595,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer width=1 @@ -589,14 +606,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -610,6 +627,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -622,15 +640,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -640,14 +659,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -661,6 +680,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -673,15 +693,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -719,14 +740,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -740,6 +761,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -752,15 +774,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -799,6 +822,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -806,7 +830,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index f5b06fc1f..527306347 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38680 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126091 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 @@ -82,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 87707000 because target called exit() +Exiting @ tick 87707000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e242611fb..e21097758 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,1031 +1,1031 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87707000 # Number of ticks simulated -final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154171 # Simulator instruction rate (inst/s) -host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149440007 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 677333 # Number of instructions simulated -sim_ops 677333 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 559 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 175415 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 175326 # Number of instructions committed -system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls -system.cpu0.num_int_insts 120376 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 82397 # number of memory refs -system.cpu0.num_load_insts 54591 # Number of load instructions -system.cpu0.num_store_insts 27806 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 29689 # Number of branches fetched -system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits -system.cpu0.dcache.overall_hits::total 82008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses -system.cpu0.dcache.overall_misses::total 328 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 173297 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167400 # Number of instructions committed -system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107326 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 49494 # number of memory refs -system.cpu1.num_load_insts 39345 # Number of load instructions -system.cpu1.num_store_insts 10149 # Number of store instructions -system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles -system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles -system.cpu1.Branches 35694 # Number of branches fetched -system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction -system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction -system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits -system.cpu1.dcache.overall_hits::total 49120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses -system.cpu1.dcache.overall_misses::total 287 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 278 # number of writebacks -system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 173296 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167335 # Number of instructions committed -system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls -system.cpu2.num_int_insts 114196 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read -system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59830 # number of memory refs -system.cpu2.num_load_insts 42793 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles -system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles -system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.Branches 32221 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction -system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits -system.cpu2.dcache.overall_hits::total 59499 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses -system.cpu2.dcache.overall_misses::total 255 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 278 # number of writebacks -system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 173297 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167272 # Number of instructions committed -system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls -system.cpu3.num_int_insts 113295 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 58510 # number of memory refs -system.cpu3.num_load_insts 42344 # Number of load instructions -system.cpu3.num_store_insts 16166 # Number of store instructions -system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles -system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles -system.cpu3.Branches 32639 # Number of branches fetched -system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction -system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction -system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits -system.cpu3.dcache.overall_hits::total 58176 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses -system.cpu3.dcache.overall_misses::total 260 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 279 # number of writebacks -system.cpu3.icache.writebacks::total 279 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use -system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19423 # Number of tag accesses -system.l2c.tags.data_accesses 19423 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 799 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 799 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.218885 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram +sim_seconds 0.000088 +sim_ticks 87707000 +final_tick 87707000 +sim_freq 1000000000000 +host_inst_rate 1004816 +host_op_rate 1004778 +host_tick_rate 130103429 +host_mem_usage 276508 +host_seconds 0.67 +sim_insts 677333 +sim_ops 677333 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 +system.physmem.bytes_read::cpu0.inst 18048 +system.physmem.bytes_read::cpu0.data 10560 +system.physmem.bytes_read::cpu1.inst 3968 +system.physmem.bytes_read::cpu1.data 1280 +system.physmem.bytes_read::cpu2.inst 192 +system.physmem.bytes_read::cpu2.data 832 +system.physmem.bytes_read::cpu3.inst 64 +system.physmem.bytes_read::cpu3.data 832 +system.physmem.bytes_read::total 35776 +system.physmem.bytes_inst_read::cpu0.inst 18048 +system.physmem.bytes_inst_read::cpu1.inst 3968 +system.physmem.bytes_inst_read::cpu2.inst 192 +system.physmem.bytes_inst_read::cpu3.inst 64 +system.physmem.bytes_inst_read::total 22272 +system.physmem.num_reads::cpu0.inst 282 +system.physmem.num_reads::cpu0.data 165 +system.physmem.num_reads::cpu1.inst 62 +system.physmem.num_reads::cpu1.data 20 +system.physmem.num_reads::cpu2.inst 3 +system.physmem.num_reads::cpu2.data 13 +system.physmem.num_reads::cpu3.inst 1 +system.physmem.num_reads::cpu3.data 13 +system.physmem.num_reads::total 559 +system.physmem.bw_read::cpu0.inst 205776050 +system.physmem.bw_read::cpu0.data 120400880 +system.physmem.bw_read::cpu1.inst 45241543 +system.physmem.bw_read::cpu1.data 14594046 +system.physmem.bw_read::cpu2.inst 2189107 +system.physmem.bw_read::cpu2.data 9486130 +system.physmem.bw_read::cpu3.inst 729702 +system.physmem.bw_read::cpu3.data 9486130 +system.physmem.bw_read::total 407903588 +system.physmem.bw_inst_read::cpu0.inst 205776050 +system.physmem.bw_inst_read::cpu1.inst 45241543 +system.physmem.bw_inst_read::cpu2.inst 2189107 +system.physmem.bw_inst_read::cpu3.inst 729702 +system.physmem.bw_inst_read::total 253936402 +system.physmem.bw_total::cpu0.inst 205776050 +system.physmem.bw_total::cpu0.data 120400880 +system.physmem.bw_total::cpu1.inst 45241543 +system.physmem.bw_total::cpu1.data 14594046 +system.physmem.bw_total::cpu2.inst 2189107 +system.physmem.bw_total::cpu2.data 9486130 +system.physmem.bw_total::cpu3.inst 729702 +system.physmem.bw_total::cpu3.data 9486130 +system.physmem.bw_total::total 407903588 +system.pwrStateResidencyTicks::UNDEFINED 87707000 +system.cpu_clk_domain.clock 500 +system.cpu0.workload.numSyscalls 26 +system.cpu0.pwrStateResidencyTicks::ON 87707000 +system.cpu0.numCycles 175415 +system.cpu0.numWorkItemsStarted 0 +system.cpu0.numWorkItemsCompleted 0 +system.cpu0.committedInsts 175326 +system.cpu0.committedOps 175326 +system.cpu0.num_int_alu_accesses 120376 +system.cpu0.num_fp_alu_accesses 0 +system.cpu0.num_func_calls 390 +system.cpu0.num_conditional_control_insts 28824 +system.cpu0.num_int_insts 120376 +system.cpu0.num_fp_insts 0 +system.cpu0.num_int_register_reads 349286 +system.cpu0.num_int_register_writes 121983 +system.cpu0.num_fp_register_reads 0 +system.cpu0.num_fp_register_writes 0 +system.cpu0.num_mem_refs 82397 +system.cpu0.num_load_insts 54591 +system.cpu0.num_store_insts 27806 +system.cpu0.num_idle_cycles 0 +system.cpu0.num_busy_cycles 175415 +system.cpu0.not_idle_fraction 1 +system.cpu0.idle_fraction 0 +system.cpu0.Branches 29689 +system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% +system.cpu0.op_class::IntAlu 66491 37.91% 52.97% +system.cpu0.op_class::IntMult 0 0.00% 52.97% +system.cpu0.op_class::IntDiv 0 0.00% 52.97% +system.cpu0.op_class::FloatAdd 0 0.00% 52.97% +system.cpu0.op_class::FloatCmp 0 0.00% 52.97% +system.cpu0.op_class::FloatCvt 0 0.00% 52.97% +system.cpu0.op_class::FloatMult 0 0.00% 52.97% +system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% +system.cpu0.op_class::FloatDiv 0 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+system.l2c.ReadCleanReq_accesses::cpu2.inst 358 +system.l2c.ReadCleanReq_accesses::cpu3.inst 359 +system.l2c.ReadCleanReq_accesses::total 1542 +system.l2c.ReadSharedReq_accesses::cpu0.data 71 +system.l2c.ReadSharedReq_accesses::cpu1.data 10 +system.l2c.ReadSharedReq_accesses::cpu2.data 10 +system.l2c.ReadSharedReq_accesses::cpu3.data 10 +system.l2c.ReadSharedReq_accesses::total 101 +system.l2c.demand_accesses::cpu0.inst 467 +system.l2c.demand_accesses::cpu0.data 170 +system.l2c.demand_accesses::cpu1.inst 358 +system.l2c.demand_accesses::cpu1.data 23 +system.l2c.demand_accesses::cpu2.inst 358 +system.l2c.demand_accesses::cpu2.data 22 +system.l2c.demand_accesses::cpu3.inst 359 +system.l2c.demand_accesses::cpu3.data 22 +system.l2c.demand_accesses::total 1779 +system.l2c.overall_accesses::cpu0.inst 467 +system.l2c.overall_accesses::cpu0.data 170 +system.l2c.overall_accesses::cpu1.inst 358 +system.l2c.overall_accesses::cpu1.data 23 +system.l2c.overall_accesses::cpu2.inst 358 +system.l2c.overall_accesses::cpu2.data 22 +system.l2c.overall_accesses::cpu3.inst 359 +system.l2c.overall_accesses::cpu3.data 22 +system.l2c.overall_accesses::total 1779 +system.l2c.ReadExReq_miss_rate::cpu0.data 1 +system.l2c.ReadExReq_miss_rate::cpu1.data 1 +system.l2c.ReadExReq_miss_rate::cpu2.data 1 +system.l2c.ReadExReq_miss_rate::cpu3.data 1 +system.l2c.ReadExReq_miss_rate::total 1 +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 +system.l2c.ReadCleanReq_miss_rate::total 0.225681 +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 +system.l2c.ReadSharedReq_miss_rate::total 0.742574 +system.l2c.demand_miss_rate::cpu0.inst 0.603854 +system.l2c.demand_miss_rate::cpu0.data 0.970588 +system.l2c.demand_miss_rate::cpu1.inst 0.173184 +system.l2c.demand_miss_rate::cpu1.data 0.869565 +system.l2c.demand_miss_rate::cpu2.inst 0.008380 +system.l2c.demand_miss_rate::cpu2.data 0.590909 +system.l2c.demand_miss_rate::cpu3.inst 0.002786 +system.l2c.demand_miss_rate::cpu3.data 0.590909 +system.l2c.demand_miss_rate::total 0.314221 +system.l2c.overall_miss_rate::cpu0.inst 0.603854 +system.l2c.overall_miss_rate::cpu0.data 0.970588 +system.l2c.overall_miss_rate::cpu1.inst 0.173184 +system.l2c.overall_miss_rate::cpu1.data 0.869565 +system.l2c.overall_miss_rate::cpu2.inst 0.008380 +system.l2c.overall_miss_rate::cpu2.data 0.590909 +system.l2c.overall_miss_rate::cpu3.inst 0.002786 +system.l2c.overall_miss_rate::cpu3.data 0.590909 +system.l2c.overall_miss_rate::total 0.314221 +system.l2c.blocked_cycles::no_mshrs 0 +system.l2c.blocked_cycles::no_targets 0 +system.l2c.blocked::no_mshrs 0 +system.l2c.blocked::no_targets 0 +system.l2c.avg_blocked_cycles::no_mshrs nan +system.l2c.avg_blocked_cycles::no_targets nan +system.membus.snoop_filter.tot_requests 799 +system.membus.snoop_filter.hit_single_requests 240 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 +system.membus.trans_dist::ReadResp 423 +system.membus.trans_dist::UpgradeReq 193 +system.membus.trans_dist::ReadExReq 183 +system.membus.trans_dist::ReadExResp 136 +system.membus.trans_dist::ReadSharedReq 423 +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 +system.membus.pkt_count::total 1358 +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 +system.membus.pkt_size::total 35776 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 799 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 799 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 799 +system.toL2Bus.snoop_filter.tot_requests 3918 +system.toL2Bus.snoop_filter.hit_single_requests 1142 +system.toL2Bus.snoop_filter.hit_multi_requests 1788 +system.toL2Bus.snoop_filter.tot_snoops 0 +system.toL2Bus.snoop_filter.hit_single_snoops 0 +system.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 +system.toL2Bus.trans_dist::ReadResp 2179 +system.toL2Bus.trans_dist::WritebackDirty 1 +system.toL2Bus.trans_dist::WritebackClean 1050 +system.toL2Bus.trans_dist::CleanEvict 1 +system.toL2Bus.trans_dist::UpgradeReq 275 +system.toL2Bus.trans_dist::UpgradeResp 275 +system.toL2Bus.trans_dist::ReadExReq 412 +system.toL2Bus.trans_dist::ReadExResp 412 +system.toL2Bus.trans_dist::ReadCleanReq 1542 +system.toL2Bus.trans_dist::ReadSharedReq 637 +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 +system.toL2Bus.pkt_count::total 6784 +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 +system.toL2Bus.pkt_size::total 233088 +system.toL2Bus.snoops 0 +system.toL2Bus.snoopTraffic 0 +system.toL2Bus.snoop_fanout::samples 3918 +system.toL2Bus.snoop_fanout::mean 1.279735 +system.toL2Bus.snoop_fanout::stdev 1.218885 +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% +system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% +system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% +system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 3 +system.toL2Bus.snoop_fanout::total 3918 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 524dea641..02e1544f6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -94,14 +95,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -206,7 +211,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -215,14 +220,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -260,6 +266,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer workload=system.cpu0.workload @@ -269,14 +276,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -290,6 +297,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -302,15 +310,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -320,14 +329,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -341,6 +350,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -353,15 +363,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -412,6 +423,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer workload=system.cpu0.workload @@ -421,14 +433,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -442,6 +454,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -454,15 +467,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -472,14 +486,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -493,6 +507,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -505,15 +520,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -564,6 +580,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer workload=system.cpu0.workload @@ -573,14 +590,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -594,6 +611,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -606,15 +624,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -624,14 +643,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -645,6 +664,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -657,15 +677,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -703,14 +724,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -724,6 +745,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -736,15 +758,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -783,6 +806,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -790,7 +814,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index dc5d474a6..771ec0419 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38675 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126092 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 @@ -27,59 +26,59 @@ Iteration 1 completed Iteration 2 completed [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock [Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 264174500 because target called exit() +Exiting @ tick 263409500 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index bdf146296..e816fec12 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,1659 +1,1659 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263409500 # Number of ticks simulated -final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870162 # Simulator instruction rate (inst/s) -host_op_rate 870149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345251596 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.76 # Real time elapsed on the host -sim_insts 663871 # Number of instructions simulated -sim_ops 663871 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 526819 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158244 # Number of instructions committed -system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108988 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73856 # number of memory refs -system.cpu0.num_load_insts 48897 # Number of load instructions -system.cpu0.num_store_insts 24959 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26842 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158306 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits -system.cpu0.dcache.overall_hits::total 73442 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits -system.cpu0.icache.overall_hits::total 157840 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 526818 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 169340 # Number of instructions committed -system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111465 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54688 # number of memory refs -system.cpu1.num_load_insts 41399 # Number of load instructions -system.cpu1.num_store_insts 13289 # Number of store instructions -system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles -system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles -system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles -system.cpu1.Branches 34599 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction -system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction -system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 169372 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits -system.cpu1.dcache.overall_hits::total 54340 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses -system.cpu1.dcache.overall_misses::total 269 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits -system.cpu1.icache.overall_hits::total 169007 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 280 # number of writebacks -system.cpu1.icache.writebacks::total 280 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 526819 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165892 # Number of instructions committed -system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110657 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read -system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55200 # number of memory refs -system.cpu2.num_load_insts 40995 # Number of load instructions -system.cpu2.num_store_insts 14205 # Number of store instructions -system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles -system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles -system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles -system.cpu2.Branches 33279 # Number of branches fetched -system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction -system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction -system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165924 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits -system.cpu2.dcache.overall_hits::total 54855 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses -system.cpu2.dcache.overall_misses::total 267 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits -system.cpu2.icache.overall_hits::total 165559 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 280 # number of writebacks -system.cpu2.icache.writebacks::total 280 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 526818 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 170395 # Number of instructions committed -system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111057 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53550 # number of memory refs -system.cpu3.num_load_insts 41191 # Number of load instructions -system.cpu3.num_store_insts 12359 # Number of store instructions -system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles -system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles -system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles -system.cpu3.Branches 35332 # Number of branches fetched -system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction -system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction -system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 170427 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits -system.cpu3.dcache.overall_hits::total 53200 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits -system.cpu3.icache.overall_hits::total 170061 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses -system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 281 # number of writebacks -system.cpu3.icache.writebacks::total 281 # number of writebacks -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use -system.l2c.tags.total_refs 1794 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 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50500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 771500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 28924000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14401000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 510000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 762000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 50500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 771500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28924000 # number of overall MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 839 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 839 # Request fanout histogram -system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1028 # Total snoops (count) -system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 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+system.toL2Bus.respLayer0.occupancy 700500 +system.toL2Bus.respLayer0.utilization 0.3 +system.toL2Bus.respLayer1.occupancy 499498 +system.toL2Bus.respLayer1.utilization 0.2 +system.toL2Bus.respLayer2.occupancy 550995 +system.toL2Bus.respLayer2.utilization 0.2 +system.toL2Bus.respLayer3.occupancy 431976 +system.toL2Bus.respLayer3.utilization 0.2 +system.toL2Bus.respLayer4.occupancy 552491 +system.toL2Bus.respLayer4.utilization 0.2 +system.toL2Bus.respLayer5.occupancy 427974 +system.toL2Bus.respLayer5.utilization 0.2 +system.toL2Bus.respLayer6.occupancy 554986 +system.toL2Bus.respLayer6.utilization 0.2 +system.toL2Bus.respLayer7.occupancy 431477 +system.toL2Bus.respLayer7.utilization 0.2 ---------- End Simulation Statistics ---------- -- cgit v1.2.3