From fa1fbcf020ee9aacdd4a7a09e81a633e09bad97a Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 1 Sep 2014 16:55:52 -0500
Subject: stats: updates due to recent ruby and x86 changes Also updates many
 out of date config files.

---
 .../quick/se/50.memtest/ref/null/none/memtest/config.ini | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

(limited to 'tests/quick/se/50.memtest/ref/null/none/memtest/config.ini')

diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index dd37e6b1e..62f705803 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.funcmem system.physmem
@@ -36,7 +38,9 @@ system_port=system.membus.slave[1]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
@@ -490,9 +494,19 @@ size=32768
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
-- 
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