From 57e07ac2d2daaa7469241372510395e43ebe14c0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Jan 2012 07:24:45 -0800 Subject: SE/FS: Make both SE and FS tests available all the time. --HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => 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=> tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : 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=> tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => 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tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : 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=> tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : 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=> tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : 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tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py --- .../rubytest-ruby-MESI_CMP_directory/config.ini | 279 ++++ .../rubytest-ruby-MESI_CMP_directory/ruby.stats | 641 +++++++++ .../linux/rubytest-ruby-MESI_CMP_directory/simerr | 1 + .../linux/rubytest-ruby-MESI_CMP_directory/simout | 10 + .../rubytest-ruby-MESI_CMP_directory/stats.txt | 17 + .../rubytest-ruby-MOESI_CMP_directory/config.ini | 275 ++++ .../rubytest-ruby-MOESI_CMP_directory/ruby.stats | 1470 ++++++++++++++++++++ .../linux/rubytest-ruby-MOESI_CMP_directory/simerr | 1 + .../linux/rubytest-ruby-MOESI_CMP_directory/simout | 10 + .../rubytest-ruby-MOESI_CMP_directory/stats.txt | 17 + .../linux/rubytest-ruby-MOESI_CMP_token/config.ini | 286 ++++ .../linux/rubytest-ruby-MOESI_CMP_token/ruby.stats | 1049 ++++++++++++++ .../linux/rubytest-ruby-MOESI_CMP_token/simerr | 1 + .../linux/rubytest-ruby-MOESI_CMP_token/simout | 10 + .../linux/rubytest-ruby-MOESI_CMP_token/stats.txt | 17 + .../linux/rubytest-ruby-MOESI_hammer/config.ini | 254 ++++ .../linux/rubytest-ruby-MOESI_hammer/ruby.stats | 972 +++++++++++++ .../alpha/linux/rubytest-ruby-MOESI_hammer/simerr | 1 + .../alpha/linux/rubytest-ruby-MOESI_hammer/simout | 10 + .../linux/rubytest-ruby-MOESI_hammer/stats.txt | 17 + .../ref/alpha/linux/rubytest-ruby/config.ini | 220 +++ .../ref/alpha/linux/rubytest-ruby/ruby.stats | 311 +++++ .../ref/alpha/linux/rubytest-ruby/simerr | 1 + .../ref/alpha/linux/rubytest-ruby/simout | 10 + .../ref/alpha/linux/rubytest-ruby/stats.txt | 17 + 25 files changed, 5897 insertions(+) create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr create mode 100755 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout create mode 100644 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt (limited to 'tests/quick/se/60.rubytest/ref/alpha/linux') diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini new file mode 100644 index 000000000..ad26765cf --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini @@ -0,0 +1,279 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +buffer_size=0 +cntrl_id=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +cntrl_id=1 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=true +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + +[system.tester] +type=RubyTester +check_flush=false +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.l1_cntrl0.sequencer.port[0] + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..160177fb6 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -0,0 +1,641 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 1 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:22:04 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.63 +Virtual_time_in_minutes: 0.0105 +Virtual_time_in_hours: 0.000175 +Virtual_time_in_days: 7.29167e-06 + +Ruby_current_time: 363611 +Ruby_start_time: 0 +Ruby_cycles: 363611 + +mbytes_resident: 39.3828 +mbytes_total: 209.344 +resident_ratio: 0.188125 + +ruby_cycles_executed: [ 363612 ] + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1005 average: 15.8269 | standard deviation: 1.12204 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 55 936 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 256 max: 45325 count: 990 average: 5734.15 | standard deviation: 8337.32 | 76 21 69 108 63 78 75 44 25 38 32 18 17 15 12 7 10 11 13 11 7 5 7 8 2 2 3 1 3 1 4 4 4 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 4 5 2 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 7 8 2 5 6 4 2 0 3 4 3 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 2 0 2 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 256 max: 45325 count: 45 average: 7821.33 | standard deviation: 10900.5 | 7 0 1 6 1 1 4 1 2 4 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 256 max: 43192 count: 890 average: 5921.87 | standard deviation: 8354.16 | 69 16 57 85 53 68 69 41 23 34 32 16 16 15 12 7 10 10 13 11 7 5 7 8 2 2 3 1 3 0 4 4 3 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 3 5 0 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 5 7 2 5 6 3 2 0 3 3 2 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 1 0 2 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 16 max: 1980 count: 55 average: 988.782 | standard deviation: 366.735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 1 1 2 3 0 0 3 0 3 3 0 2 1 1 2 0 1 0 1 0 0 0 1 1 0 0 1 0 0 3 0 0 0 2 1 0 1 1 1 1 1 0 1 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 45325 count: 990 average: 5734.15 | standard deviation: 8337.32 | 76 21 69 108 63 78 75 44 25 38 32 18 17 15 12 7 10 11 13 11 7 5 7 8 2 2 3 1 3 1 4 4 4 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 4 5 2 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 7 8 2 5 6 4 2 0 3 4 3 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 2 0 2 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 256 max: 45325 count: 45 average: 7821.33 | standard deviation: 10900.5 | 7 0 1 6 1 1 4 1 2 4 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_NULL: [binsize: 256 max: 43192 count: 890 average: 5921.87 | standard deviation: 8354.16 | 69 16 57 85 53 68 69 41 23 34 32 16 16 15 12 7 10 10 13 11 7 5 7 8 2 2 3 1 3 0 4 4 3 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 3 5 0 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 5 7 2 5 6 3 2 0 3 3 2 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 1 0 2 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 16 max: 1980 count: 55 average: 988.782 | standard deviation: 366.735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 1 1 2 3 0 0 3 0 3 3 0 2 1 1 2 0 1 0 1 0 0 0 1 1 0 0 1 0 0 3 0 0 0 2 1 0 1 1 1 1 1 0 1 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 64 max: 1871 count: 7077 average: 36.6084 | standard deviation: 151.734 | 6477 143 39 71 25 30 49 30 38 33 27 37 15 21 8 10 2 3 2 2 2 3 1 0 4 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 10 count: 4540 average: 0.27511 | standard deviation: 0.967186 | 4062 142 118 124 37 26 11 11 5 2 2 ] + virtual_network_0_delay_cycles: [binsize: 64 max: 1871 count: 2537 average: 101.628 | standard deviation: 240.096 | 1937 143 39 71 25 30 49 30 38 33 27 37 15 21 8 10 2 3 2 2 2 3 1 0 4 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 551 average: 0.136116 | standard deviation: 0.766337 | 529 4 3 6 4 2 1 1 1 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 10 count: 3989 average: 0.294309 | standard deviation: 0.990299 | 3533 138 115 118 33 24 10 10 4 2 2 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 10428 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 80 + +Network Stats +------------- + +total_msg_count_Control: 5404 43232 +total_msg_count_Request_Control: 1653 13224 +total_msg_count_Response_Data: 7779 560088 +total_msg_count_Response_Control: 7929 63432 +total_msg_count_Writeback_Data: 3666 263952 +total_msg_count_Writeback_Control: 93 744 +total_msgs: 26524 total_bytes: 944672 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 1.54279 + links_utilized_percent_switch_0_link_0: 1.3161 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 1.76947 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 918 66096 [ 0 918 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 758 6064 [ 0 758 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 919 7352 [ 919 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 919 7352 [ 0 57 862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 32 256 [ 32 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 2.70619 + links_utilized_percent_switch_1_link_0: 2.98272 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.42966 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 918 7344 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1798 14384 [ 0 936 862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 30 240 [ 30 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1710 123120 [ 0 1710 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 845 6760 [ 0 845 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.16361 + links_utilized_percent_switch_2_link_0: 1.11355 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 1.21366 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 792 57024 [ 0 792 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 1.80417 + links_utilized_percent_switch_3_link_0: 1.3161 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 2.98286 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 1.11355 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 918 66096 [ 0 918 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 758 6064 [ 0 758 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 918 7344 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 1798 14384 [ 0 936 862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 792 57024 [ 0 792 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 55 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 55 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 55 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 865 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 865 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.50867% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.4913% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 865 100% + + --- L1Cache --- + - Event Counts - +Load [45 ] 45 +Ifetch [147 ] 147 +Store [894 ] 894 +Inv [551 ] 551 +L1_Replacement [512283 ] 512283 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [38 ] 38 +DataS_fromL1 [0 ] 0 +Data_all_Acks [880 ] 880 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [758 ] 758 + + - Transitions - +NP Load [39 ] 39 +NP Ifetch [55 ] 55 +NP Store [826 ] 826 +NP Inv [3 ] 3 +NP L1_Replacement [0 ] 0 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Inv [0 ] 0 +I L1_Replacement [147 ] 147 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S Inv [29 ] 29 +S L1_Replacement [8 ] 8 + +E Load [0 ] 0 +E Ifetch [0 ] 0 +E Store [0 ] 0 +E Inv [6 ] 6 +E L1_Replacement [32 ] 32 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [6 ] 6 +M Ifetch [0 ] 0 +M Store [66 ] 66 +M Inv [95 ] 95 +M L1_Replacement [728 ] 728 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [19 ] 19 +IS L1_Replacement [23106 ] 23106 +IS Data_Exclusive [38 ] 38 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [37 ] 37 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [488262 ] 488262 +IM Data [0 ] 0 +IM Data_all_Acks [824 ] 824 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [19 ] 19 + +M_I Load [0 ] 0 +M_I Ifetch [92 ] 92 +M_I Store [1 ] 1 +M_I Inv [399 ] 399 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [359 ] 359 + +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 + +SINK_WB_ACK Load [0 ] 0 +SINK_WB_ACK Ifetch [0 ] 0 +SINK_WB_ACK Store [1 ] 1 +SINK_WB_ACK Inv [0 ] 0 +SINK_WB_ACK L1_Replacement [0 ] 0 +SINK_WB_ACK WB_Ack [399 ] 399 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 883 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 883 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.30351% + system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 5.77576% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.9207% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 883 100% + + --- L2Cache --- + - Event Counts - +L1_GET_INSTR [55 ] 55 +L1_GETS [39 ] 39 +L1_GETX [824 ] 824 +L1_UPGRADE [0 ] 0 +L1_PUTX [383 ] 383 +L1_PUTX_old [3508 ] 3508 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [314 ] 314 +L2_Replacement_clean [23024 ] 23024 +Mem_Data [883 ] 883 +Mem_Ack [879 ] 879 +WB_Data [478 ] 478 +WB_Data_clean [16 ] 16 +Ack [0 ] 0 +Ack_all [57 ] 57 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [861 ] 861 +MEM_Inv [0 ] 0 + + - Transitions - +NP L1_GET_INSTR [51 ] 51 +NP L1_GETS [38 ] 38 +NP L1_GETX [794 ] 794 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [146 ] 146 + +SS L1_GET_INSTR [1 ] 1 +SS L1_GETS [1 ] 1 +SS L1_GETX [3 ] 3 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [51 ] 51 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [3 ] 3 +M L1_GETS [0 ] 0 +M L1_GETX [27 ] 27 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [314 ] 314 +M L2_Replacement_clean [14 ] 14 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [359 ] 359 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L2_Replacement_clean [500 ] 500 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [253 ] 253 +M_I Mem_Ack [879 ] 879 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [0 ] 0 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [0 ] 0 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [1514 ] 1514 +MCT_I WB_Data [478 ] 478 +MCT_I WB_Data_clean [16 ] 16 +MCT_I Ack_all [6 ] 6 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [51 ] 51 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [526 ] 526 +ISS Mem_Data [38 ] 38 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [1318 ] 1318 +IS Mem_Data [51 ] 51 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [9234 ] 9234 +IM Mem_Data [794 ] 794 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [3 ] 3 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [24 ] 24 +MT_MB L1_PUTX_old [1595 ] 1595 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [11381 ] 11381 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [858 ] 858 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1675 + memory_reads: 883 + memory_writes: 792 + memory_refreshes: 758 + memory_total_request_delays: 1135 + memory_delays_per_request: 0.677612 + memory_delays_in_input_queue: 142 + memory_delays_behind_head_of_bank_queue: 3 + memory_delays_stalled_at_head_of_bank_queue: 990 + memory_stalls_for_bank_busy: 236 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 85 + memory_stalls_for_bus: 355 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 236 + memory_stalls_for_read_read_turnaround: 78 + accesses_per_bank: 45 47 58 82 66 78 55 33 49 52 38 55 46 40 51 49 52 40 55 65 70 48 54 42 54 49 52 46 55 52 44 53 + + --- Directory --- + - Event Counts - +Fetch [883 ] 883 +Data [792 ] 792 +Memory_Data [883 ] 883 +Memory_Ack [792 ] 792 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [87 ] 87 + + - Transitions - +I Fetch [883 ] 883 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [792 ] 792 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [87 ] 87 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [883 ] 883 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [792 ] 792 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE [0 ] 0 + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr new file mode 100755 index 000000000..cfdf73ce9 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr @@ -0,0 +1 @@ +hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout new file mode 100755 index 000000000..bb1def18d --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:44:57 +gem5 started Jan 23 2012 04:22:03 +gem5 executing on zizzer +command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 363611 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt new file mode 100644 index 000000000..a412dab3a --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -0,0 +1,17 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000364 # Number of seconds simulated +sim_ticks 363611 # Number of ticks simulated +final_tick 363611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 742759 # Simulator tick rate (ticks/s) +host_mem_usage 214372 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host +system.physmem.bytes_read 0 # Number of bytes read from this memory +system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 0 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini new file mode 100644 index 000000000..cc5b405b4 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -0,0 +1,275 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +buffer_size=0 +cntrl_id=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +cntrl_id=1 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=true +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + +[system.tester] +type=RubyTester +check_flush=false +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.l1_cntrl0.sequencer.port[0] + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..9cbc6e028 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -0,0 +1,1470 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 1 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:22:16 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.62 +Virtual_time_in_minutes: 0.0103333 +Virtual_time_in_hours: 0.000172222 +Virtual_time_in_days: 7.17593e-06 + +Ruby_current_time: 371241 +Ruby_start_time: 0 +Ruby_cycles: 371241 + +mbytes_resident: 39.6328 +mbytes_total: 209.516 +resident_ratio: 0.189164 + +ruby_cycles_executed: [ 371242 ] + +Busy Controller Counts: +L2Cache-0:0 +L1Cache-0:0 + +Directory-0:0 + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 993 average: 15.8197 | standard deviation: 1.13014 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 60 919 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 10451 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 80 + +Network Stats +------------- + +total_msg_count_Request_Control: 5209 41672 +total_msg_count_Response_Data: 5058 364176 +total_msg_count_ResponseL2hit_Data: 150 10800 +total_msg_count_Writeback_Data: 4929 354888 +total_msg_count_Writeback_Control: 10567 84536 +total_msg_count_Unblock_Control: 5193 41544 +total_msgs: 31106 total_bytes: 897616 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 2.51865 + links_utilized_percent_switch_0_link_0: 2.57016 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.46713 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 1802 14416 [ 888 836 78 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 1.31922 + links_utilized_percent_switch_1_link_0: 1.20205 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.4364 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 894 7152 [ 894 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 889 7112 [ 889 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.19949 + links_utilized_percent_switch_2_link_0: 1.26481 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 1.13417 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 834 6672 [ 0 834 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 1.67901 + links_utilized_percent_switch_3_link_0: 2.57016 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 1.20205 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 1.26481 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + + --- L1Cache --- + - Event Counts - +Load [50 ] 50 +Ifetch [304 ] 304 +Store [970 ] 970 +L1_Replacement [527165 ] 527165 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [893 ] 893 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [888 ] 888 +Writeback_Nack [0 ] 0 +All_acks [799 ] 799 +Use_Timeout [890 ] 890 + + - Transitions - +I Load [45 ] 45 +I Ifetch [49 ] 49 +I Store [800 ] 800 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [0 ] 0 +M Ifetch [1 ] 1 +M Store [0 ] 0 +M L1_Replacement [91 ] 91 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L1_Replacement [1727 ] 1727 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [92 ] 92 + +MM Load [5 ] 5 +MM Ifetch [0 ] 0 +MM Store [70 ] 70 +MM L1_Replacement [798 ] 798 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [11 ] 11 +MM_W L1_Replacement [29093 ] 29093 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [798 ] 798 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [453807 ] 453807 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [799 ] 799 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [14583 ] 14583 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [799 ] 799 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [27066 ] 27066 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [94 ] 94 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [254 ] 254 +MI Store [89 ] 89 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [888 ] 888 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- + - Event Counts - +L1_GETS [157 ] 157 +L1_GETX [842 ] 842 +L1_PUTO [0 ] 0 +L1_PUTX [2111 ] 2111 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [759 ] 759 +Data [759 ] 759 +Data_Exclusive [84 ] 84 +L1_WBCLEANDATA [82 ] 82 +L1_WBDIRTYDATA [806 ] 806 +Writeback_Ack [833 ] 833 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [890 ] 890 +DmaAck [0 ] 0 +L2_Replacement [836 ] 836 + + - Transitions - +NP L1_GETS [84 ] 84 +NP L1_GETX [759 ] 759 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [888 ] 888 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [10 ] 10 +M L1_GETX [40 ] 40 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [836 ] 836 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [63 ] 63 +ILXW L1_GETX [23 ] 23 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [82 ] 82 +ILXW L1_WBDIRTYDATA [806 ] 806 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [99 ] 99 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [84 ] 84 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [83 ] 83 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [759 ] 759 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [1113 ] 1113 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [759 ] 759 +IGMO Exclusive_Unblock [758 ] 758 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [11 ] 11 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [40 ] 40 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [9 ] 9 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [20 ] 20 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [833 ] 833 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +ILOSD L1_GETS [0 ] 0 +ILOSD L1_GETX [0 ] 0 +ILOSD L1_PUTO [0 ] 0 +ILOSD L1_PUTX [0 ] 0 +ILOSD L1_PUTS_only [0 ] 0 +ILOSD L1_PUTS [0 ] 0 +ILOSD Fwd_GETX [0 ] 0 +ILOSD Fwd_GETS [0 ] 0 +ILOSD Fwd_DMA [0 ] 0 +ILOSD Own_GETX [0 ] 0 +ILOSD Inv [0 ] 0 +ILOSD DmaAck [0 ] 0 +ILOSD L2_Replacement [0 ] 0 + +ILOSXD L1_GETS [0 ] 0 +ILOSXD L1_GETX [0 ] 0 +ILOSXD L1_PUTO [0 ] 0 +ILOSXD L1_PUTX [0 ] 0 +ILOSXD L1_PUTS_only [0 ] 0 +ILOSXD L1_PUTS [0 ] 0 +ILOSXD Fwd_GETX [0 ] 0 +ILOSXD Fwd_GETS [0 ] 0 +ILOSXD Fwd_DMA [0 ] 0 +ILOSXD Own_GETX [0 ] 0 +ILOSXD Inv [0 ] 0 +ILOSXD DmaAck [0 ] 0 +ILOSXD L2_Replacement [0 ] 0 + +ILOD L1_GETS [0 ] 0 +ILOD L1_GETX [0 ] 0 +ILOD L1_PUTO [0 ] 0 +ILOD L1_PUTX [0 ] 0 +ILOD L1_PUTS_only [0 ] 0 +ILOD L1_PUTS [0 ] 0 +ILOD Fwd_GETX [0 ] 0 +ILOD Fwd_GETS [0 ] 0 +ILOD Fwd_DMA [0 ] 0 +ILOD Own_GETX [0 ] 0 +ILOD Inv [0 ] 0 +ILOD DmaAck [0 ] 0 +ILOD L2_Replacement [0 ] 0 + +ILXD L1_GETS [0 ] 0 +ILXD L1_GETX [0 ] 0 +ILXD L1_PUTO [0 ] 0 +ILXD L1_PUTX [0 ] 0 +ILXD L1_PUTS_only [0 ] 0 +ILXD L1_PUTS [0 ] 0 +ILXD Fwd_GETX [0 ] 0 +ILXD Fwd_GETS [0 ] 0 +ILXD Fwd_DMA [0 ] 0 +ILXD Own_GETX [0 ] 0 +ILXD Inv [0 ] 0 +ILXD DmaAck [0 ] 0 +ILXD L2_Replacement [0 ] 0 + +ILOXD L1_GETS [0 ] 0 +ILOXD L1_GETX [0 ] 0 +ILOXD L1_PUTO [0 ] 0 +ILOXD L1_PUTX [0 ] 0 +ILOXD L1_PUTS_only [0 ] 0 +ILOXD L1_PUTS [0 ] 0 +ILOXD Fwd_GETX [0 ] 0 +ILOXD Fwd_GETS [0 ] 0 +ILOXD Fwd_DMA [0 ] 0 +ILOXD Own_GETX [0 ] 0 +ILOXD Inv [0 ] 0 +ILOXD DmaAck [0 ] 0 +ILOXD L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1598 + memory_reads: 843 + memory_writes: 755 + memory_refreshes: 774 + memory_total_request_delays: 711 + memory_delays_per_request: 0.444931 + memory_delays_in_input_queue: 99 + memory_delays_behind_head_of_bank_queue: 1 + memory_delays_stalled_at_head_of_bank_queue: 611 + memory_stalls_for_bank_busy: 192 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 42 + memory_stalls_for_bus: 230 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 69 + memory_stalls_for_read_read_turnaround: 78 + accesses_per_bank: 55 50 42 77 67 66 60 47 44 55 47 36 56 64 44 42 45 36 61 44 58 41 44 55 46 43 43 50 49 41 48 42 + + --- Directory --- + - Event Counts - +GETX [761 ] 761 +GETS [84 ] 84 +PUTX [834 ] 834 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [841 ] 841 +Clean_Writeback [78 ] 78 +Dirty_Writeback [755 ] 755 +Memory_Data [843 ] 843 +Memory_Ack [754 ] 754 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_ACK [0 ] 0 +Data [0 ] 0 + + - Transitions - +I GETX [759 ] 759 +I GETS [84 ] 84 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [750 ] 750 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [834 ] 834 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [83 ] 83 +IS Memory_Data [84 ] 84 +IS Memory_Ack [1 ] 1 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [758 ] 758 +MM Memory_Data [759 ] 759 +MM Memory_Ack [3 ] 3 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [2 ] 2 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [78 ] 78 +MI Dirty_Writeback [755 ] 755 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data [0 ] 0 + +OD GETX [0 ] 0 +OD GETS [0 ] 0 +OD PUTX [0 ] 0 +OD PUTO [0 ] 0 +OD PUTO_SHARERS [0 ] 0 +OD DMA_READ [0 ] 0 +OD DMA_WRITE [0 ] 0 +OD DMA_ACK [0 ] 0 + +MD GETX [0 ] 0 +MD GETS [0 ] 0 +MD PUTX [0 ] 0 +MD PUTO [0 ] 0 +MD PUTO_SHARERS [0 ] 0 +MD DMA_READ [0 ] 0 +MD DMA_WRITE [0 ] 0 +MD DMA_ACK [0 ] 0 + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr new file mode 100755 index 000000000..cfdf73ce9 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr @@ -0,0 +1 @@ +hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout new file mode 100755 index 000000000..dfaf3cf5d --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:47:36 +gem5 started Jan 23 2012 04:22:16 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 371241 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt new file mode 100644 index 000000000..59e160c20 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -0,0 +1,17 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000371 # Number of seconds simulated +sim_ticks 371241 # Number of ticks simulated +final_tick 371241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 812201 # Simulator tick rate (ticks/s) +host_mem_usage 214548 # Number of bytes of host memory used +host_seconds 0.46 # Real time elapsed on the host +system.physmem.bytes_read 0 # Number of bytes read from this memory +system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 0 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini new file mode 100644 index 000000000..753a30469 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -0,0 +1,286 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +N_tokens=2 +buffer_size=0 +cntrl_id=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +cntrl_id=1 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=true +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + +[system.tester] +type=RubyTester +check_flush=false +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.l1_cntrl0.sequencer.port[0] + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats new file mode 100644 index 000000000..ef66b37d5 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -0,0 +1,1049 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 1 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:22:32 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 + +Ruby_current_time: 254811 +Ruby_start_time: 0 +Ruby_cycles: 254811 + +mbytes_resident: 39.6562 +mbytes_total: 209.445 +resident_ratio: 0.189339 + +ruby_cycles_executed: [ 254812 ] + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 968 average: 15.8223 | standard deviation: 1.1424 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 901 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 64 max: 6786 count: 953 average: 4217 | standard deviation: 1907.02 | 76 12 1 4 2 6 12 15 5 9 2 8 6 3 1 0 1 2 3 0 0 0 3 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 7 8 5 15 14 23 19 28 37 33 34 37 54 51 30 34 31 30 25 32 21 23 24 23 23 15 17 15 6 6 8 9 3 6 5 4 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 6374 count: 48 average: 4227.06 | standard deviation: 2103.17 | 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 2 0 0 0 2 3 1 0 1 1 0 4 0 1 0 0 1 0 1 2 0 0 1 0 0 1 1 0 0 0 1 1 0 2 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 64 max: 6786 count: 853 average: 4438.8 | standard deviation: 1719.13 | 68 11 0 2 1 3 3 6 0 2 1 3 1 1 1 0 0 2 3 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 6 7 5 15 14 21 19 27 36 32 31 37 52 47 29 33 27 29 24 31 19 22 24 21 23 14 16 12 6 6 6 8 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1410 count: 52 average: 569.423 | standard deviation: 218.615 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 3 1 2 2 0 0 1 0 0 1 1 2 0 2 3 2 0 1 1 0 0 1 0 0 1 1 1 1 2 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 116 count: 88 average: 17.0114 | standard deviation: 36.8762 | 0 22 14 23 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 2 1 0 1 1 1 0 1 1 ] +miss_latency_L2Cache: [binsize: 32 max: 6374 count: 41 average: 3115.78 | standard deviation: 2260.77 | 0 0 0 0 0 0 0 2 0 1 2 1 0 1 4 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 2 0 1 0 0 3 1 0 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 ] +miss_latency_Directory: [binsize: 64 max: 6786 count: 824 average: 4720.34 | standard deviation: 1325.89 | 0 0 1 2 1 3 11 11 5 8 0 8 5 2 1 0 1 2 2 0 0 0 3 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 6 8 4 14 14 21 19 27 35 32 31 36 52 48 30 33 31 30 25 32 21 23 23 23 23 15 16 15 6 5 8 8 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 824 +miss_latency_LD_L1Cache: [binsize: 1 max: 111 count: 9 average: 14.2222 | standard deviation: 36.3043 | 0 3 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L2Cache: [binsize: 32 max: 6374 count: 2 average: 5575 | standard deviation: 1129.96 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 6097 count: 37 average: 5178.95 | standard deviation: 519.569 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 2 3 1 0 1 1 0 4 0 1 0 0 1 0 1 2 0 0 1 0 0 1 1 0 0 0 1 1 0 2 1 0 0 0 0 1 1 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 79 average: 17.3291 | standard deviation: 37.1563 | 0 19 13 19 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 2 1 0 0 1 1 0 1 1 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 6128 count: 33 average: 3448.85 | standard deviation: 2129.45 | 0 0 0 0 0 0 0 1 0 1 1 1 0 1 2 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 2 0 1 0 0 2 1 0 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ] +miss_latency_ST_Directory: [binsize: 64 max: 6786 count: 741 average: 4954.27 | standard deviation: 899.825 | 0 0 0 1 0 1 2 4 0 2 0 3 0 0 1 0 0 2 2 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 5 7 4 14 14 19 19 26 34 31 29 36 50 44 29 32 27 29 24 31 19 22 23 21 23 14 15 12 6 5 6 7 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L2Cache: [binsize: 4 max: 669 count: 6 average: 464.167 | standard deviation: 153.369 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1410 count: 46 average: 583.152 | standard deviation: 223.341 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 3 1 2 2 0 0 1 0 0 0 0 2 0 2 3 2 0 1 1 0 0 1 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 10441 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 80 + +Network Stats +------------- + +total_msg_count_Request_Control: 5091 40728 +total_msg_count_Response_Data: 2586 186192 +total_msg_count_ResponseL2hit_Data: 120 8640 +total_msg_count_Response_Control: 9 72 +total_msg_count_Writeback_Data: 4998 359856 +total_msg_count_Writeback_Control: 210 1680 +total_msg_count_Persistent_Control: 2100 16800 +total_msgs: 15114 total_bytes: 613968 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 1.82645 + links_utilized_percent_switch_0_link_0: 1.74522 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 1.90769 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 844 60768 [ 0 0 0 0 844 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 65 4680 [ 0 0 0 0 65 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 927 66744 [ 0 0 0 0 927 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 1.66584 + links_utilized_percent_switch_1_link_0: 1.76111 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.57058 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 862 62064 [ 0 0 0 0 862 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 732 52704 [ 0 0 0 0 732 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.5275 + links_utilized_percent_switch_2_link_0: 1.58215 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 1.47286 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 827 59544 [ 0 0 0 0 827 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 1.67327 + links_utilized_percent_switch_3_link_0: 1.67654 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 1.76111 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 1.58215 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 844 60768 [ 0 0 0 0 844 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 65 4680 [ 0 0 0 0 65 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 862 62064 [ 0 0 0 0 862 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 52 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 52 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 52 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 815 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 815 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.78528% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.2147% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 815 100% + + --- L1Cache --- + - Event Counts - +Load [48 ] 48 +Ifetch [52 ] 52 +Store [855 ] 855 +Atomic [0 ] 0 +L1_Replacement [18483 ] 18483 +Data_Shared [8 ] 8 +Data_Owner [3 ] 3 +Data_All_Tokens [937 ] 937 +Ack [0 ] 0 +Ack_All_Tokens [3 ] 3 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [350 ] 350 +Request_Timeout [565 ] 565 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [856 ] 856 +Use_TimeoutNoStarvers_NoMig [0 ] 0 + + - Transitions - +NP Load [39 ] 39 +NP Ifetch [52 ] 52 +NP Store [776 ] 776 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [83 ] 83 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [168 ] 168 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S Atomic [0 ] 0 +S L1_Replacement [8 ] 8 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M Load [0 ] 0 +M Ifetch [0 ] 0 +M Store [0 ] 0 +M Atomic [0 ] 0 +M L1_Replacement [80 ] 80 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [14 ] 14 + +MM Load [9 ] 9 +MM Ifetch [0 ] 0 +MM Store [68 ] 68 +MM Atomic [0 ] 0 +MM L1_Replacement [774 ] 774 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [17 ] 17 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [1 ] 1 +M_W Atomic [0 ] 0 +M_W L1_Replacement [353 ] 353 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [3 ] 3 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [81 ] 81 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [10 ] 10 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [7103 ] 7103 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [22 ] 22 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [775 ] 775 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [9674 ] 9674 +IM Data_Shared [0 ] 0 +IM Data_Owner [3 ] 3 +IM Data_All_Tokens [771 ] 771 +IM Ack [0 ] 0 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [104 ] 104 +IM Request_Timeout [466 ] 466 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [0 ] 0 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [3 ] 3 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [3 ] 3 +OM Request_Timeout [24 ] 24 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [491 ] 491 +IS Data_Shared [8 ] 8 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [83 ] 83 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [19 ] 19 +IS Request_Timeout [75 ] 75 + +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 + +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 + +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 830 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 830 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 830 100% + + --- L2Cache --- + - Event Counts - +L1_GETS [91 ] 91 +L1_GETS_Last_Token [0 ] 0 +L1_GETX [776 ] 776 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [762 ] 762 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [4 ] 4 +Writeback_All_Tokens [858 ] 858 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [152 ] 152 +Persistent_GETS [23 ] 23 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [175 ] 175 + + - Transitions - +NP L1_GETS [83 ] 83 +NP L1_GETX [744 ] 744 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [0 ] 0 +NP Writeback_All_Tokens [766 ] 766 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [154 ] 154 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [18 ] 18 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [3 ] 3 +I Writeback_All_Tokens [30 ] 30 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [1 ] 1 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [0 ] 0 +S L1_GETX [0 ] 0 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [0 ] 0 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [3 ] 3 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [1 ] 1 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [3 ] 3 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [0 ] 0 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [1 ] 1 +O Writeback_All_Tokens [4 ] 4 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [7 ] 7 +M L1_GETX [29 ] 29 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [744 ] 744 +M Persistent_GETX [15 ] 15 +M Persistent_GETS [2 ] 2 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [58 ] 58 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [133 ] 133 +I_L Persistent_GETS [21 ] 21 +I_L Own_Lock_or_Unlock [21 ] 21 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1574 + memory_reads: 826 + memory_writes: 748 + memory_refreshes: 531 + memory_total_request_delays: 1037 + memory_delays_per_request: 0.658831 + memory_delays_in_input_queue: 141 + memory_delays_behind_head_of_bank_queue: 2 + memory_delays_stalled_at_head_of_bank_queue: 894 + memory_stalls_for_bank_busy: 217 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 83 + memory_stalls_for_bus: 353 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 169 + memory_stalls_for_read_read_turnaround: 72 + accesses_per_bank: 45 29 60 82 68 54 61 51 42 44 37 39 45 54 39 49 42 55 46 41 46 48 53 59 44 62 49 35 51 49 60 35 + + --- Directory --- + - Event Counts - +GETX [768 ] 768 +GETS [83 ] 83 +Lockdown [175 ] 175 +Unlockdown [175 ] 175 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [757 ] 757 +Ack_Owner [0 ] 0 +Ack_Owner_All_Tokens [70 ] 70 +Tokens [0 ] 0 +Ack_All_Tokens [0 ] 0 +Request_Timeout [0 ] 0 +Memory_Data [825 ] 825 +Memory_Ack [748 ] 748 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 + + - Transitions - +O GETX [739 ] 739 +O GETS [83 ] 83 +O Lockdown [4 ] 4 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [6 ] 6 +NO GETS [0 ] 0 +NO Lockdown [159 ] 159 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [0 ] 0 +NO Data_All_Tokens [748 ] 748 +NO Ack_Owner [0 ] 0 +NO Ack_Owner_All_Tokens [70 ] 70 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [2 ] 2 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [173 ] 173 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [9 ] 9 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [2 ] 2 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [748 ] 748 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [21 ] 21 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [2 ] 2 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [4 ] 4 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [10 ] 10 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [10 ] 10 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [811 ] 811 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens [0 ] 0 + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr new file mode 100755 index 000000000..cfdf73ce9 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr @@ -0,0 +1 @@ +hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout new file mode 100755 index 000000000..151753306 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:50:16 +gem5 started Jan 23 2012 04:22:31 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 254811 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt new file mode 100644 index 000000000..35d3a3293 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -0,0 +1,17 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000255 # Number of seconds simulated +sim_ticks 254811 # Number of ticks simulated +final_tick 254811 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 1986774 # Simulator tick rate (ticks/s) +host_mem_usage 214476 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +system.physmem.bytes_read 0 # Number of bytes read from this memory +system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 0 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini new file mode 100644 index 000000000..3ae5a9266 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -0,0 +1,254 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +cntrl_id=1 +directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +is_icache=false +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +cntrl_id=0 +issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=true +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=true +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + +[system.tester] +type=RubyTester +check_flush=false +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.l1_cntrl0.sequencer.port[0] + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats new file mode 100644 index 000000000..2e775c964 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -0,0 +1,972 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 1 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, unordered +virtual_net_3: active, unordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:21:49 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.25 +Virtual_time_in_minutes: 0.00416667 +Virtual_time_in_hours: 6.94444e-05 +Virtual_time_in_days: 2.89352e-06 + +Ruby_current_time: 213131 +Ruby_start_time: 0 +Ruby_cycles: 213131 + +mbytes_resident: 39.2617 +mbytes_total: 209.207 +resident_ratio: 0.187669 + +ruby_cycles_executed: [ 213132 ] + +Busy Controller Counts: +L1Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.7883 | standard deviation: 1.14907 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 82 879 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 64 max: 6858 count: 963 average: 3505.41 | standard deviation: 1666 | 67 16 4 2 10 5 22 17 6 9 5 8 4 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 9 13 24 17 17 29 22 26 32 30 39 37 41 29 39 32 34 28 34 30 27 28 19 18 10 3 7 12 5 7 7 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 6253 count: 51 average: 3926.14 | standard deviation: 1480.7 | 3 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 64 max: 6858 count: 863 average: 3652.34 | standard deviation: 1553.9 | 60 13 3 2 7 3 9 13 1 7 0 4 1 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 8 13 21 16 16 26 21 25 32 30 37 35 38 27 38 28 33 28 33 28 23 25 18 18 9 1 7 10 5 7 7 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1022 count: 49 average: 479.796 | standard deviation: 243.565 | 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 114 count: 72 average: 17.4167 | standard deviation: 35.9832 | 0 9 9 12 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 1 2 0 0 1 0 0 0 1 ] +miss_latency_L2Cache: [binsize: 32 max: 5339 count: 41 average: 2283.05 | standard deviation: 1908.79 | 5 0 0 6 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Directory: [binsize: 64 max: 6858 count: 850 average: 3859.83 | standard deviation: 1320.43 | 0 0 4 0 10 4 22 15 6 8 5 8 3 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 9 12 23 17 15 27 21 25 31 29 38 35 41 29 39 32 33 28 32 30 27 28 19 18 9 3 7 12 5 7 6 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 850 +miss_latency_LD_L1Cache: [binsize: 1 max: 103 count: 4 average: 27.75 | standard deviation: 50.183 | 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 6253 count: 47 average: 4257.91 | standard deviation: 974.148 | 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 114 count: 66 average: 17.197 | standard deviation: 35.8598 | 0 8 9 11 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 2 0 0 1 0 0 0 1 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 5339 count: 37 average: 2523.57 | standard deviation: 1854.34 | 3 0 0 4 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_Directory: [binsize: 64 max: 6858 count: 760 average: 4022.97 | standard deviation: 1109.22 | 0 0 3 0 7 2 9 11 1 6 0 4 0 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 8 12 20 16 14 24 20 24 31 29 36 33 38 27 38 28 32 28 31 28 23 25 18 18 8 1 7 10 5 7 6 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 2 average: 4 | standard deviation: 0 | 0 0 0 0 2 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 112 count: 4 average: 58.25 | standard deviation: 60.9289 | 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1022 count: 43 average: 541.14 | standard deviation: 189.677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 10363 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 80 + +Network Stats +------------- + +total_msg_count_Request_Control: 2553 20424 +total_msg_count_Response_Data: 2550 183600 +total_msg_count_Writeback_Data: 2292 165024 +total_msg_count_Writeback_Control: 5291 42328 +total_msg_count_Unblock_Control: 2546 20368 +total_msgs: 15232 total_bytes: 431744 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 2.11044 + links_utilized_percent_switch_0_link_0: 1.9922 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.22868 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 0 0 845 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 2.10985 + links_utilized_percent_switch_1_link_0: 2.2275 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.9922 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 850 6800 [ 0 0 850 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 848 6784 [ 0 0 0 0 0 848 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 2.11009 + links_utilized_percent_switch_2_link_0: 1.9922 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.22797 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 47 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 846 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 846 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 846 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 893 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 893 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.26316% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.4737% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.26316% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 893 100% + + --- L1Cache --- + - Event Counts - +Load [51 ] 51 +Ifetch [52 ] 52 +Store [889 ] 889 +L2_Replacement [845 ] 845 +L1_to_L2 [15901 ] 15901 +Trigger_L2_to_L1D [37 ] 37 +Trigger_L2_to_L1I [4 ] 4 +Complete_L2_to_L1 [41 ] 41 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [850 ] 850 +Writeback_Ack [842 ] 842 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [850 ] 850 +Flush_line [0 ] 0 +Block_Ack [0 ] 0 + + - Transitions - +I Load [47 ] 47 +I Ifetch [43 ] 43 +I Store [762 ] 762 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 +I Invalidate [0 ] 0 +I Flush_line [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 +S Invalidate [0 ] 0 +S Flush_line [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 +O Invalidate [0 ] 0 +O Flush_line [0 ] 0 + +M Load [0 ] 0 +M Ifetch [1 ] 1 +M Store [0 ] 0 +M L2_Replacement [79 ] 79 +M L1_to_L2 [88 ] 88 +M Trigger_L2_to_L1D [9 ] 9 +M Trigger_L2_to_L1I [0 ] 0 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 +M Invalidate [0 ] 0 +M Flush_line [0 ] 0 + +MM Load [4 ] 4 +MM Ifetch [1 ] 1 +MM Store [65 ] 65 +MM L2_Replacement [766 ] 766 +MM L1_to_L2 [800 ] 800 +MM Trigger_L2_to_L1D [28 ] 28 +MM Trigger_L2_to_L1I [4 ] 4 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 +MM Invalidate [0 ] 0 +MM Flush_line [0 ] 0 + +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [0 ] 0 +MR Ifetch [0 ] 0 +MR Store [9 ] 9 +MR L1_to_L2 [43 ] 43 +MR Flush_line [0 ] 0 + +MMR Load [0 ] 0 +MMR Ifetch [4 ] 4 +MMR Store [28 ] 28 +MMR L1_to_L2 [78 ] 78 +MMR Flush_line [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [9451 ] 9451 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [760 ] 760 +IM Flush_line [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 +SM Flush_line [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 +OM Flush_line [0 ] 0 + +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 +ISM Flush_line [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [239 ] 239 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [90 ] 90 +M_W Flush_line [0 ] 0 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [1 ] 1 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [4486 ] 4486 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [760 ] 760 +MM_W Flush_line [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [611 ] 611 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [90 ] 90 +IS Flush_line [0 ] 0 + +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 +SS Flush_line [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Flush_line [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [1 ] 1 +MI Store [2 ] 2 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [842 ] 842 +MI Flush_line [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 +II Flush_line [0 ] 0 + +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [3 ] 3 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [81 ] 81 +MT Complete_L2_to_L1 [9 ] 9 + +MMT Load [0 ] 0 +MMT Ifetch [2 ] 2 +MMT Store [19 ] 19 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [24 ] 24 +MMT Complete_L2_to_L1 [32 ] 32 + +MI_F Load [0 ] 0 +MI_F Ifetch [0 ] 0 +MI_F Store [0 ] 0 +MI_F L1_to_L2 [0 ] 0 +MI_F Writeback_Ack [0 ] 0 +MI_F Flush_line [0 ] 0 + +MM_F Load [0 ] 0 +MM_F Ifetch [0 ] 0 +MM_F Store [0 ] 0 +MM_F L1_to_L2 [0 ] 0 +MM_F Other_GETX [0 ] 0 +MM_F Other_GETS [0 ] 0 +MM_F Merged_GETS [0 ] 0 +MM_F Other_GETS_No_Mig [0 ] 0 +MM_F NC_DMA_GETS [0 ] 0 +MM_F Invalidate [0 ] 0 +MM_F Ack [0 ] 0 +MM_F All_acks [0 ] 0 +MM_F All_acks_no_sharers [0 ] 0 +MM_F Flush_line [0 ] 0 +MM_F Block_Ack [0 ] 0 + +IM_F Load [0 ] 0 +IM_F Ifetch [0 ] 0 +IM_F Store [0 ] 0 +IM_F L2_Replacement [0 ] 0 +IM_F L1_to_L2 [0 ] 0 +IM_F Other_GETX [0 ] 0 +IM_F Other_GETS [0 ] 0 +IM_F Other_GETS_No_Mig [0 ] 0 +IM_F NC_DMA_GETS [0 ] 0 +IM_F Invalidate [0 ] 0 +IM_F Ack [0 ] 0 +IM_F Data [0 ] 0 +IM_F Exclusive_Data [0 ] 0 +IM_F Flush_line [0 ] 0 + +ISM_F Load [0 ] 0 +ISM_F Ifetch [0 ] 0 +ISM_F Store [0 ] 0 +ISM_F L2_Replacement [0 ] 0 +ISM_F L1_to_L2 [0 ] 0 +ISM_F Ack [0 ] 0 +ISM_F All_acks_no_sharers [0 ] 0 +ISM_F Flush_line [0 ] 0 + +SM_F Load [0 ] 0 +SM_F Ifetch [0 ] 0 +SM_F Store [0 ] 0 +SM_F L2_Replacement [0 ] 0 +SM_F L1_to_L2 [0 ] 0 +SM_F Other_GETX [0 ] 0 +SM_F Other_GETS [0 ] 0 +SM_F Other_GETS_No_Mig [0 ] 0 +SM_F NC_DMA_GETS [0 ] 0 +SM_F Invalidate [0 ] 0 +SM_F Ack [0 ] 0 +SM_F Data [0 ] 0 +SM_F Exclusive_Data [0 ] 0 +SM_F Flush_line [0 ] 0 + +OM_F Load [0 ] 0 +OM_F Ifetch [0 ] 0 +OM_F Store [0 ] 0 +OM_F L2_Replacement [0 ] 0 +OM_F L1_to_L2 [0 ] 0 +OM_F Other_GETX [0 ] 0 +OM_F Other_GETS [0 ] 0 +OM_F Merged_GETS [0 ] 0 +OM_F Other_GETS_No_Mig [0 ] 0 +OM_F NC_DMA_GETS [0 ] 0 +OM_F Invalidate [0 ] 0 +OM_F Ack [0 ] 0 +OM_F All_acks [0 ] 0 +OM_F All_acks_no_sharers [0 ] 0 +OM_F Flush_line [0 ] 0 + +MM_WF Load [0 ] 0 +MM_WF Ifetch [0 ] 0 +MM_WF Store [0 ] 0 +MM_WF L2_Replacement [0 ] 0 +MM_WF L1_to_L2 [0 ] 0 +MM_WF Ack [0 ] 0 +MM_WF All_acks_no_sharers [0 ] 0 +MM_WF Flush_line [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1614 + memory_reads: 850 + memory_writes: 764 + memory_refreshes: 444 + memory_total_request_delays: 1136 + memory_delays_per_request: 0.703841 + memory_delays_in_input_queue: 148 + memory_delays_behind_head_of_bank_queue: 4 + memory_delays_stalled_at_head_of_bank_queue: 984 + memory_stalls_for_bank_busy: 278 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 71 + memory_stalls_for_bus: 363 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 151 + memory_stalls_for_read_read_turnaround: 121 + accesses_per_bank: 44 58 47 90 75 58 58 48 47 49 56 50 32 37 53 44 53 47 48 55 53 40 39 41 34 44 54 59 55 47 50 49 + + --- Directory --- + - Event Counts - +GETX [760 ] 760 +GETS [91 ] 91 +PUT [889 ] 889 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [848 ] 848 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [78 ] 78 +Writeback_Exclusive_Dirty [764 ] 764 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [850 ] 850 +Memory_Ack [763 ] 763 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 +GETF [0 ] 0 +PUTF [0 ] 0 + + - Transitions - +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 +NX GETF [0 ] 0 + +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [842 ] 842 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 +NO GETF [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 +S GETF [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O GETF [0 ] 0 + +E GETX [760 ] 760 +E GETS [90 ] 90 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 +E GETF [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 +O_R GETF [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 +S_R GETF [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 +NO_R GETF [0 ] 0 + +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [47 ] 47 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [848 ] 848 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 +NO_B GETF [0 ] 0 + +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 +NO_B_X GETF [0 ] 0 + +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 +NO_B_S GETF [0 ] 0 + +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 +NO_B_S_W GETF [0 ] 0 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 +O_B GETF [0 ] 0 + +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [850 ] 850 +NO_B_W GETF [0 ] 0 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 +O_B_W GETF [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 +NO_W GETF [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W GETF [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 +NO_DW_B_W GETF [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_W GETF [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B_D GETF [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B GETF [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 +NO_DW_W GETF [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 +O_DR_B_W GETF [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 +O_DR_B GETF [0 ] 0 + +WB GETX [0 ] 0 +WB GETS [1 ] 1 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [78 ] 78 +WB Writeback_Exclusive_Dirty [764 ] 764 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 +WB GETF [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 +WB_O_W GETF [0 ] 0 + +WB_E_W GETX [0 ] 0 +WB_E_W GETS [0 ] 0 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack [763 ] 763 +WB_E_W GETF [0 ] 0 + +NO_F GETX [0 ] 0 +NO_F GETS [0 ] 0 +NO_F PUT [0 ] 0 +NO_F UnblockM [0 ] 0 +NO_F Pf_Replacement [0 ] 0 +NO_F GETF [0 ] 0 +NO_F PUTF [0 ] 0 + +NO_F_W GETX [0 ] 0 +NO_F_W GETS [0 ] 0 +NO_F_W PUT [0 ] 0 +NO_F_W Pf_Replacement [0 ] 0 +NO_F_W DMA_READ [0 ] 0 +NO_F_W DMA_WRITE [0 ] 0 +NO_F_W Memory_Data [0 ] 0 +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr new file mode 100755 index 000000000..cfdf73ce9 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr @@ -0,0 +1 @@ +hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout new file mode 100755 index 000000000..959553323 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:42:19 +gem5 started Jan 23 2012 04:21:49 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 213131 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt new file mode 100644 index 000000000..e2e363d28 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -0,0 +1,17 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000213 # Number of seconds simulated +sim_ticks 213131 # Number of ticks simulated +final_tick 213131 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 2118201 # Simulator tick rate (ticks/s) +host_mem_usage 214232 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +system.physmem.bytes_read 0 # Number of bytes read from this memory +system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 0 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini new file mode 100644 index 000000000..e6be42bee --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -0,0 +1,220 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=1 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.cacheMemory +cache_response_latency=12 +cntrl_id=0 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=true +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + +[system.tester] +type=RubyTester +check_flush=false +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.l1_cntrl0.sequencer.port[0] + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats new file mode 100644 index 000000000..7421fe4ce --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -0,0 +1,311 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 1 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, ordered +virtual_net_3: active, ordered +virtual_net_4: active, ordered +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:59:28 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.22 +Virtual_time_in_minutes: 0.00366667 +Virtual_time_in_hours: 6.11111e-05 +Virtual_time_in_days: 2.5463e-06 + +Ruby_current_time: 277351 +Ruby_start_time: 0 +Ruby_cycles: 277351 + +mbytes_resident: 38.8945 +mbytes_total: 208.887 +resident_ratio: 0.186199 + +ruby_cycles_executed: [ 277352 ] + +Busy Controller Counts: +L1Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 997 average: 15.7763 | standard deviation: 1.14597 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 8 90 886 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 32 max: 6224 count: 983 average: 4476.87 | standard deviation: 570.324 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 2 0 2 3 0 2 1 4 3 2 4 9 5 6 7 2 0 12 12 1 15 9 13 19 15 17 26 15 14 15 22 15 27 26 24 26 29 18 22 28 28 18 36 21 21 25 22 24 27 21 26 29 13 19 18 6 19 19 15 12 5 10 11 10 8 5 7 4 4 3 0 2 0 0 0 2 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 32 max: 5442 count: 42 average: 4462.83 | standard deviation: 536.15 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 3 0 1 0 1 1 0 2 1 0 0 0 0 3 1 4 1 0 0 1 0 0 2 1 4 1 0 0 0 0 2 0 0 2 0 0 0 0 1 0 0 1 2 0 0 0 1 1 0 1 ] +miss_latency_ST: [binsize: 32 max: 6224 count: 883 average: 4472.62 | standard deviation: 577.868 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 2 0 1 3 0 2 0 4 2 1 4 9 5 4 7 2 0 11 10 1 12 9 11 19 14 15 26 13 11 15 21 14 24 23 21 19 28 17 20 26 28 18 29 20 17 21 21 19 24 19 24 24 12 17 15 6 18 18 14 11 5 9 8 10 8 4 6 3 4 2 0 2 0 0 0 2 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 32 max: 5789 count: 58 average: 4551.81 | standard deviation: 472.973 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 2 0 1 1 3 0 2 3 0 1 2 1 0 0 5 0 0 3 1 5 3 2 0 5 1 0 3 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 32 max: 5122 count: 40 average: 3916 | standard deviation: 434.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 1 0 2 0 0 1 2 0 3 1 1 0 1 1 0 0 0 2 3 3 2 3 0 1 1 0 0 0 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ] +miss_latency_Directory: [binsize: 32 max: 6224 count: 943 average: 4500.67 | standard deviation: 563.316 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 2 2 0 1 1 2 3 2 3 7 5 3 6 1 0 11 11 1 15 9 11 16 12 15 23 15 13 14 22 15 27 24 23 25 27 18 22 28 28 18 36 21 21 25 22 24 27 21 26 29 13 18 18 6 19 19 15 11 5 10 11 10 8 5 7 4 4 3 0 2 0 0 0 2 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 943 +miss_latency_LD_L1Cache: [binsize: 16 max: 3058 count: 1 average: 3058 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 5442 count: 41 average: 4497.1 | standard deviation: 494.066 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 3 0 1 0 1 1 0 2 1 0 0 0 0 3 1 4 1 0 0 1 0 0 2 1 4 1 0 0 0 0 2 0 0 2 0 0 0 0 1 0 0 1 2 0 0 0 1 1 0 1 ] +miss_latency_ST_L1Cache: [binsize: 32 max: 5122 count: 38 average: 3945.16 | standard deviation: 420.627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 0 0 1 2 0 2 1 1 0 1 1 0 0 0 2 3 3 2 3 0 1 1 0 0 0 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ] +miss_latency_ST_Directory: [binsize: 32 max: 6224 count: 845 average: 4496.34 | standard deviation: 572.818 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 2 0 1 0 2 2 1 3 7 5 2 6 1 0 10 9 1 12 9 9 16 11 13 23 13 10 14 21 14 24 21 20 18 26 17 20 26 28 18 29 20 17 21 21 19 24 19 24 24 12 16 15 6 18 18 14 10 5 9 8 10 8 4 6 3 4 2 0 2 0 0 0 2 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3666 count: 1 average: 3666 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 32 max: 5789 count: 57 average: 4567.35 | standard deviation: 461.996 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 2 0 1 1 3 0 2 3 0 1 2 1 0 0 5 0 0 3 1 5 3 2 0 5 1 0 3 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 8 count: 1883 average: 0.143919 | standard deviation: 0.683804 | 1778 27 30 26 12 5 3 1 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 8 count: 1883 average: 0.143919 | standard deviation: 0.683804 | 1778 27 30 26 12 5 3 1 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 6 count: 943 average: 0.19088 | standard deviation: 0.752914 | 867 25 22 15 7 4 3 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 940 average: 0.0968085 | standard deviation: 0.604386 | 911 2 8 11 5 1 0 1 1 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 10335 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 72 + +Network Stats +------------- + +total_msg_count_Control: 2829 22632 +total_msg_count_Data: 2820 203040 +total_msg_count_Response_Data: 2829 203688 +total_msg_count_Writeback_Control: 2820 22560 +total_msgs: 11298 total_bytes: 451920 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 1.69731 + links_utilized_percent_switch_0_link_0: 1.69947 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 1.69514 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 1.69731 + links_utilized_percent_switch_1_link_0: 1.69514 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.69947 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.69731 + links_utilized_percent_switch_2_link_0: 1.69947 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 1.69514 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 945 + system.l1_cntrl0.cacheMemory_total_demand_misses: 945 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.cacheMemory_request_type_LD: 4.33862% + system.l1_cntrl0.cacheMemory_request_type_ST: 89.5238% + system.l1_cntrl0.cacheMemory_request_type_IFETCH: 6.13757% + + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 945 100% + + --- L1Cache --- + - Event Counts - +Load [42 ] 42 +Ifetch [59 ] 59 +Store [884 ] 884 +Data [943 ] 943 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [942 ] 942 +Writeback_Ack [940 ] 940 +Writeback_Nack [0 ] 0 + + - Transitions - +I Load [41 ] 41 +I Ifetch [58 ] 58 +I Store [846 ] 846 +I Inv [0 ] 0 +I Replacement [0 ] 0 + +II Writeback_Nack [0 ] 0 + +M Load [1 ] 1 +M Ifetch [1 ] 1 +M Store [38 ] 38 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [942 ] 942 + +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [940 ] 940 +MI Writeback_Nack [0 ] 0 + +MII Fwd_GETX [0 ] 0 + +IS Data [98 ] 98 + +IM Data [845 ] 845 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1883 + memory_reads: 943 + memory_writes: 940 + memory_refreshes: 578 + memory_total_request_delays: 2832 + memory_delays_per_request: 1.50398 + memory_delays_in_input_queue: 707 + memory_delays_behind_head_of_bank_queue: 5 + memory_delays_stalled_at_head_of_bank_queue: 2120 + memory_stalls_for_bank_busy: 238 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 276 + memory_stalls_for_bus: 930 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 552 + memory_stalls_for_read_read_turnaround: 124 + accesses_per_bank: 58 56 64 106 113 56 57 46 52 52 46 52 62 66 52 50 52 62 56 50 76 64 47 60 68 62 44 56 48 58 48 44 + + --- Directory --- + - Event Counts - +GETX [943 ] 943 +GETS [0 ] 0 +PUTX [940 ] 940 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [943 ] 943 +Memory_Ack [940 ] 940 + + - Transitions - +I GETX [943 ] 943 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [940 ] 940 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [943 ] 943 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [940 ] 940 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack [0 ] 0 + diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr new file mode 100755 index 000000000..cfdf73ce9 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr @@ -0,0 +1 @@ +hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout new file mode 100755 index 000000000..c0a210974 --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:59:28 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 277351 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt new file mode 100644 index 000000000..22332d2ed --- /dev/null +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -0,0 +1,17 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000277 # Number of seconds simulated +sim_ticks 277351 # Number of ticks simulated +final_tick 277351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 3834985 # Simulator tick rate (ticks/s) +host_mem_usage 213904 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +system.physmem.bytes_read 0 # Number of bytes read from this memory +system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 0 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory + +---------- End Simulation Statistics ---------- -- cgit v1.2.3