From f3585c841e964c98911784a187fc4f081a02a0a6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:33 -0600 Subject: stats: update stats for cache occupancy and clock domain changes --- tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout') diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index efa3fa542..ccbd2154c 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:53:51 -gem5 started Sep 22 2013 05:53:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:54:17 +gem5 started Jan 22 2014 17:29:05 +gem5 executing on u200540-lin command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -- cgit v1.2.3