From 85997e66a08b71d701e5b41462d1cfd42660b0c7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 6 Jun 2016 17:16:44 +0100 Subject: stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee --- .../se/70.twolf/ref/arm/linux/simple-atomic/stats.txt | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'tests/quick/se/70.twolf/ref/arm/linux/simple-atomic') diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 5f1cdd65c..a504e35f9 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2176341 # Simulator instruction rate (inst/s) -host_op_rate 2294214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1257887009 # Simulator tick rate (ticks/s) -host_mem_usage 304976 # Number of bytes of host memory used -host_seconds 79.18 # Real time elapsed on the host +host_inst_rate 2111044 # Simulator instruction rate (inst/s) +host_op_rate 2225381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220146763 # Simulator tick rate (ticks/s) +host_mem_usage 306656 # Number of bytes of host memory used +host_seconds 81.63 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 454362792 # Wr system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 199192984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 217614903 # Transaction distribution system.membus.trans_dist::ReadResp 217637310 # Transaction distribution system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -- cgit v1.2.3