From 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce Mon Sep 17 00:00:00 2001
From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Tue, 31 May 2016 11:07:18 +0100
Subject: stats: update for snoop filter tweak

--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
---
 .../ref/alpha/linux/minor-timing/stats.txt         |   10 +-
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   |   10 +-
 .../ref/alpha/linux/simple-atomic/stats.txt        |   10 +-
 .../simple-timing-ruby-MESI_Two_Level/stats.txt    |   10 +-
 .../stats.txt                                      |   10 +-
 .../simple-timing-ruby-MOESI_CMP_token/stats.txt   |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt      |   10 +-
 .../ref/alpha/linux/simple-timing-ruby/stats.txt   |   10 +-
 .../ref/alpha/linux/simple-timing/stats.txt        |   10 +-
 .../ref/alpha/tru64/minor-timing/stats.txt         |   10 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   10 +-
 .../simple-timing-ruby-MESI_Two_Level/stats.txt    |   10 +-
 .../stats.txt                                      |   10 +-
 .../simple-timing-ruby-MOESI_CMP_token/stats.txt   |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt      |   10 +-
 .../ref/alpha/tru64/simple-timing-ruby/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |    8 +-
 .../00.hello/ref/arm/linux/minor-timing/stats.txt  |   10 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt      |   10 +-
 .../se/00.hello/ref/arm/linux/o3-timing/stats.txt  |   10 +-
 .../arm/linux/simple-atomic-dummychecker/stats.txt |   10 +-
 .../00.hello/ref/arm/linux/simple-atomic/stats.txt |   10 +-
 .../00.hello/ref/arm/linux/simple-timing/stats.txt |    8 +-
 .../se/00.hello/ref/mips/linux/o3-timing/stats.txt |   10 +-
 .../ref/mips/linux/simple-atomic/stats.txt         |   10 +-
 .../ref/mips/linux/simple-timing-ruby/stats.txt    |   10 +-
 .../ref/mips/linux/simple-timing/stats.txt         |    8 +-
 .../00.hello/ref/power/linux/o3-timing/stats.txt   |   10 +-
 .../ref/power/linux/simple-atomic/stats.txt        |   10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   10 +-
 .../ref/sparc/linux/simple-timing-ruby/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |    8 +-
 .../se/00.hello/ref/x86/linux/o3-timing/stats.txt  |   10 +-
 .../00.hello/ref/x86/linux/simple-atomic/stats.txt |   10 +-
 .../ref/x86/linux/simple-timing-ruby/stats.txt     |   10 +-
 .../00.hello/ref/x86/linux/simple-timing/stats.txt |    8 +-
 .../ref/alpha/linux/o3-timing-mt/stats.txt         |   10 +-
 .../ref/sparc/linux/o3-timing/stats.txt            |  947 -------
 .../ref/sparc/linux/simple-atomic/stats.txt        |  124 -
 .../ref/sparc/linux/simple-timing/stats.txt        |  474 ----
 .../alpha/linux/learning-gem5-p1-simple/stats.txt  |   10 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |    8 +-
 .../arm/linux/learning-gem5-p1-simple/stats.txt    |   10 +-
 .../arm/linux/learning-gem5-p1-two-level/stats.txt |    8 +-
 .../mips/linux/learning-gem5-p1-simple/stats.txt   |   10 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |   10 +-
 .../sparc/linux/learning-gem5-p1-simple/stats.txt  |   10 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |    8 +-
 .../x86/linux/learning-gem5-p1-simple/stats.txt    |   10 +-
 .../x86/linux/learning-gem5-p1-two-level/stats.txt |    8 +-
 .../ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt       |   10 +-
 .../10.mcf/ref/arm/linux/simple-atomic/stats.txt   |  243 --
 .../10.mcf/ref/arm/linux/simple-timing/stats.txt   |  648 -----
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |  124 -
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |  127 -
 .../ref/alpha/eio/simple-atomic/stats.txt          |  152 -
 .../ref/alpha/eio/simple-timing/stats.txt          |  497 ----
 .../ref/alpha/eio/simple-atomic-mp/stats.txt       | 1082 --------
 .../ref/alpha/eio/simple-timing-mp/stats.txt       | 1634 -----------
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |  152 -
 .../ref/sparc/linux/o3-timing-mp/stats.txt         | 2892 --------------------
 .../ref/sparc/linux/simple-atomic-mp/stats.txt     |  991 -------
 .../ref/sparc/linux/simple-timing-mp/stats.txt     | 1638 -----------
 .../linux/memtest-ruby-MESI_Two_Level/stats.txt    |    6 +-
 .../memtest-ruby-MOESI_CMP_directory/stats.txt     |    6 +-
 .../linux/memtest-ruby-MOESI_CMP_token/stats.txt   |    6 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt      |    6 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt         |    6 +-
 .../ref/null/none/memtest-filter/stats.txt         |    6 +-
 .../se/50.memtest/ref/null/none/memtest/stats.txt  |    6 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  152 -
 .../ref/alpha/tru64/simple-timing/stats.txt        |  546 ----
 .../ref/arm/linux/simple-atomic/stats.txt          |  243 --
 .../ref/arm/linux/simple-timing/stats.txt          |  662 -----
 .../ref/sparc/linux/simple-atomic/stats.txt        |  124 -
 .../ref/sparc/linux/simple-timing/stats.txt        |  535 ----
 .../51.memcheck/ref/null/none/memcheck/stats.txt   |    6 +-
 .../linux/gpu-randomtest-ruby-GPU_RfO/stats.txt    |    6 +-
 .../linux/rubytest-ruby-MESI_Two_Level/stats.txt   |    6 +-
 .../rubytest-ruby-MOESI_CMP_directory/stats.txt    |    6 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/stats.txt  |    6 +-
 .../linux/rubytest-ruby-MOESI_hammer/stats.txt     |    6 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt        |    6 +-
 .../70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt |    6 +-
 .../ref/null/none/tgen-simple-mem/stats.txt        |    6 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  152 -
 .../ref/alpha/tru64/simple-timing/stats.txt        |  534 ----
 .../70.twolf/ref/arm/linux/simple-atomic/stats.txt |  243 --
 .../70.twolf/ref/arm/linux/simple-timing/stats.txt |  644 -----
 .../ref/sparc/linux/simple-atomic/stats.txt        |  124 -
 .../ref/sparc/linux/simple-timing/stats.txt        |  515 ----
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |  127 -
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |  507 ----
 94 files changed, 284 insertions(+), 17117 deletions(-)

(limited to 'tests/quick/se')

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 0faba0dc5..6544ab634 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000037                       # Nu
 sim_ticks                                    37494000                       # Number of ticks simulated
 final_tick                                   37494000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 141195                       # Simulator instruction rate (inst/s)
-host_op_rate                                   141164                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              825166364                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252900                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 176621                       # Simulator instruction rate (inst/s)
+host_op_rate                                   176529                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1031613588                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248004                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        6413                       # Number of instructions simulated
 sim_ops                                          6413                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index c082db4f6..ead74abf4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000022                       # Nu
 sim_ticks                                    22019000                       # Number of ticks simulated
 final_tick                                   22019000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140516                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140486                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              484379589                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253664                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 115969                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115940                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              399737091                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249288                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6385                       # Number of instructions simulated
 sim_ops                                          6385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index a9b70663c..9a58520d3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3214500                       # Number of ticks simulated
 final_tick                                    3214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21023                       # Simulator instruction rate (inst/s)
-host_op_rate                                    21020                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               10551583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216888                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
+host_inst_rate                                1011674                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1009913                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              506215370                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237756                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index 7c6c13cf7..e07863c49 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000122                       # Nu
 sim_ticks                                      121535                       # Number of ticks simulated
 final_tick                                     121535                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23854                       # Simulator instruction rate (inst/s)
-host_op_rate                                    23852                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 452710                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 387364                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  71837                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71828                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1363198                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407704                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 58f4afdee..86b91c7c5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000109                       # Nu
 sim_ticks                                      108878                       # Number of ticks simulated
 final_tick                                     108878                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  17471                       # Simulator instruction rate (inst/s)
-host_op_rate                                    17470                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 297052                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 393472                       # Number of bytes of host memory used
-host_seconds                                     0.37                       # Real time elapsed on the host
+host_inst_rate                                  68389                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68380                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1162621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 413676                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 5e0571904..bdd21635f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000108                       # Nu
 sim_ticks                                      108253                       # Number of ticks simulated
 final_tick                                     108253                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39556                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39552                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 668635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388512                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                   4411                       # Simulator instruction rate (inst/s)
+host_op_rate                                     4411                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  74577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409256                       # Number of bytes of host memory used
+host_seconds                                     1.45                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 7e8297657..463ba3cfb 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000087                       # Nu
 sim_ticks                                       86770                       # Number of ticks simulated
 final_tick                                      86770                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  43915                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43910                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 594975                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388108                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  99240                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99218                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1344283                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407932                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 0d68fa8cb..d5526ad82 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000107                       # Nu
 sim_ticks                                      107065                       # Number of ticks simulated
 final_tick                                     107065                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  18652                       # Simulator instruction rate (inst/s)
-host_op_rate                                    18652                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 311861                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390536                       # Number of bytes of host memory used
-host_seconds                                     0.34                       # Real time elapsed on the host
+host_inst_rate                                 109103                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109072                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1823360                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411068                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 1dfe1dcb3..4c1b7f48d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000036                       # Nu
 sim_ticks                                    35682500                       # Number of ticks simulated
 final_tick                                   35682500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 421865                       # Simulator instruction rate (inst/s)
-host_op_rate                                   421312                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2345119890                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251096                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 581025                       # Simulator instruction rate (inst/s)
+host_op_rate                                   580437                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3231677275                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247496                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 165263111..f75116dfd 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    20320000                       # Number of ticks simulated
 final_tick                                   20320000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 183657                       # Simulator instruction rate (inst/s)
-host_op_rate                                   183501                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1441333472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251592                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 154508                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154391                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1212791416                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246696                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 86178d83d..92634ef37 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12409500                       # Number of ticks simulated
 final_tick                                   12409500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67215                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67181                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              349098234                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252356                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  87055                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87008                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              452104980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247976                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index ff4b92b39..8171db450 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54662                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54627                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27487977                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219680                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 461545                       # Simulator instruction rate (inst/s)
+host_op_rate                                   460635                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              231518490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237472                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index a9f8176e1..cb06e619e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000046                       # Nu
 sim_ticks                                       45733                       # Number of ticks simulated
 final_tick                                      45733                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42490                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42477                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 753627                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 411088                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  63739                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63721                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1130531                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407420                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index be4c58d22..f80632a35 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                       41712                       # Number of ticks simulated
 final_tick                                      41712                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38081                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38070                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 616024                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 414508                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  64355                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64336                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1041083                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410320                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 6e16bb481..03e04136e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000041                       # Nu
 sim_ticks                                       40527                       # Number of ticks simulated
 final_tick                                      40527                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25710                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25704                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 404148                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390780                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                   1955                       # Simulator instruction rate (inst/s)
+host_op_rate                                     1955                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  30751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407948                       # Number of bytes of host memory used
+host_seconds                                     1.32                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 08266d48d..2707b659f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                       32936                       # Number of ticks simulated
 final_tick                                      32936                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52774                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52753                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 673978                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 411572                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  83066                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82987                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1059779                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407644                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index c437c6665..15c5cf0e9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                       41659                       # Number of ticks simulated
 final_tick                                      41659                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41992                       # Simulator instruction rate (inst/s)
-host_op_rate                                    41979                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 678429                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 412928                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  92225                       # Simulator instruction rate (inst/s)
+host_op_rate                                    92177                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1489374                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407716                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 3011688bd..9736e3d18 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18239500                       # Number of ticks simulated
 final_tick                                   18239500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 277034                       # Simulator instruction rate (inst/s)
-host_op_rate                                   276552                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1954350939                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249792                       # Number of bytes of host memory used
+host_inst_rate                                 339288                       # Simulator instruction rate (inst/s)
+host_op_rate                                   338780                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2394585777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246188                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index cb66660d4..605a65a27 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                    29977500                       # Number of ticks simulated
 final_tick                                   29977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  89930                       # Simulator instruction rate (inst/s)
-host_op_rate                                   105235                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              584953104                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268772                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 146522                       # Simulator instruction rate (inst/s)
+host_op_rate                                   171470                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              953185288                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264656                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 58e5912c9..8765a9cf5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17232500                       # Number of ticks simulated
 final_tick                                   17232500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  43939                       # Simulator instruction rate (inst/s)
-host_op_rate                                    51450                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              164826819                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269540                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  66942                       # Simulator instruction rate (inst/s)
+host_op_rate                                    78386                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              251130115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265932                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index d43357405..f8ba6e8d6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18821000                       # Number of ticks simulated
 final_tick                                   18821000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49791                       # Simulator instruction rate (inst/s)
-host_op_rate                                    58299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              203978556                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266084                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  45352                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53108                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              185838458                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261708                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 9ffa594c7..bcfa49270 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  13445                       # Simulator instruction rate (inst/s)
-host_op_rate                                    15745                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                7889483                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237392                       # Number of bytes of host memory used
-host_seconds                                     0.34                       # Real time elapsed on the host
+host_inst_rate                                 274500                       # Simulator instruction rate (inst/s)
+host_op_rate                                   321069                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              160714630                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254660                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index e53928c68..6f1efaf21 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30076                       # Simulator instruction rate (inst/s)
-host_op_rate                                    35217                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               17644392                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236884                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                 363981                       # Simulator instruction rate (inst/s)
+host_op_rate                                   425522                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              212904964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254404                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index facfa8248..e99784abb 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 441317                       # Simulator instruction rate (inst/s)
-host_op_rate                                   514292                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2726097982                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267744                       # Number of bytes of host memory used
+host_inst_rate                                 343617                       # Simulator instruction rate (inst/s)
+host_op_rate                                   400476                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2123290642                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263372                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 815eb0bfe..0194e3c6f 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000023                       # Nu
 sim_ticks                                    22532000                       # Number of ticks simulated
 final_tick                                   22532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65525                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65509                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              295199371                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251356                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  96442                       # Simulator instruction rate (inst/s)
+host_op_rate                                    96403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              434426491                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247240                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4999                       # Number of instructions simulated
 sim_ops                                          4999                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 9b5c0be15..df8a010ee 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2820500                       # Number of ticks simulated
 final_tick                                    2820500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42403                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42398                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               21196256                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214708                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                 876414                       # Simulator instruction rate (inst/s)
+host_op_rate                                   873362                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              435104956                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235716                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 4c477fff4..194e91ae7 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000100                       # Nu
 sim_ticks                                      100232                       # Number of ticks simulated
 final_tick                                     100232                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20831                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20830                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 370097                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389556                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  97717                       # Simulator instruction rate (inst/s)
+host_op_rate                                    97699                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1735645                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410048                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index f975f616d..0e87b1f2c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000034                       # Nu
 sim_ticks                                    33932500                       # Number of ticks simulated
 final_tick                                   33932500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 442497                       # Simulator instruction rate (inst/s)
-host_op_rate                                   441783                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2653552582                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249064                       # Number of bytes of host memory used
+host_inst_rate                                 431758                       # Simulator instruction rate (inst/s)
+host_op_rate                                   430982                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2588300068                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244424                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 2c6934aef..9c7cb3cdb 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19908000                       # Number of ticks simulated
 final_tick                                   19908000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 130311                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130281                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              447700777                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249300                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 120043                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120013                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              412413617                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245176                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index e25b901ab..5dd437e9a 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2896000                       # Number of ticks simulated
 final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76704                       # Simulator instruction rate (inst/s)
-host_op_rate                                    76683                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38324639                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216536                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 887311                       # Simulator instruction rate (inst/s)
+host_op_rate                                   885785                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              442112700                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234416                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5793                       # Number of instructions simulated
 sim_ops                                          5793                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 8bcf3caa4..0889a55c9 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  62253                       # Simulator instruction rate (inst/s)
-host_op_rate                                    62235                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               31469743                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218904                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                 633206                       # Simulator instruction rate (inst/s)
+host_op_rate                                   631372                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              318532177                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236156                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 24a3b23de..3a583092f 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000082                       # Nu
 sim_ticks                                       81703                       # Number of ticks simulated
 final_tick                                      81703                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27831                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27828                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 426765                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 393224                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  79389                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79372                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1217125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409468                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index ddd387c47..ad6f58618 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30526500                       # Number of ticks simulated
 final_tick                                   30526500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 608531                       # Simulator instruction rate (inst/s)
-host_op_rate                                   607803                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3479427932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249516                       # Number of bytes of host memory used
+host_inst_rate                                 398653                       # Simulator instruction rate (inst/s)
+host_op_rate                                   397863                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2276293986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245124                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 3c1544f1d..4713d8f7c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21273500                       # Number of ticks simulated
 final_tick                                   21273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70008                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              276755373                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271684                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  54566                       # Simulator instruction rate (inst/s)
+host_op_rate                                    98846                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              215714601                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266040                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index c4292eb87..dcd77e088 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5615000                       # Number of ticks simulated
 final_tick                                    5615000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  26569                       # Simulator instruction rate (inst/s)
-host_op_rate                                    48126                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27718570                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237032                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                 380560                       # Simulator instruction rate (inst/s)
+host_op_rate                                   688269                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              395838528                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254256                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 06e819e18..bf06f8c45 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                       87948                       # Number of ticks simulated
 final_tick                                      87948                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28860                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52275                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 471584                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 411784                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  77426                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140230                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1264887                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 428592                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index b345a9c01..0e6d74be3 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30886500                       # Number of ticks simulated
 final_tick                                   30886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 235920                       # Simulator instruction rate (inst/s)
-host_op_rate                                   427054                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1352150005                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266824                       # Number of bytes of host memory used
+host_inst_rate                                 324268                       # Simulator instruction rate (inst/s)
+host_op_rate                                   586988                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1858658321                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262968                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index fcca5b721..458736244 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25580500                       # Number of ticks simulated
 final_tick                                   25580500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  85448                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85436                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              171120344                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253996                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                 119260                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119247                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              238851205                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249876                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                       12770                       # Number of instructions simulated
 sim_ops                                         12770                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index e76497684..e69de29bb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,947 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000029                       # Number of seconds simulated
-sim_ticks                                    28845500                       # Number of ticks simulated
-final_tick                                   28845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68981                       # Simulator instruction rate (inst/s)
-host_op_rate                                    68975                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              137812851                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251992                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-sim_insts                                       14436                       # Number of instructions simulated
-sim_ops                                         14436                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                32640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23232                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   510                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            805394256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            326151393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1131545648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       805394256                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          805394256                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           805394256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           326151393                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1131545648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           511                       # Number of read requests accepted
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         511                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    32704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     32704                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 105                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  53                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  27                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  23                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  38                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   4                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                  2                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 57                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 31                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 63                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 41                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        28814000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     511                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       149                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      412.160000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     276.286075                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.271863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             13     17.33%     17.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     24.00%     41.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           12     16.00%     57.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7      9.33%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      6.67%     73.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            8     10.67%     84.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.33%     85.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11     14.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
-system.physmem.totQLat                        3584250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13165500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7014.19                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25764.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1133.76                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1133.76                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           8.86                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.86                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        428                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        56387.48                       # Average gap between requests
-system.physmem.pageHitRate                      83.76                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     309960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     169125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2121600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               15733710                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 369750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20229825                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              856.515480                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         717750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        27177750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     241920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     132000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1396200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15520815                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 556500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 19373115                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              820.243027                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        4073500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21995000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                   12618                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              7653                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1475                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 9458                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     736                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                166                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups            9458                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits               1844                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             7614                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          897                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            57692                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              15531                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          59063                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                       12618                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               2580                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         17477                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3145                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                    6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1084                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           25                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      7530                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   719                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              35695                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.654658                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.906598                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    22943     64.28%     64.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4506     12.62%     76.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      507      1.42%     78.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      451      1.26%     79.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      761      2.13%     81.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      707      1.98%     83.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      297      0.83%     84.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      355      0.99%     85.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     5168     14.48%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                35695                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.218713                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.023764                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12449                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 12945                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      7933                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   796                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1572                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  42061                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1572                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13228                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1813                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9713                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7918                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1451                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  37021                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     10                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   1034                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               31983                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 66431                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            54837                       # Number of integer rename lookups
-system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    18164                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                796                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            801                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      4352                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 4576                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2922                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                15                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      28829                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 757                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     25362                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               117                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           15150                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        11340                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            282                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         35695                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.710520                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.505149                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               26438     74.07%     74.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3266      9.15%     83.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1617      4.53%     87.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1544      4.33%     92.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1236      3.46%     95.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 754      2.11%     97.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 464      1.30%     98.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 276      0.77%     99.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                 100      0.28%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           35695                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     153     52.04%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     53     18.03%     70.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    88     29.93%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 18585     73.28%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 4271     16.84%     90.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2506      9.88%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  25362                       # Type of FU issued
-system.cpu.iq.rate                           0.439610                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         294                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011592                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              86830                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             44763                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        22607                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  25656                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         2351                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           28                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores         1474                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            26                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1572                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1846                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               31165                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               242                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  4576                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2922                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                757                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             28                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            211                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1623                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1834                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 23714                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3945                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1648                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1579                       # number of nop insts executed
-system.cpu.iew.exec_refs                         6244                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     5021                       # Number of branches executed
-system.cpu.iew.exec_stores                       2299                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.411045                       # Inst execution rate
-system.cpu.iew.wb_sent                          23102                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         22607                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10530                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     13790                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.391857                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.763597                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts           15914                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1475                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        32556                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.465721                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.244675                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        25812     79.28%     79.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3638     11.17%     90.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1209      3.71%     94.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          603      1.85%     96.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          337      1.04%     97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          302      0.93%     97.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          374      1.15%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           53      0.16%     99.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          228      0.70%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        32556                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                15162                       # Number of instructions committed
-system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           3673                       # Number of memory references committed
-system.cpu.commit.loads                          2225                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       3358                       # Number of branches committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                     12174                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                  187                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass          726      4.79%      4.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu            10763     70.99%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult               0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     75.77% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead            2225     14.67%     90.45% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   228                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        62581                       # The number of ROB reads
-system.cpu.rob.rob_writes                       65380                       # The number of ROB writes
-system.cpu.timesIdled                             195                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21997                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
-system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               3.996398                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.996398                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.250225                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.250225                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    36850                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   20548                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    8142                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            99.867537                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4648                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             31.835616                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    99.867537                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024382                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024382                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             10540                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            10540                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3609                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3609                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          4642                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4642                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4642                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4642                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          140                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           140                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          549                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            549                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          549                       # number of overall misses
-system.cpu.dcache.overall_misses::total           549                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9339500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9339500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     27134481                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     27134481                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36473981                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36473981                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36473981                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36473981                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5191                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5191                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5191                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5191                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037343                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037343                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.105760                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.105760                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.105760                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.105760                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66437.123862                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66437.123862                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1313                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.086957                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          401                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          401                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5108500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5108500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6578000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6578000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11686500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11686500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11686500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11686500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017338                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017338                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           206.414108                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                6949                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             19.038356                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   206.414108                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.100788                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.100788                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          274                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             15425                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            15425                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         6949                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6949                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6949                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6949                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6949                       # number of overall hits
-system.cpu.icache.overall_hits::total            6949                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          581                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           581                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          581                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            581                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          581                       # number of overall misses
-system.cpu.icache.overall_misses::total           581                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     40819000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     40819000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     40819000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     40819000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     40819000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     40819000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         7530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         7530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         7530                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         7530                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         7530                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         7530                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.077158                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.077158                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.077158                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.077158                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.077158                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.077158                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70256.454389                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70256.454389                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          190                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           95                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          216                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          216                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          216                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          216                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          216                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          216                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          365                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          365                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27746500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27746500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27746500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27746500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27746500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27746500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.048473                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.048473                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.048473                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          240.923513                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              426                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.004695                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   205.773852                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    35.149660                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006280                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001073                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007352                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          426                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013000                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4613                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4613                       # Number of data accesses
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           65                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           65                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          363                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          148                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           511                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          148                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          511                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6452500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6452500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27176000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     27176000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5013500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5013500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     27176000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11466000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     38642000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     27176000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11466000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     38642000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          365                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          365                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           65                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           65                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          365                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          148                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          513                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          365                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          148                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          513                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994521                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994521                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994521                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.996101                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994521                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.996101                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          363                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           65                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           65                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          363                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          511                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          511                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5622500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5622500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23546000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23546000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4383500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4383500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23546000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10006000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     33552000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23546000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10006000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     33552000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994521                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.996101                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.996101                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          513                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            2                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp           428                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          365                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           65                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1024                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              32704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          513                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.003899                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.062378                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                511     99.61%     99.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  2      0.39%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            513                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         256500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        547500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        219000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                426                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           428                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1020                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1020                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        32576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   32576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               511                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     511    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 511                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              623500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2694000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              9.3                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index af8e6136b..e69de29bb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,124 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000008                       # Number of seconds simulated
-sim_ticks                                     7612000                       # Number of ticks simulated
-final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20450                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20449                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               10266040                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218684                       # Number of bytes of host memory used
-host_seconds                                     0.74                       # Real time elapsed on the host
-sim_insts                                       15162                       # Number of instructions simulated
-sim_ops                                         15162                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             60828                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11342                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                72170                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data           9042                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              9042                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15207                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2225                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 17432                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data              1442                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 1442                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data                  6                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                     6                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7991066737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1490015765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9481082501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7991066737                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7991066737                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1187861272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1187861272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7991066737                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2677877036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10668943773                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            15225                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15162                       # Number of instructions committed
-system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12219                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13819                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3683                       # number of memory refs
-system.cpu.num_load_insts                        2231                       # Number of load instructions
-system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               15224.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                              3363                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
-system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::MemRead                     2231     14.67%     90.45% # Class of executed instruction
-system.cpu.op_class::MemWrite                    1452      9.55%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                      15207                       # Class of executed instruction
-system.membus.trans_dist::ReadReq               17432                       # Transaction distribution
-system.membus.trans_dist::ReadResp              17432                       # Transaction distribution
-system.membus.trans_dist::WriteReq               1442                       # Transaction distribution
-system.membus.trans_dist::WriteResp              1442                       # Transaction distribution
-system.membus.trans_dist::SwapReq                   6                       # Transaction distribution
-system.membus.trans_dist::SwapResp                  6                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port        30414                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         7346                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  37760                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        60828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port        20442                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   81270                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             18880                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.805456                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.395860                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3673     19.45%     19.45% # Request fanout histogram
-system.membus.snoop_fanout::1                   15207     80.55%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total               18880                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 457c52bd3..e69de29bb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,474 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000044                       # Number of seconds simulated
-sim_ticks                                    44282500                       # Number of ticks simulated
-final_tick                                   44282500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 298703                       # Simulator instruction rate (inst/s)
-host_op_rate                                   298583                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              871748609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249440                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-sim_insts                                       15162                       # Number of instructions simulated
-sim_ops                                         15162                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            401784000                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            199446734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               601230734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       401784000                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          401784000                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           401784000                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           199446734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              601230734                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            88565                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15162                       # Number of instructions committed
-system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12219                       # number of integer instructions
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13818                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3683                       # number of memory refs
-system.cpu.num_load_insts                        2231                       # Number of load instructions
-system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               88564.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                              3363                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                   726      4.77%      4.77% # Class of executed instruction
-system.cpu.op_class::IntAlu                     10798     71.01%     75.78% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.78% # Class of executed instruction
-system.cpu.op_class::MemRead                     2231     14.67%     90.45% # Class of executed instruction
-system.cpu.op_class::MemWrite                    1452      9.55%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                      15207                       # Class of executed instruction
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            97.148649                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                3535                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             25.615942                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    97.148649                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.023718                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.023718                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              7484                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             7484                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         2172                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2172                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1357                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3529                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3529                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3529                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3529                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            53                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           85                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           85                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3286000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3286000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5270000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5270000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      8556000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      8556000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      8556000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      8556000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023820                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.023820                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037633                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037633                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037633                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037633                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        62000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        62000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        62000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        62000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        62000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        62000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        62000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        62000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3233000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3233000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8418000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8418000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        61000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        61000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        61000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           151.748662                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs               14928                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               280                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             53.314286                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   151.748662                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.074096                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.074096                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          280                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.136719                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             30696                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            30696                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst        14928                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total           14928                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst         14928                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total            14928                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst        14928                       # number of overall hits
-system.cpu.icache.overall_hits::total           14928                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          280                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           280                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          280                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            280                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          280                       # number of overall misses
-system.cpu.icache.overall_misses::total           280                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17264500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17264500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17264500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17264500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17264500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17264500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst        15208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total        15208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst        15208                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total        15208                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst        15208                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total        15208                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018411                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.018411                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.018411                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.018411                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.018411                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.018411                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61658.928571                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61658.928571                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16984500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16984500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16984500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16984500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16984500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16984500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.018411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.018411                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.018411                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          182.297739                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              331                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.006042                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   151.068800                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.228940                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004610                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000953                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005563                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          331                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          276                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010101                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           53                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           53                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           416                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          416                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5057500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5057500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16541500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     16541500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      3153500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      3153500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16541500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      8211000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     24752500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16541500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      8211000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     24752500                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          280                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          280                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           53                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           53                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.992857                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992857                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995215                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992857                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995215                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           53                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           53                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          416                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          416                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4207500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4207500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     13761500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     13761500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2623500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2623500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     13761500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6831000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     20592500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     13761500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6831000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     20592500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.992857                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          418                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            2                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp           333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           85                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          280                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           53                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          560                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               836                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              26752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          418                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.004785                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.069088                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                416     99.52%     99.52% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  2      0.48%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            418                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        420000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        207000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                331                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               85                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           331                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          832                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    832                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               416                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     416    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 416                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              416500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2080000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              4.7                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
index 1b652ed70..3711ab70b 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000405                       # Nu
 sim_ticks                                   405365000                       # Number of ticks simulated
 final_tick                                  405365000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83628                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83610                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5251060650                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 610048                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 217578                       # Simulator instruction rate (inst/s)
+host_op_rate                                   217432                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13650898473                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 630716                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
index 3c13d46b0..57afd555e 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000061                       # Nu
 sim_ticks                                    61470000                       # Number of ticks simulated
 final_tick                                   61470000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 583425                       # Simulator instruction rate (inst/s)
-host_op_rate                                   580281                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5518802940                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 637904                       # Number of bytes of host memory used
+host_inst_rate                                 556042                       # Simulator instruction rate (inst/s)
+host_op_rate                                   555477                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5286056763                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 634812                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
index 5a6464d85..6a638c326 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000326                       # Nu
 sim_ticks                                   325849000                       # Number of ticks simulated
 final_tick                                  325849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67062                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77548                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4377845869                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 629736                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 156546                       # Simulator instruction rate (inst/s)
+host_op_rate                                   180975                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10214317316                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647364                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index 60d51d141..1fca855be 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 523400                       # Simulator instruction rate (inst/s)
-host_op_rate                                   604831                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5220928914                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 655332                       # Number of bytes of host memory used
+host_inst_rate                                 388067                       # Simulator instruction rate (inst/s)
+host_op_rate                                   448196                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3866626926                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 651460                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
index 4088c6bf9..9cc36ad4e 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000369                       # Nu
 sim_ticks                                   368887000                       # Number of ticks simulated
 final_tick                                  368887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25687                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25686                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1679592961                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 607900                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                 294016                       # Simulator instruction rate (inst/s)
+host_op_rate                                   293668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19182713753                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 628676                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
index 2c65c222a..f4dfddbc8 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000059                       # Nu
 sim_ticks                                    58892000                       # Number of ticks simulated
 final_tick                                   58892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 350541                       # Simulator instruction rate (inst/s)
-host_op_rate                                   350101                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3650563038                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 636120                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 509573                       # Simulator instruction rate (inst/s)
+host_op_rate                                   509069                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5309891860                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632772                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
index 05b70a5db..aae0960f1 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000333                       # Nu
 sim_ticks                                   333033000                       # Number of ticks simulated
 final_tick                                  333033000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75807                       # Simulator instruction rate (inst/s)
-host_op_rate                                    75776                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4546866876                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 611808                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 348800                       # Simulator instruction rate (inst/s)
+host_op_rate                                   348537                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            20908249754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 629116                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
index 718f7b51e..f9225f3bc 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                    53334000                       # Number of ticks simulated
 final_tick                                   53334000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 388058                       # Simulator instruction rate (inst/s)
-host_op_rate                                   387570                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3721714769                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 636836                       # Number of bytes of host memory used
+host_inst_rate                                 429905                       # Simulator instruction rate (inst/s)
+host_op_rate                                   429380                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4122052129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 633208                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
index f579e14d0..f88f09a70 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000445                       # Nu
 sim_ticks                                   445082000                       # Number of ticks simulated
 final_tick                                  445082000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66069                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119271                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5145784728                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 629884                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                 211115                       # Simulator instruction rate (inst/s)
+host_op_rate                                   380995                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            16432986499                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647212                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
index e0706d7d4..78bfc0a03 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000056                       # Nu
 sim_ticks                                    55844000                       # Number of ticks simulated
 final_tick                                   55844000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 250477                       # Simulator instruction rate (inst/s)
-host_op_rate                                   451948                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2445398371                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 655164                       # Number of bytes of host memory used
+host_inst_rate                                 299396                       # Simulator instruction rate (inst/s)
+host_op_rate                                   540174                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2922543083                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 651308                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
index 092f1ac37..1711c0a9f 100644
--- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
+++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000663                       # Nu
 sim_ticks                                   663454500                       # Number of ticks simulated
 final_tick                                  663454500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97803                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201121                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              968968514                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1290208                       # Number of bytes of host memory used
-host_seconds                                     0.68                       # Real time elapsed on the host
+host_inst_rate                                 153021                       # Simulator instruction rate (inst/s)
+host_op_rate                                   314663                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1515963159                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1308268                       # Number of bytes of host memory used
+host_seconds                                     0.44                       # Real time elapsed on the host
 sim_insts                                       66963                       # Number of instructions simulated
 sim_ops                                        137705                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index f57e8a542..e69de29bb 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,243 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.054141                       # Number of seconds simulated
-sim_ticks                                 54141000500                       # Number of ticks simulated
-final_tick                                54141000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 763855                       # Simulator instruction rate (inst/s)
-host_op_rate                                   767659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              456454296                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 371948                       # Number of bytes of host memory used
-host_seconds                                   118.61                       # Real time elapsed on the host
-sim_insts                                    90602408                       # Number of instructions simulated
-sim_ops                                      91053639                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         431323084                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          90016598                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            521339682                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    431323084                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       431323084                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       18908138                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18908138                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          107830771                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           22461532                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             130292303                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data           4738868                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              4738868                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7966662604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1662632703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9629295306                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7966662604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7966662604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           349238799                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              349238799                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7966662604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2011871502                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9978534106                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        108282002                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    90602408                       # Number of instructions committed
-system.cpu.committedOps                      91053639                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72326352                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124257699                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            271814243                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      27220755                       # number of memory refs
-system.cpu.num_load_insts                    22475911                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               108282001.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          18732305                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63822829     70.09%     70.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91054081                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           130287906                       # Transaction distribution
-system.membus.trans_dist::ReadResp          130291793                       # Transaction distribution
-system.membus.trans_dist::WriteReq            4734981                       # Transaction distribution
-system.membus.trans_dist::WriteResp           4734981                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq               510                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp              510                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq          3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq           3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp          3887                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    215661542                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     54400800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              270062342                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               540247820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         135031171                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.798562                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                27200400     20.14%     20.14% # Request fanout histogram
-system.membus.snoop_fanout::1               107830771     79.86%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           135031171                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 93c64ae72..e69de29bb 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,648 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.147149                       # Number of seconds simulated
-sim_ticks                                147148719500                       # Number of ticks simulated
-final_tick                               147148719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1067474                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1072778                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1734188097                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 402040                       # Number of bytes of host memory used
-host_seconds                                    84.85                       # Real time elapsed on the host
-sim_insts                                    90576862                       # Number of instructions simulated
-sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             36928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            944832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               981760                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        36928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           36928                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                577                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              14763                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15340                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               250957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6420933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6671890                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          250957                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             250957                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              250957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6420933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6671890                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        294297439                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    90576862                       # Number of instructions committed
-system.cpu.committedOps                      91026991                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72326352                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124237033                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            339191621                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      27220755                       # number of memory refs
-system.cpu.num_load_insts                    22475911                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               294297438.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          18732305                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63822829     70.09%     70.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91054081                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            942702                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3565.478025                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       54453325500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3565.478025                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.870478                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.870478                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1357                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2563                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55347598                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55347598                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21556948                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21556948                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          507                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           507                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26245320                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26245320                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26245827                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26245827                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       900187                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        900187                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       946796                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         946796                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       946799                       # number of overall misses
-system.cpu.dcache.overall_misses::total        946799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11713009000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11713009000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1319019500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1319019500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13032028500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13032028500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13032028500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13032028500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13764.346808                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13764.303194                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
-system.cpu.dcache.writebacks::total            942334                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10812776000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10812776000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1272410500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1272410500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       134000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       134000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12085186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12085186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12085320500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12085320500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements                 2                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.111710                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           107830173                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               599                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          180016.983306                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.111710                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.249078                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.249078                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          552                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.291504                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         215662143                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        215662143                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    107830173                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       107830173                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     107830173                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        107830173                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    107830173                       # number of overall hits
-system.cpu.icache.overall_hits::total       107830173                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          599                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           599                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          599                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
-system.cpu.icache.overall_misses::total           599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     36093000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     36093000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     36093000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     36093000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     36093000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     36093000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    107830772                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    107830772                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    107830772                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    107830772                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    107830772                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    107830772                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000006                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 60255.425710                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 60255.425710                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks            2                       # number of writebacks
-system.cpu.icache.writebacks::total                 2                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35494000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     35494000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35494000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     35494000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35494000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     35494000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9564.658425                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1827433                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15323                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           119.260784                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8876.269803                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   494.164592                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   194.224030                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.270882                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015081                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.005927                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.291890                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15323                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1473                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15181828                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15181828                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       942334                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       942334                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           22                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           22                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       899974                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       899974                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       932035                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          932057                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       932035                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         932057                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          577                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          577                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          215                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          215                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          577                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        14763                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15340                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          577                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        14763                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15340                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    865856500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    865856500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     34343500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     34343500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     12794500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     12794500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     34343500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    878651000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    912994500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     34343500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    878651000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    912994500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       942334                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       942334                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          599                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          599                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       900189                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       900189                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.963272                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.963272                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000239                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000239                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963272                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.015593                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016192                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963272                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.015593                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016192                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          577                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          577                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          215                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          215                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          577                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        14763                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15340                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          577                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        14763                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15340                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    720376500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    720376500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     28573500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     28573500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     10644500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     10644500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28573500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    731021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    759594500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28573500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    731021000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    759594500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.963272                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000239                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000239                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015593                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016192                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.963272                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015593                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016192                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      1890101                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       942715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests          114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       942334                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          368                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       900189                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1200                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2836298                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2837498                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        38464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          120942912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       947397                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000132                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.011486                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             947272     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                125      0.01%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         947397                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1887386500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        898500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1420197000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                792                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           792                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15340                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15340    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15340                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15604500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           76700000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index b85047da6..e69de29bb 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,124 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.122216                       # Number of seconds simulated
-sim_ticks                                122215823500                       # Number of ticks simulated
-final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1145191                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1145238                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              574019671                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353116                       # Number of bytes of host memory used
-host_seconds                                   212.91                       # Real time elapsed on the host
-sim_insts                                   243825150                       # Number of instructions simulated
-sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         977685992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         328674008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1306360000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    977685992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       977685992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       91606089                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          91606089                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          244421498                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           82220433                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             326641931                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          22901951                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             22901951                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data               3886                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                  3886                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999667834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2689291768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10688959601                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           749543606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              749543606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999667834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3438835373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11438503207                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        244431648                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   243825150                       # Number of instructions committed
-system.cpu.committedOps                     243835265                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             194726494                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
-system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619959                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726494                       # number of integer instructions
-system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456818988                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451554                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711441                       # number of memory refs
-system.cpu.num_load_insts                    82803521                       # Number of load instructions
-system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               244431647.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          29302884                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
-system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      42      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::MemRead                 82803527     33.88%     90.63% # Class of executed instruction
-system.cpu.op_class::MemWrite                22907920      9.37%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  244431613                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           326641931                       # Transaction distribution
-system.membus.trans_dist::ReadResp          326641931                       # Transaction distribution
-system.membus.trans_dist::WriteReq           22901951                       # Transaction distribution
-system.membus.trans_dist::WriteResp          22901951                       # Transaction distribution
-system.membus.trans_dist::SwapReq                3886                       # Transaction distribution
-system.membus.trans_dist::SwapResp               3886                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    488842996                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    210252540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              699095536                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    977685992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    420311185                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              1397997177                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         349547768                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.699251                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.458584                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0               105126270     30.07%     30.07% # Request fanout histogram
-system.membus.snoop_fanout::1               244421498     69.93%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           349547768                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 98c94dc36..e69de29bb 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,127 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.168950                       # Number of seconds simulated
-sim_ticks                                168950040000                       # Number of ticks simulated
-final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 537919                       # Simulator instruction rate (inst/s)
-host_op_rate                                   947189                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              575240737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379572                       # Number of bytes of host memory used
-host_seconds                                   293.70                       # Real time elapsed on the host
-sim_insts                                   157988548                       # Number of instructions simulated
-sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         717246013                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           2458815325                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1741569312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1741569312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data      243173117                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         243173117                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          217696164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           90779447                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             308475611                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          31439752                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             31439752                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          10308191179                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           4245314254                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             14553505433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     10308191179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        10308191179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1439319677                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1439319677                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         10308191179                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5684633931                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            15992825110                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        337900081                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   157988548                       # Number of instructions committed
-system.cpu.committedOps                     278192465                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             278169482                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                     8475189                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278169482                       # number of integer instructions
-system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           635379407                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          217447860                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            104140596                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            61764861                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     122219137                       # number of memory refs
-system.cpu.num_load_insts                    90779385                       # Number of load instructions
-system.cpu.num_store_insts                   31439752                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               337900080.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          29309705                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction
-system.cpu.op_class::IntMult                    10938      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::IntDiv                       329      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      12      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::MemRead                 90779385     32.63%     88.70% # Class of executed instruction
-system.cpu.op_class::MemWrite                31439752     11.30%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  278192465                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           308475611                       # Transaction distribution
-system.membus.trans_dist::ReadResp          308475611                       # Transaction distribution
-system.membus.trans_dist::WriteReq           31439752                       # Transaction distribution
-system.membus.trans_dist::WriteResp          31439752                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    435392328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total    435392328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    244438398                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total    244438398                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              679830726                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1741569312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total   1741569312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    960419130                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total    960419130                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2701988442                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         339915363                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.640442                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.479871                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0               122219199     35.96%     35.96% # Request fanout histogram
-system.membus.snoop_fanout::1               217696164     64.04%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           339915363                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 850ec8600..e69de29bb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,152 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1181428                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1181354                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              590676886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220296                       # Number of bytes of host memory used
-host_seconds                                     0.42                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           2000076                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            872600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              2872676                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      2000076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         2000076                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data         417562                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            417562                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             500019                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             124435                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                624454                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data             56340                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                56340                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999808012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           3490183609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11489991621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999808012                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999808012                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1670144451                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1670144451                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999808012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5160328060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13160136072                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500019                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500032                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                           500032                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                             59023                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 18814      3.76%      3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu                    300388     60.08%     63.84% # Class of executed instruction
-system.cpu.op_class::IntMult                       10      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      10      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       2      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult                      2      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::MemRead                   124443     24.89%     88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                     500019                       # Class of executed instruction
-system.membus.trans_dist::ReadReq              624454                       # Transaction distribution
-system.membus.trans_dist::ReadResp             624454                       # Transaction distribution
-system.membus.trans_dist::WriteReq              56340                       # Transaction distribution
-system.membus.trans_dist::WriteResp             56340                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port      1000038                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port       361550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1361588                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port      2000076                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port      1290162                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 3290238                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            680794                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.734464                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.441618                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  180775     26.55%     26.55% # Request fanout histogram
-system.membus.snoop_fanout::1                  500019     73.45%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              680794                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 45ece38cc..e69de29bb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,497 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000733                       # Number of seconds simulated
-sim_ticks                                   733071500                       # Number of ticks simulated
-final_tick                                  733071500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 558953                       # Simulator instruction rate (inst/s)
-host_op_rate                                   558933                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              819448941                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229836                       # Number of bytes of host memory used
-host_seconds                                     0.89                       # Real time elapsed on the host
-sim_insts                                      500001                       # Number of instructions simulated
-sim_ops                                        500001                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                54848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   857                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst             35183471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39635970                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                74819441                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        35183471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           35183471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            35183471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39635970                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               74819441                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                       124435                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
-system.cpu.dtb.write_hits                       56340                       # DTB write hits
-system.cpu.dtb.write_misses                        10                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
-system.cpu.dtb.data_hits                       180775                       # DTB hits
-system.cpu.dtb.data_misses                         18                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                   180793                       # DTB accesses
-system.cpu.itb.fetch_hits                      500020                       # ITB hits
-system.cpu.itb.fetch_misses                        13                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                  500033                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                          1466143                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                      500001                       # Number of instructions committed
-system.cpu.committedOps                        500001                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                    1466143                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                             59023                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 18814      3.76%      3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu                    300388     60.08%     63.84% # Class of executed instruction
-system.cpu.op_class::IntMult                       10      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      10      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       2      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult                      2      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu.op_class::MemRead                   124443     24.89%     88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite                   56350     11.27%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                     500019                       # Class of executed instruction
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           286.668758                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs              180321                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               454                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            397.182819                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   286.668758                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.069987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.069987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          454                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          426                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.110840                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses            362004                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses           362004                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data       124120                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total          124120                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data        56201                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total          56201                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data        180321                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total           180321                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data       180321                       # number of overall hits
-system.cpu.dcache.overall_hits::total          180321                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          139                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.dcache.overall_misses::total           454                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     19530000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     19530000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      8618000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8618000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     28148000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     28148000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     28148000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     28148000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002531                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002531                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002511                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002511                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002511                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002511                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        62000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        62000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        62000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        62000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        62000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        62000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        62000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        62000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          454                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          454                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     19215000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     19215000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8479000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      8479000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     27694000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     27694000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     27694000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     27694000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002531                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002531                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        61000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        61000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        61000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           264.585152                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs              499617                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               403                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1239.744417                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   264.585152                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.129192                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.129192                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          403                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          403                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.196777                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           1000443                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          1000443                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst       499617                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total          499617                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst        499617                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total           499617                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst       499617                       # number of overall hits
-system.cpu.icache.overall_hits::total          499617                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           403                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            403                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.icache.overall_misses::total           403                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     24986500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     24986500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     24986500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     24986500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     24986500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     24986500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst       500020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst       500020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000806                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000806                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000806                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000806                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000806                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000806                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62001.240695                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62001.240695                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          403                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          403                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          403                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24583500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24583500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24583500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24583500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24583500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24583500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000806                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          480.680597                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              718                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   264.590924                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   216.089673                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008075                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006595                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.014669                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          718                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          714                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021912                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             7713                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            7713                       # Number of data accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          403                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          403                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          315                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          315                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           857                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          403                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          454                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          857                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      8270500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      8270500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     23979000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     23979000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     18742500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     18742500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     23979000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     27013000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     50992000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     23979000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     27013000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     50992000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total          139                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          403                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          403                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          315                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          315                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          403                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          454                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          857                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          403                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          454                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          857                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          139                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          403                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          403                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          315                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          315                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          857                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          857                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6880500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      6880500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19949000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19949000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15592500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15592500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19949000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     22473000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     42422000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19949000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     22473000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     42422000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          857                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp           718                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq          139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp          139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          403                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          315                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          806                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          908                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1714                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        25792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        29056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              54848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          857                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                857    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            857                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         428500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        604500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        681000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                718                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               139                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              139                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           718                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        54848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   54848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               857                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     857    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 857                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              857500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4285000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index f03bf3dc9..e69de29bb 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,1082 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   250015500                       # Number of ticks simulated
-final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1254205                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1254187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              156780790                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242604                       # Number of bytes of host memory used
-host_seconds                                     1.59                       # Real time elapsed on the host
-sim_insts                                     2000004                       # Number of instructions simulated
-sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst           103161604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data           116216795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               877513594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst      103161604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          412646416                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst          103161604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data          116216795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              877513594                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500019                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.Branches                            59023                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    500019                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements               61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.872320                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           723563                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          723563                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.icache.tags.replacements              152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           500482                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          500482                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499556                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499556                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499556                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu0.icache.writebacks::total              152                       # number of writebacks
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56340                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180775                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500019                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     500001                       # Number of instructions committed
-system.cpu1.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474689                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180793                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56350                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.Branches                            59023                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    500019                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements               61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   276.872320                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           723563                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          723563                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56201                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180312                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180312                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.icache.tags.replacements              152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           500482                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          500482                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499556                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499556                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499556                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu1.icache.writebacks::total              152                       # number of writebacks
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124435                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56340                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180775                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500019                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     500001                       # Number of instructions committed
-system.cpu2.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474689                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180793                       # number of memory refs
-system.cpu2.num_load_insts                     124443                       # Number of load instructions
-system.cpu2.num_store_insts                     56350                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.Branches                            59023                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    500019                       # Class of executed instruction
-system.cpu2.dcache.tags.replacements               61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data   276.872320                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           723563                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          723563                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56201                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180312                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180312                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.icache.tags.replacements              152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           500482                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          500482                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499556                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499556                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499556                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu2.icache.writebacks::total              152                       # number of writebacks
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124435                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56340                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180775                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu3.itb.fetch_hits                     500019                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     500001                       # Number of instructions committed
-system.cpu3.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474689                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180793                       # number of memory refs
-system.cpu3.num_load_insts                     124443                       # Number of load instructions
-system.cpu3.num_store_insts                     56350                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.Branches                            59023                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    500019                       # Class of executed instruction
-system.cpu3.dcache.tags.replacements               61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data   276.872320                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2          248                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           723563                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          723563                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124111                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56201                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180312                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180312                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.icache.tags.replacements              152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst   218.086151                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           500482                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          500482                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499556                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499556                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499556                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499556                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499556                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       500019                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       500019                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       500019                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu3.icache.writebacks::total              152                       # number of writebacks
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                 1962.780232                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks      17.466765                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data      219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst      267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data      219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000267                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.029950                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024         2932                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1088                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1836                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    39936                       # Number of tag accesses
-system.l2c.tags.data_accesses                   39936                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks          116                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total             116                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          608                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             608                       # number of WritebackClean hits
-system.l2c.ReadCleanReq_hits::cpu0.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total               36                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          403                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst          403                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data          315                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          315                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data          315                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total           1260                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks          116                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total          116                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks          608                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total          608                       # number of WritebackClean accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          463                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          463                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          463                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data          324                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data          324                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data          324                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data          324                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total         1296                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.870410                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.870410                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.870410                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.870410                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.870410                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.972222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.972222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.972222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.972222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.972222                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3428                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3428    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3428                       # Request fanout histogram
-system.toL2Bus.snoop_filter.tot_requests         4556                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests          852                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty          116                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean          608                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict             128                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 283392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             4556                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   4556    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               4556                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index e6bd082aa..e69de29bb 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,1634 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000734                       # Number of seconds simulated
-sim_ticks                                   733914500                       # Number of ticks simulated
-final_tick                                  733914500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 598517                       # Simulator instruction rate (inst/s)
-host_op_rate                                   598513                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              219630055                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242608                       # Number of bytes of host memory used
-host_seconds                                     3.34                       # Real time elapsed on the host
-sim_insts                                     1999973                       # Number of instructions simulated
-sim_ops                                       1999973                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst            25792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data            29056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               219392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst        25792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          103168                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            39590443                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            39590443                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            39590443                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst            35143058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data            39590443                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               298934004                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst       35143058                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          140572233                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst           35143058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data           39590443                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              298934004                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                      124435                       # DTB read hits
-system.cpu0.dtb.read_misses                         8                       # DTB read misses
-system.cpu0.dtb.read_acv                            0                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu0.dtb.write_hits                      56340                       # DTB write hits
-system.cpu0.dtb.write_misses                       10                       # DTB write misses
-system.cpu0.dtb.write_acv                           0                       # DTB write access violations
-system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
-system.cpu0.dtb.data_hits                      180775                       # DTB hits
-system.cpu0.dtb.data_misses                        18                       # DTB misses
-system.cpu0.dtb.data_acv                            0                       # DTB access violations
-system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
-system.cpu0.itb.fetch_hits                     500020                       # ITB hits
-system.cpu0.itb.fetch_misses                       13                       # ITB misses
-system.cpu0.itb.fetch_acv                           0                       # ITB acv
-system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                         1467829                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     500001                       # Number of instructions committed
-system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                   1467829                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.Branches                            59023                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu                   300388     60.08%     63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  56350     11.27%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    500019                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements               61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          273.068294                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.068294                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.533337                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.533337                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           723563                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          723563                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     19649000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      8621000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     28270000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     28270000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     28270000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     28270000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu0.dcache.writebacks::total               29                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     27807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     27807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     27807000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     27807000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
-system.cpu0.icache.tags.replacements              152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          216.116668                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             499557                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs          1078.956803                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   216.116668                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.422103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.422103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           500483                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          500483                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       499557                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         499557                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       499557                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          499557                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       499557                       # number of overall hits
-system.cpu0.icache.overall_hits::total         499557                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
-system.cpu0.icache.overall_misses::total          463                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     25776500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     25776500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     25776500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     25776500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     25776500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     25776500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 55672.786177                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 55672.786177                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu0.icache.writebacks::total              152                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     25313500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     25313500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     25313500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     25313500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     25313500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     25313500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177                       # average overall mshr miss latency
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                      124435                       # DTB read hits
-system.cpu1.dtb.read_misses                         8                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu1.dtb.write_hits                      56339                       # DTB write hits
-system.cpu1.dtb.write_misses                       10                       # DTB write misses
-system.cpu1.dtb.write_acv                           0                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu1.dtb.data_hits                      180774                       # DTB hits
-system.cpu1.dtb.data_misses                        18                       # DTB misses
-system.cpu1.dtb.data_acv                            0                       # DTB access violations
-system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
-system.cpu1.itb.fetch_hits                     500014                       # ITB hits
-system.cpu1.itb.fetch_misses                       13                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                 500027                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                         1467829                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     499995                       # Number of instructions committed
-system.cpu1.committedOps                       499995                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               474683                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      474683                       # number of integer instructions
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_int_register_reads             654276                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371538                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                       180792                       # number of memory refs
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_store_insts                     56349                       # Number of store instructions
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                   1467829                       # Number of busy cycles
-system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.Branches                            59022                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu                   300383     60.08%     63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead                  124443     24.89%     88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    500013                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements               61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          273.065457                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   273.065457                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.533331                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.533331                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           723559                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          723559                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        56200                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       180311                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       180311                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         180311                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     19649000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      8621500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      8621500                       # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     28270500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     28270500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     28270500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     28270500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 62025.179856                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856                       # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 61059.395248                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu1.dcache.writebacks::total               29                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      8482500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      8482500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     27807500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total     27807500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     27807500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total     27807500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 59645.061728                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61025.179856                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 61025.179856                       # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
-system.cpu1.icache.tags.replacements              152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          216.114546                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             499551                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs          1078.943844                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   216.114546                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.422099                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.422099                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           500477                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          500477                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       499551                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         499551                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       499551                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          499551                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       499551                       # number of overall hits
-system.cpu1.icache.overall_hits::total         499551                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
-system.cpu1.icache.overall_misses::total          463                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     25783000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     25783000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     25783000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     25783000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     25783000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     25783000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       500014                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       500014                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       500014                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       500014                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       500014                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       500014                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 55686.825054                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 55686.825054                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 55686.825054                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 55686.825054                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 55686.825054                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 55686.825054                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu1.icache.writebacks::total              152                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     25320000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     25320000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     25320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     25320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     25320000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     25320000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054                       # average overall mshr miss latency
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                      124435                       # DTB read hits
-system.cpu2.dtb.read_misses                         8                       # DTB read misses
-system.cpu2.dtb.read_acv                            0                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
-system.cpu2.dtb.write_hits                      56339                       # DTB write hits
-system.cpu2.dtb.write_misses                       10                       # DTB write misses
-system.cpu2.dtb.write_acv                           0                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu2.dtb.data_hits                      180774                       # DTB hits
-system.cpu2.dtb.data_misses                        18                       # DTB misses
-system.cpu2.dtb.data_acv                            0                       # DTB access violations
-system.cpu2.dtb.data_accesses                  180792                       # DTB accesses
-system.cpu2.itb.fetch_hits                     500009                       # ITB hits
-system.cpu2.itb.fetch_misses                       13                       # ITB misses
-system.cpu2.itb.fetch_acv                           0                       # ITB acv
-system.cpu2.itb.fetch_accesses                 500022                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                         1467829                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     499990                       # Number of instructions committed
-system.cpu2.committedOps                       499990                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               474678                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      474678                       # number of integer instructions
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_int_register_reads             654270                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371533                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                       180791                       # number of memory refs
-system.cpu2.num_load_insts                     124442                       # Number of load instructions
-system.cpu2.num_store_insts                     56349                       # Number of store instructions
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                   1467829                       # Number of busy cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.Branches                            59022                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu                   300379     60.07%     63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead                  124442     24.89%     88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    500008                       # Class of executed instruction
-system.cpu2.dcache.tags.replacements               61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse          273.062707                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data   273.062707                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.533326                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.533326                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           723559                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          723559                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        56200                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data       180311                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data       180311                       # number of overall hits
-system.cpu2.dcache.overall_hits::total         180311                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     19649000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total     19649000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      8621000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     28270000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     28270000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     28270000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     28270000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data       180774                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data       180774                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 60645.061728                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 62021.582734                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 61058.315335                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu2.dcache.writebacks::total               29                       # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total     19325000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     27807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total     27807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     27807000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total     27807000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 59645.061728                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335                       # average overall mshr miss latency
-system.cpu2.icache.tags.replacements              152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse          216.112416                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             499546                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs          1078.933045                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   216.112416                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.422095                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.422095                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           500472                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          500472                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       499546                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         499546                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       499546                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          499546                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       499546                       # number of overall hits
-system.cpu2.icache.overall_hits::total         499546                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
-system.cpu2.icache.overall_misses::total          463                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     25788500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     25788500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     25788500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     25788500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     25788500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     25788500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       500009                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       500009                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       500009                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       500009                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       500009                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       500009                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 55698.704104                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 55698.704104                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 55698.704104                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 55698.704104                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 55698.704104                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu2.icache.writebacks::total              152                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     25325500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     25325500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     25325500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     25325500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     25325500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     25325500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104                       # average overall mshr miss latency
-system.cpu3.dtb.fetch_hits                          0                       # ITB hits
-system.cpu3.dtb.fetch_misses                        0                       # ITB misses
-system.cpu3.dtb.fetch_acv                           0                       # ITB acv
-system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu3.dtb.read_hits                      124433                       # DTB read hits
-system.cpu3.dtb.read_misses                         8                       # DTB read misses
-system.cpu3.dtb.read_acv                            0                       # DTB read access violations
-system.cpu3.dtb.read_accesses                  124441                       # DTB read accesses
-system.cpu3.dtb.write_hits                      56339                       # DTB write hits
-system.cpu3.dtb.write_misses                       10                       # DTB write misses
-system.cpu3.dtb.write_acv                           0                       # DTB write access violations
-system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
-system.cpu3.dtb.data_hits                      180772                       # DTB hits
-system.cpu3.dtb.data_misses                        18                       # DTB misses
-system.cpu3.dtb.data_acv                            0                       # DTB access violations
-system.cpu3.dtb.data_accesses                  180790                       # DTB accesses
-system.cpu3.itb.fetch_hits                     500006                       # ITB hits
-system.cpu3.itb.fetch_misses                       13                       # ITB misses
-system.cpu3.itb.fetch_acv                           0                       # ITB acv
-system.cpu3.itb.fetch_accesses                 500019                       # ITB accesses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.read_acv                            0                       # DTB read access violations
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.write_acv                           0                       # DTB write access violations
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.data_hits                           0                       # DTB hits
-system.cpu3.itb.data_misses                         0                       # DTB misses
-system.cpu3.itb.data_acv                            0                       # DTB access violations
-system.cpu3.itb.data_accesses                       0                       # DTB accesses
-system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                         1467829                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     499987                       # Number of instructions committed
-system.cpu3.committedOps                       499987                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               474675                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      474675                       # number of integer instructions
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_int_register_reads             654265                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371530                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                       180790                       # number of memory refs
-system.cpu3.num_load_insts                     124441                       # Number of load instructions
-system.cpu3.num_store_insts                     56349                       # Number of store instructions
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                   1467829                       # Number of busy cycles
-system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.Branches                            59022                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                18814      3.76%      3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu                   300377     60.07%     63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult                      10      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                     10      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      2      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     2      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead                  124441     24.89%     88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  56349     11.27%    100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    500005                       # Class of executed instruction
-system.cpu3.dcache.tags.replacements               61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse          273.059955                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs             180309                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs           389.436285                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data   273.059955                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.533320                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.533320                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           723551                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          723551                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data       124109                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total         124109                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        56200                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data       180309                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total          180309                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data       180309                       # number of overall hits
-system.cpu3.dcache.overall_hits::total         180309                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     19649500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total     19649500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      8621000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      8621000                       # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     28270500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     28270500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     28270500                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     28270500                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data       180772                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total       180772                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data       180772                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total       180772                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.002604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.002467                       # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 62021.582734                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734                       # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 61059.395248                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
-system.cpu3.dcache.writebacks::total               29                       # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     19325500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total     19325500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      8482000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     27807500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total     27807500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     27807500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total     27807500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002467                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 59646.604938                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 59646.604938                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 61021.582734                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734                       # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 60059.395248                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248                       # average overall mshr miss latency
-system.cpu3.icache.tags.replacements              152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse          216.110261                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             499543                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs          1078.926566                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst   216.110261                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.422090                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.422090                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           500469                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          500469                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       499543                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         499543                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       499543                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          499543                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       499543                       # number of overall hits
-system.cpu3.icache.overall_hits::total         499543                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
-system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     25793000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     25793000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     25793000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     25793000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     25793000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     25793000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       500006                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       500006                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       500006                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       500006                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       500006                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       500006                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.000926                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 55708.423326                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 55708.423326                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 55708.423326                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 55708.423326                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 55708.423326                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 55708.423326                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          152                       # number of writebacks
-system.cpu3.icache.writebacks::total              152                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     25330000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     25330000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     25330000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     25330000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     25330000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     25330000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 54708.423326                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326                       # average overall mshr miss latency
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                 1940.317854                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks      17.170012                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      264.661885                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data      216.132475                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      264.659128                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      216.130297                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      264.656363                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      216.128138                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst      264.653570                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data      216.125986                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000262                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.004038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.003298                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.003298                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.004038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.003298                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.004038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.003298                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2904                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
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-system.l2c.tags.data_accesses                   39936                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks          116                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total             116                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          608                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             608                       # number of WritebackClean hits
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-system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
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-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
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-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
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-system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
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-system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
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-system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      8272000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data      8272500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      8272000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      8272500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     33089000                       # number of ReadExReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::cpu1.inst     23989500                       # number of ReadCleanReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::cpu3.inst     24001000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     95970000                       # number of ReadCleanReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.data     18743500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data     18743500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data     18744000                       # number of ReadSharedReq miss cycles
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-system.l2c.demand_miss_latency::cpu2.data     27015500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst     24001000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data     27016500                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu1.data     27016000                       # number of overall miss cycles
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-system.l2c.WritebackDirty_accesses::total          116                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
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-system.l2c.demand_avg_miss_latency::cpu1.data 59506.607930                       # average overall miss latency
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-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
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-system.l2c.overall_mshr_misses::cpu0.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst          403                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data          454                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total            3428                       # number of overall MSHR misses
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6882000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      6882500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      6882000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      6882500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total     27529000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     19954000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     19959500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst     19965500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst     19971000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     79850000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data     15593500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     15593500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data     15593500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data     15594000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total     62374500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     19954000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     22475500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     19959500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data     22476000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst     19965500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data     22475500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst     19971000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data     22476500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total    169753500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     19954000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     22475500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     19959500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data     22476000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst     19965500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data     22475500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst     19971000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data     22476500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total    169753500                       # number of overall MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.870410                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.972222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.925486                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.925486                       # mshr miss rate for overall accesses
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49510.791367                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49514.388489                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49510.791367                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49514.388489                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 49512.589928                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49534.739454                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49503.174603                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49503.174603                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49503.174603                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49504.761905                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49503.571429                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49505.506608                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49506.607930                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49505.506608                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49507.709251                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 49519.690782                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49513.647643                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49505.506608                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49527.295285                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49506.607930                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49542.183623                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 49519.690782                       # average overall mshr miss latency
-system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  219392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3442                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3442    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3442                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             3471468                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           17140000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         4556                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests          852                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty          116                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean          608                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict             128                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        39360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 283392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3704                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   3704    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3704                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            3002000                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            694500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index d462b7494..e69de29bb 100644
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,152 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.199332                       # Number of seconds simulated
-sim_ticks                                199332411500                       # Number of ticks simulated
-final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1276946                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1276946                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              638473293                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226984                       # Number of bytes of host memory used
-host_seconds                                   312.20                       # Real time elapsed on the host
-sim_insts                                   398664595                       # Number of instructions simulated
-sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1594658604                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         662449271                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           2257107875                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1594658604                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1594658604                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data      492356798                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         492356798                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          398664651                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           94754489                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             493419140                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          73520729                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             73520729                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999996548                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           3323339471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11323336020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999996548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999996548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          2470028804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2470028804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999996548                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5793368275                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13793364824                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     94754489                       # DTB read hits
-system.cpu.dtb.read_misses                         21                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 94754510                       # DTB read accesses
-system.cpu.dtb.write_hits                    73520729                       # DTB write hits
-system.cpu.dtb.write_misses                        35                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73520764                       # DTB write accesses
-system.cpu.dtb.data_hits                    168275218                       # DTB hits
-system.cpu.dtb.data_misses                         56                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168275274                       # DTB accesses
-system.cpu.itb.fetch_hits                   398664651                       # ITB hits
-system.cpu.itb.fetch_misses                       173                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               398664824                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   398664595                       # Number of instructions committed
-system.cpu.committedOps                     398664595                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             316365907                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
-system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     25997787                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    316365907                       # number of integer instructions
-system.cpu.num_fp_insts                     155295119                       # number of float instructions
-system.cpu.num_int_register_reads           372938760                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          159335860                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     168275274                       # number of memory refs
-system.cpu.num_load_insts                    94754510                       # Number of load instructions
-system.cpu.num_store_insts                   73520764                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  398664824                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          44587532                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
-system.cpu.op_class::IntAlu                 141652555     35.53%     41.33% # Class of executed instruction
-system.cpu.op_class::IntMult                  2124322      0.53%     41.86% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     41.86% # Class of executed instruction
-system.cpu.op_class::FloatAdd                35620060      8.93%     50.80% # Class of executed instruction
-system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
-system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv                 1563283      0.39%     57.79% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::MemRead                 94754510     23.77%     81.56% # Class of executed instruction
-system.cpu.op_class::MemWrite                73520764     18.44%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  398664651                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           493419140                       # Transaction distribution
-system.membus.trans_dist::ReadResp          493419140                       # Transaction distribution
-system.membus.trans_dist::WriteReq           73520729                       # Transaction distribution
-system.membus.trans_dist::WriteResp          73520729                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    797329302                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    336550436                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             1133879738                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1594658604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1154806069                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2749464673                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         566939869                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.703187                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.456853                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0               168275218     29.68%     29.68% # Request fanout histogram
-system.membus.snoop_fanout::1               398664651     70.32%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           566939869                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index d612f6415..e69de29bb 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,2892 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000126                       # Number of seconds simulated
-sim_ticks                                   125889000                       # Number of ticks simulated
-final_tick                                  125889000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 196054                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196054                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               21072637                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267156                       # Number of bytes of host memory used
-host_seconds                                     5.97                       # Real time elapsed on the host
-sim_insts                                     1171234                       # Number of instructions simulated
-sim_ops                                       1171234                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            24000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             1536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data              896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             5824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                45696                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        24000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         1536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         5824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           31616                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               375                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                24                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                14                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                91                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                21                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   714                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           190644139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            86425343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            12201225                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             7117381                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            46262978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            10676072                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             2033537                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7625766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               362986440                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      190644139                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       12201225                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       46262978                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        2033537                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          251141879                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          190644139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           86425343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           12201225                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            7117381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           46262978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           10676072                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            2033537                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7625766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              362986440                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           714                       # Number of read requests accepted
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         714                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    45696                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     45696                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  45                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  34                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  62                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  68                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 69                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 19                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       125655000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     714                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          181                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      245.392265                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     162.885057                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     238.848920                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             70     38.67%     38.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           41     22.65%     61.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           29     16.02%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           15      8.29%     85.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            9      4.97%     90.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            7      3.87%     94.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      1.66%     96.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      1.10%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      2.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            181                       # Bytes accessed per row activation
-system.physmem.totQLat                        8022250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  21409750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      3570000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11235.64                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29985.64                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         362.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      362.99                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.84                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.84                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        529                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       175987.39                       # Average gap between requests
-system.physmem.pageHitRate                      74.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     914760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     499125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   3088800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                8136960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               61236810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy               21187500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 95063955                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              761.486343                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE       34878500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF         4160000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        85815250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     453600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     247500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2324400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                8136960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               43234785                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               36978750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 91375995                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              731.944849                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE       61171750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF         4160000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        59522000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups                  99978                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            95393                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1592                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               97255                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                   1133                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups          97255                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits             89772                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses            7483                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted         1066                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          251779                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             22796                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        589750                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      99978                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             90905                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       197463                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3483                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                        64                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         2183                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                     8051                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  854                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples            224259                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.629772                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.263592                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   34588     15.42%     15.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   92788     41.38%     56.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     690      0.31%     57.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1001      0.45%     57.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     509      0.23%     57.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   88318     39.38%     97.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     733      0.33%     97.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     501      0.22%     97.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    5131      2.29%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              224259                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.397086                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.342332                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17767                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                19916                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   184006                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  829                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  1741                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                571897                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  1741                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18447                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   2370                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         16226                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   184143                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                 1332                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                566816                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents                   855                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             387804                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups              1129387                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          853087                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups                2                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps               368443                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   19361                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts              1077                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts          1101                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     5304                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              180818                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              91318                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            88191                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           87908                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    472586                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded               1109                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   468485                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              119                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          16710                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        13548                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           550                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       224259                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.089035                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.110026                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              37572     16.75%     16.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4453      1.99%     18.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              89499     39.91%     58.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              89119     39.74%     98.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1731      0.77%     99.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                984      0.44%     99.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                574      0.26%     99.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                227      0.10%     99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                100      0.04%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         224259                       # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                    140     42.68%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     42.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    69     21.04%     63.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  119     36.28%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               197740     42.21%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              180204     38.47%     80.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              90541     19.33%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                468485                       # Type of FU issued
-system.cpu0.iq.rate                          1.860699                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        328                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000700                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1161676                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           490453                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       465867                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                468813                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           87651                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         3007                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1906                       # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           11                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  1741                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   2371                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             562514                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              182                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               180818                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               91318                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               990                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           236                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1703                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1939                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               466997                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               179835                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1488                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        88819                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      270170                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   92803                       # Number of branches executed
-system.cpu0.iew.exec_stores                     90335                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.854789                       # Inst execution rate
-system.cpu0.iew.wb_sent                        466340                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       465867                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   276291                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   279830                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      1.850301                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.987353                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts          17414                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1592                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       220844                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.467878                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.142709                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        37532     16.99%     16.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        91545     41.45%     58.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2011      0.91%     59.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          623      0.28%     59.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          506      0.23%     59.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        87423     39.59%     99.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          455      0.21%     99.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          281      0.13%     99.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          468      0.21%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       220844                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              545016                       # Number of instructions committed
-system.cpu0.commit.committedOps                545016                       # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        267223                       # Number of memory references committed
-system.cpu0.commit.loads                       177811                       # Number of loads committed
-system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     91299                       # Number of branches committed
-system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   366774                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        88031     16.15%     16.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          189678     34.80%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         177895     32.64%     83.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         89412     16.41%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           545016                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events                  468                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                      781645                       # The number of ROB reads
-system.cpu0.rob.rob_writes                    1128336                       # The number of ROB writes
-system.cpu0.timesIdled                            327                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          27520                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     456901                       # Number of Instructions Simulated
-system.cpu0.committedOps                       456901                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.551058                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.551058                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.814691                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.814691                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  834795                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 376287                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 272308                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          143.015419                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             180238                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs          1047.895349                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   143.015419                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.279327                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.279327                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           726286                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          726286                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        91504                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          91504                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        88818                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         88818                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           19                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       180322                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          180322                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       180322                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         180322                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          576                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          576                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          552                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          552                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           23                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           23                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1128                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1128                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1128                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1128                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     18232000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     18232000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     36205990                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     36205990                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       589500                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       589500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     54437990                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     54437990                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     54437990                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     54437990                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        92080                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        92080                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        89370                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        89370                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       181450                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       181450                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       181450                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       181450                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006255                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.006255                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006177                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006177                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.547619                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.547619                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006217                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006217                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006217                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006217                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31652.777778                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31652.777778                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65590.561594                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 65590.561594                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 25630.434783                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 25630.434783                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48260.629433                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 48260.629433                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          818                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.181818                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          380                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          380                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          386                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          386                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          766                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          766                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          766                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          766                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          196                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          196                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          166                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          166                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           23                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           23                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7598500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7598500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8576000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8576000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       566500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       566500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     16174500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     16174500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     16174500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     16174500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002129                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002129                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001857                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001857                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.547619                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.547619                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.001995                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.001995                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.001995                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.001995                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38767.857143                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38767.857143                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
-system.cpu0.icache.tags.replacements              403                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          251.059263                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               7130                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              705                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.113475                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   251.059263                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.490350                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.490350                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.589844                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             8756                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            8756                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         7130                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           7130                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         7130                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            7130                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         7130                       # number of overall hits
-system.cpu0.icache.overall_hits::total           7130                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          921                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          921                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          921                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           921                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          921                       # number of overall misses
-system.cpu0.icache.overall_misses::total          921                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     43922000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     43922000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     43922000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     43922000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     43922000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     43922000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         8051                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         8051                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         8051                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         8051                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         8051                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         8051                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.114396                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.114396                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.114396                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.114396                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.114396                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.114396                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47689.467970                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47689.467970                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47689.467970                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47689.467970                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47689.467970                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs          113                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    28.250000                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          403                       # number of writebacks
-system.cpu0.icache.writebacks::total              403                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          215                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          215                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          215                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          215                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          215                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          706                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          706                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          706                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          706                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          706                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          706                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     33748500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     33748500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     33748500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     33748500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     33748500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     33748500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087691                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.087691                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087691                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.087691                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
-system.cpu1.branchPred.lookups                  75929                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            68631                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             2222                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               68395                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                   1839                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups          68395                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits             58396                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses            9999                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted         1194                       # Number of mispredicted indirect branches.
-system.cpu1.numCycles                          196540                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             32617                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        424540                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      75929                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             60235                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       157282                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   4599                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles         1756                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    22091                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  889                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            193967                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             2.188723                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.372433                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   56525     29.14%     29.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   66630     34.35%     63.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    5516      2.84%     66.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3688      1.90%     68.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     688      0.35%     68.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   50225     25.89%     94.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1136      0.59%     95.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                    1351      0.70%     95.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    8208      4.23%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              193967                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.386328                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       2.160069                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   20990                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                50963                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                   116406                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 3299                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2299                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                394135                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2299                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   22042                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  22361                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         14616                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                   117990                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                14649                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                387817                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                 13215                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                    19                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.RenamedOperands             272713                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               753683                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          582463                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups               32                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps               245854                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   26859                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1602                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1739                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    20098                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads              111716                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              54519                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            52739                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           48254                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    321016                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               5993                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   319557                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          23622                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        18296                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved          1159                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       193967                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.647481                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.362491                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              60994     31.45%     31.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              19742     10.18%     41.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              53241     27.45%     69.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              52847     27.25%     96.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3638      1.88%     98.19% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1763      0.91%     99.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6               1052      0.54%     99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                407      0.21%     99.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                283      0.15%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         193967                       # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                    169     37.31%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     37.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    58     12.80%     50.11% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  226     49.89%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               151236     47.33%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead              114807     35.93%     83.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              53514     16.75%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                319557                       # Type of FU issued
-system.cpu1.iq.rate                          1.625913                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        453                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001418                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            833588                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           350606                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       315974                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                320010                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           48132                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         4290                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses           32                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         2608                       # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2299                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   7227                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   50                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             380950                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              338                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts               111716                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               54519                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1500                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           429                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         2382                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                2811                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               317250                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts               110168                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             2307                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        53941                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      163396                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   64160                       # Number of branches executed
-system.cpu1.iew.exec_stores                     53228                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.614175                       # Inst execution rate
-system.cpu1.iew.wb_sent                        316458                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       315974                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   181395                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   189019                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      1.607683                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.959665                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts          24733                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           4834                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             2222                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       189334                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.881189                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.115429                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        65341     34.51%     34.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        60499     31.95%     66.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5361      2.83%     69.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         5469      2.89%     72.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1297      0.69%     72.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        48347     25.54%     98.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          750      0.40%     98.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7         1038      0.55%     99.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8         1232      0.65%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       189334                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              356173                       # Number of instructions committed
-system.cpu1.commit.committedOps                356173                       # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        159337                       # Number of memory references committed
-system.cpu1.commit.loads                       107426                       # Number of loads committed
-system.cpu1.commit.membars                       4118                       # Number of memory barriers committed
-system.cpu1.commit.branches                     61998                       # Number of branches committed
-system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   243452                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        52786     14.82%     14.82% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          139932     39.29%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead         111544     31.32%     85.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         51911     14.57%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           356173                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                 1232                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                      568422                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     766486                       # The number of ROB writes
-system.cpu1.timesIdled                            207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2573                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       46533                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     299269                       # Number of Instructions Simulated
-system.cpu1.committedOps                       299269                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.656734                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.656734                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.522687                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.522687                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  554283                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 257020                       # number of integer regfile writes
-system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 165298                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           25.915239                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              58936                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          2032.275862                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.915239                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050616                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.050616                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           455882                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          455882                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        61472                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          61472                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        51691                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         51691                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           10                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       113163                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          113163                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       113163                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         113163                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          523                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          523                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          150                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          150                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           60                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          673                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           673                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          673                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          673                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8464500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      8464500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2960500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      2960500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       828000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       828000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     11425000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     11425000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     11425000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     11425000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        61995                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        61995                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        51841                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        51841                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       113836                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       113836                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       113836                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       113836                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008436                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.008436                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002893                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.002893                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.857143                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.857143                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005912                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005912                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005912                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005912                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16184.512428                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16184.512428                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19736.666667                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19736.666667                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data        13800                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total        13800                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16976.225854                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16976.225854                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          362                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          362                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           43                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           43                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          405                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          405                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          405                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          405                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          161                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           60                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           60                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          268                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          268                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1530000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1530000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1517000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1517000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       768000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       768000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3047000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3047000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002597                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002597                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002064                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002064                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.857143                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.857143                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002354                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.002354                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002354                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.002354                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9503.105590                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9503.105590                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data        12800                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total        12800                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
-system.cpu1.icache.tags.replacements              548                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           97.609803                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              21265                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              682                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            31.180352                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.609803                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190644                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.190644                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.261719                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            22773                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           22773                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        21265                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          21265                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        21265                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           21265                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        21265                       # number of overall hits
-system.cpu1.icache.overall_hits::total          21265                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          826                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          826                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          826                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           826                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          826                       # number of overall misses
-system.cpu1.icache.overall_misses::total          826                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     13533000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     13533000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     13533000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     13533000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     13533000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     13533000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        22091                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        22091                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        22091                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        22091                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        22091                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        22091                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037391                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037391                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037391                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037391                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037391                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037391                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16383.777240                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 16383.777240                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16383.777240                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 16383.777240                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 16383.777240                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks          548                       # number of writebacks
-system.cpu1.icache.writebacks::total              548                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          144                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst          144                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total          144                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst          144                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total          144                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          682                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          682                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          682                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          682                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          682                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          682                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     10822000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     10822000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     10822000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     10822000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     10822000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     10822000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030872                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.030872                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030872                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.030872                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
-system.cpu2.branchPred.lookups                  65577                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            57724                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             2464                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               57712                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                   1983                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups          57712                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits             46848                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses           10864                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted         1379                       # Number of mispredicted indirect branches.
-system.cpu2.numCycles                          195641                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             39175                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        357136                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      65577                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             48831                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       146036                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   5085                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         2246                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles           31                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                    27545                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  945                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            190045                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.879218                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.350973                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   72125     37.95%     37.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   57864     30.45%     68.40% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    8007      4.21%     72.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3378      1.78%     74.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     697      0.37%     74.76% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   36524     19.22%     93.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1219      0.64%     94.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                    1446      0.76%     95.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    8785      4.62%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              190045                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.335190                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.825466                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   23115                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                69586                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    90388                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 4404                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2542                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                325134                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2542                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   24144                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  33213                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         15151                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    91754                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                23231                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                318523                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                 20453                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands             223607                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               605589                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          472031                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               26                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps               193721                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   29886                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1685                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1831                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    29018                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               87037                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              41099                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            41296                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           34595                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    259686                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               8253                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   260132                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued              104                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          25858                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        19408                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved          1214                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       190045                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.368792                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.393545                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              77002     40.52%     40.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              26562     13.98%     54.49% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              39729     20.91%     75.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              39504     20.79%     96.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3584      1.89%     98.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1794      0.94%     99.02% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6               1114      0.59%     99.60% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                438      0.23%     99.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                318      0.17%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         190045                       # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                    198     41.51%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     41.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    44      9.22%     50.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  235     49.27%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               127776     49.12%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               92295     35.48%     84.60% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              40061     15.40%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                260132                       # Type of FU issued
-system.cpu2.iq.rate                          1.329639                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        477                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001834                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            710890                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           293781                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       256087                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                52                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                260609                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           34538                       # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         4572                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses           34                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         2770                       # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2542                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   9787                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             310555                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              374                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                87037                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               41099                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1544                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            36                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           461                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         2649                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                3110                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               257554                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                85462                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             2578                       # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        42616                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      125205                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   53054                       # Number of branches executed
-system.cpu2.iew.exec_stores                     39743                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.316462                       # Inst execution rate
-system.cpu2.iew.wb_sent                        256619                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       256087                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   143359                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   151246                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.308964                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.947853                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts          27054                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           7039                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             2464                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       184962                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.532661                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.012592                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        83513     45.15%     45.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        49247     26.63%     71.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5539      2.99%     74.77% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         7621      4.12%     78.89% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1289      0.70%     79.59% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        34776     18.80%     98.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          735      0.40%     98.79% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1086      0.59%     99.38% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8         1156      0.62%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       184962                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              283484                       # Number of instructions committed
-system.cpu2.commit.committedOps                283484                       # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        120794                       # Number of memory references committed
-system.cpu2.commit.loads                        82465                       # Number of loads committed
-system.cpu2.commit.membars                       6325                       # Number of memory barriers committed
-system.cpu2.commit.branches                     50613                       # Number of branches committed
-system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   193531                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        41403     14.61%     14.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu          114962     40.55%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          88790     31.32%     86.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         38329     13.52%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           283484                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                 1156                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                      493758                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     626207                       # The number of ROB writes
-system.cpu2.timesIdled                            224                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5596                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       47431                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     235756                       # Number of Instructions Simulated
-system.cpu2.committedOps                       235756                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.829845                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.829845                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.205044                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.205044                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  440950                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 206257                       # number of integer regfile writes
-system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 127194                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.976674                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              45756                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1525.200000                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.976674                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.052689                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.052689                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           357076                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          357076                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        50413                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          50413                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        38109                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         38109                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           15                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        88522                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           88522                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        88522                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          88522                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          463                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          152                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          152                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           53                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          615                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           615                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          615                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          615                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      8046000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      8046000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3843000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3843000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       809500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       809500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     11889000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     11889000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     11889000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     11889000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        50876                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        50876                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        38261                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        38261                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        89137                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        89137                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        89137                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        89137                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009101                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.009101                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003973                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003973                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.779412                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.779412                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006899                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.006899                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006899                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.006899                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17377.969762                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 17377.969762                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25282.894737                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 25282.894737                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15273.584906                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 15273.584906                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19331.707317                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 19331.707317                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          298                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          298                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           47                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
-system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data            5                       # number of SwapReq MSHR hits
-system.cpu2.dcache.SwapReq_mshr_hits::total            5                       # number of SwapReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          345                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          345                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          345                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          345                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          165                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           48                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           48                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          270                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          270                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1997000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1997000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1762500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1762500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       756500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       756500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3759500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3759500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3759500                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3759500                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003243                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003243                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002744                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002744                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.705882                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.705882                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003029                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003029                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003029                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003029                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12103.030303                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12103.030303                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
-system.cpu2.icache.tags.replacements              555                       # number of replacements
-system.cpu2.icache.tags.tagsinuse          101.261159                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              26702                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              694                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            38.475504                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   101.261159                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.197776                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.197776                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          139                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.271484                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            28239                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           28239                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        26702                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          26702                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        26702                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           26702                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        26702                       # number of overall hits
-system.cpu2.icache.overall_hits::total          26702                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          843                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          843                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          843                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           843                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          843                       # number of overall misses
-system.cpu2.icache.overall_misses::total          843                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     19527000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     19527000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     19527000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     19527000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     19527000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     19527000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        27545                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        27545                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        27545                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        27545                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        27545                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        27545                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.030604                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.030604                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.030604                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.030604                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.030604                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.030604                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23163.701068                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23163.701068                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23163.701068                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23163.701068                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23163.701068                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs          220                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                7                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs    31.428571                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          555                       # number of writebacks
-system.cpu2.icache.writebacks::total              555                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          149                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total          149                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst          149                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total          149                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst          149                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total          149                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          694                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          694                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          694                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          694                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          694                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          694                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     15501500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     15501500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     15501500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     15501500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     15501500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     15501500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.025195                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.025195                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.025195                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.025195                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
-system.cpu3.branchPred.lookups                  57182                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            48797                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             2586                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               48362                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
-system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                   2121                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups          48362                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits             37349                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses           11013                       # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted         1473                       # Number of mispredicted indirect branches.
-system.cpu3.numCycles                          195288                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             45700                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        298023                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      57182                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             39470                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       143366                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   5327                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1948                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    34377                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                 1007                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            193690                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.538660                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.252819                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   90820     46.89%     46.89% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   51773     26.73%     73.62% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                   11180      5.77%     79.39% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3385      1.75%     81.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     629      0.32%     81.46% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   24090     12.44%     93.90% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1143      0.59%     94.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                    1449      0.75%     95.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    9221      4.76%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              193690                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.292809                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.526069                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   23670                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                95373                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    66026                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 5948                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2663                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                265184                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2663                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   24704                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  48500                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         15195                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    67410                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                35208                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                258083                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                 30956                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.RenamedOperands             178302                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               471983                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          372133                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups               28                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps               146703                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   31599                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1744                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1884                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    41025                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               65361                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              28681                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            31955                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           22074                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    204469                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded              11525                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   207359                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued              114                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          27267                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        21384                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved          1390                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       193690                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.070572                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.351583                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              96267     49.70%     49.70% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              35951     18.56%     68.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              27208     14.05%     82.31% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              26919     13.90%     96.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3677      1.90%     98.11% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1713      0.88%     98.99% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6               1079      0.56%     99.55% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                520      0.27%     99.82% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                356      0.18%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         193690                       # Number of insts issued each cycle
-system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                    253     45.42%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     45.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    65     11.67%     57.09% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  239     42.91%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               106203     51.22%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     51.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               73580     35.48%     86.70% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              27576     13.30%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                207359                       # Type of FU issued
-system.cpu3.iq.rate                          1.061811                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        557                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.002686                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            609079                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           243241                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       202956                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes                56                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                207916                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           22032                       # Number of loads that had data forwarded from stores
-system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         4860                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses           37                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         2877                       # Number of stores squashed
-system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2663                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                  13076                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   57                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             249222                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              349                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                65361                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               28681                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1596                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    28                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            36                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           455                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         2781                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                3236                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               204483                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                63509                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             2876                       # Number of squashed instructions skipped in execute
-system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        33228                       # number of nop insts executed
-system.cpu3.iew.exec_refs                       90738                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   43690                       # Number of branches executed
-system.cpu3.iew.exec_stores                     27229                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.047084                       # Inst execution rate
-system.cpu3.iew.wb_sent                        203493                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       202956                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   108735                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   116603                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      1.039265                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.932523                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts          28499                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls          10135                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             2586                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       188297                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.172069                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.830514                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0       105729     56.15%     56.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        39844     21.16%     77.31% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         5499      2.92%     80.23% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3        10725      5.70%     85.93% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1244      0.66%     86.59% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        22268     11.83%     98.41% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          755      0.40%     98.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7         1030      0.55%     99.36% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8         1203      0.64%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       188297                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              220697                       # Number of instructions committed
-system.cpu3.commit.committedOps                220697                       # Number of ops (including micro ops) committed
-system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                         86305                       # Number of memory references committed
-system.cpu3.commit.loads                        60501                       # Number of loads committed
-system.cpu3.commit.membars                       9419                       # Number of memory barriers committed
-system.cpu3.commit.branches                     41182                       # Number of branches committed
-system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   149608                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        31970     14.49%     14.49% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu           93003     42.14%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          69920     31.68%     88.31% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         25804     11.69%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           220697                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                 1203                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                      435704                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     503857                       # The number of ROB writes
-system.cpu3.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1598                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       47785                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     179308                       # Number of Instructions Simulated
-system.cpu3.committedOps                       179308                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.089120                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.089120                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.918172                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.918172                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  337868                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 159407                       # number of integer regfile writes
-system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                  92688                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           25.364861                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              33092                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1103.066667                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.364861                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.049541                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.049541                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           269290                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          269290                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        40990                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          40990                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        25593                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         25593                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        66583                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           66583                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        66583                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          66583                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          463                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          463                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          141                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          141                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          604                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           604                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          604                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          604                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      7157000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      7157000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3001000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3001000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       868000                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       868000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     10158000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     10158000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     10158000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     10158000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41453                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41453                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        25734                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        25734                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        67187                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        67187                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        67187                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        67187                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011169                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.011169                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.005479                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.005479                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.785714                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008990                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.008990                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008990                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.008990                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15457.883369                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 15457.883369                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21283.687943                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 21283.687943                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15781.818182                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 15781.818182                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16817.880795                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16817.880795                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          291                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          291                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           35                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
-system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            4                       # number of SwapReq MSHR hits
-system.cpu3.dcache.SwapReq_mshr_hits::total            4                       # number of SwapReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          326                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          326                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          172                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          106                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          278                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          278                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          278                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1798500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1798500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1645500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1645500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       813000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       813000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3444000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3444000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3444000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3444000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004149                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004149                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.004119                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.004119                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.728571                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.728571                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004138                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.004138                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004138                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.004138                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10456.395349                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10456.395349                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
-system.cpu3.icache.tags.replacements              608                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           93.738869                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              33506                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              743                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            45.095559                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    93.738869                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.183084                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.183084                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.263672                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            35120                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           35120                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        33506                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          33506                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        33506                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           33506                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        33506                       # number of overall hits
-system.cpu3.icache.overall_hits::total          33506                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          871                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          871                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          871                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           871                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          871                       # number of overall misses
-system.cpu3.icache.overall_misses::total          871                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     11659000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     11659000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     11659000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     11659000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     11659000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     11659000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        34377                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        34377                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        34377                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        34377                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        34377                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        34377                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.025337                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.025337                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.025337                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.025337                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.025337                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.025337                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13385.763490                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13385.763490                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13385.763490                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13385.763490                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13385.763490                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          608                       # number of writebacks
-system.cpu3.icache.writebacks::total              608                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          128                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total          128                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst          128                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total          128                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst          128                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total          128                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          743                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          743                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          743                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          743                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          743                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          743                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     10055000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     10055000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     10055000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     10055000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     10055000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     10055000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021613                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.021613                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021613                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.021613                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  458.562207                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       3097                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      581                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     5.330465                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.811695                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      303.236105                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       58.939439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       17.006196                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        1.379366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       67.599671                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        5.915132                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        1.812120                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        1.862482                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.004627                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000899                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000259                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000021                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.001031                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000090                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000028                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000028                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.006997                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          581                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.008865                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    32091                       # Number of tag accesses
-system.l2c.tags.data_accesses                   32091                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          751                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             751                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst           329                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst           654                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           595                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           735                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total              2313                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data           11                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data            5                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                 329                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 654                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 595                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 735                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    2345                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                329                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                654                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                595                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                735                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   2345                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data            23                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            22                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            24                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                89                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          377                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           28                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst           99                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst            8                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total             512                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data            3                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total             89                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               377                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                28                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                14                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                99                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                21                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                15                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   732                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              377                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               28                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               14                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               99                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               21                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               15                       # number of overall misses
-system.l2c.overall_misses::total                  732                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      7972500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       902000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      1048000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       927000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     10849500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     29037500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst      2384000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst      7728000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst       627500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     39777000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data      6533500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data       165500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data       634500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data       262000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total      7595500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     29037500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     14506000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      2384000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1067500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      7728000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1682500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       627500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1189000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        58222000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     29037500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     14506000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      2384000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1067500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      7728000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1682500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       627500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1189000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       58222000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks          751                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total          751                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           26                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           24                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              92                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          706                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          682                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          694                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst          743                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          2825                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data           13                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data           13                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data           14                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total          121                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             706                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             682                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             743                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3077                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total               3077                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.884615                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.967391                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
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-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.533994                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.041056                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.142651                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010767                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.181239                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.153846                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.615385                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.214286                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.735537                       # miss rate for ReadSharedReq accesses
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-system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.560000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.142651                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.807692                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.010767                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.576923                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.237894                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.533994                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.041056                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.560000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.142651                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.807692                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.010767                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.576923                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.237894                       # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84813.829787                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75166.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80615.384615                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data        77250                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 82820.610687                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 78437.500000                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 77689.453125                       # average ReadCleanReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        82750                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 79312.500000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 87333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 85342.696629                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 77022.546419                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 85329.411765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85142.857143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data        76250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 78060.606061                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 80119.047619                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 78437.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 79266.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 79538.251366                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 77022.546419                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 85329.411765                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data        76250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 78060.606061                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 80119.047619                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 78437.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 79266.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 79538.251366                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            8                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           17                       # number of ReadCleanReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           23                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           22                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           24                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           89                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          376                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           24                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           91                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            4                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total          495                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data            8                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data            3                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total           89                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          376                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           24                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data           14                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst           91                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           21                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              715                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          376                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           24                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data           14                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst           91                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data           21                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             715                       # number of overall MSHR misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       437500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       380000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       419000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       457000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      1693500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      7032500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       782000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       918000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       807000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      9539500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     25253500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      1934500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      6358500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       309500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     33856000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5773500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       145500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       554500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       232000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total      6705500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     25253500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     12806000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      1934500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       927500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      6358500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1472500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       309500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data      1039000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     50101000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     25253500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     12806000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      1934500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       927500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      6358500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1472500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       309500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data      1039000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     50101000                       # number of overall MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.884615                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.967391                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.175221                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.615385                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.735537                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.560000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.807692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.232369                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.532578                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.035191                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.560000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.131124                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.807692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005384                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.232369                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19021.739130                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19045.454545                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19041.666667                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19028.089888                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74813.829787                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65166.666667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70615.384615                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        67250                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72820.610687                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        77375                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68395.959596                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 75967.105263                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        72750                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 69312.500000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 77333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75342.696629                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75329.411765                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        66250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70119.047619                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        77375                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69266.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70071.328671                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67163.563830                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        66250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        77375                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70071.328671                       # average overall mshr miss latency
-system.membus.trans_dist::ReadResp                583                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              286                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           583                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1765                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1765                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   45696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              248                       # Total snoops (count)
-system.membus.snoop_fanout::samples              1051                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    1051    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                1051                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              998006                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3803500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         6324                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1712                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3265                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              3513                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            6                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean         2114                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             289                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            289                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              399                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             399                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          2825                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          695                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1814                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          602                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1912                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1943                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          371                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2094                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          383                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  9492                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        70912                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        78720                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        79936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 332224                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1039                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             4208                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.288736                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.116485                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1347     32.01%     32.01% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   1142     27.14%     59.15% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    876     20.82%     79.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    843     20.03%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               4208                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            5296461                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              4.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           1058997                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            523496                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1025493                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            437958                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1044987                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            431472                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1116994                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            444965                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index f2280533e..e69de29bb 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,991 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000088                       # Number of seconds simulated
-sim_ticks                                    87707000                       # Number of ticks simulated
-final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1039500                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1039462                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              134594380                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262812                       # Number of bytes of host memory used
-host_seconds                                     0.65                       # Real time elapsed on the host
-sim_insts                                      677333                       # Number of instructions simulated
-sim_ops                                        677333                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            18048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             3968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst               64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                35776                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        18048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         3968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst           64                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22272                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               282                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                62                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   559                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205776050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           120400880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            45241543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            14594046                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             2189107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             9486130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              729702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             9486130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               407903588                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205776050                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       45241543                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        2189107                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         729702                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          253936402                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205776050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          120400880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           45241543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           14594046                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            2189107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             729702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              407903588                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          175415                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     175326                       # Number of instructions committed
-system.cpu0.committedOps                       175326                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               120376                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        28824                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      120376                       # number of integer instructions
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             349286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            121983                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        82397                       # number of memory refs
-system.cpu0.num_load_insts                      54591                       # Number of load instructions
-system.cpu0.num_store_insts                     27806                       # Number of store instructions
-system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
-system.cpu0.num_busy_cycles              175414.998000                       # Number of busy cycles
-system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
-system.cpu0.Branches                            29689                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                26416     15.06%     15.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                    66491     37.91%     52.97% # Class of executed instruction
-system.cpu0.op_class::IntMult                       0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     52.97% # Class of executed instruction
-system.cpu0.op_class::MemRead                   54675     31.17%     84.15% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  27806     15.85%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    175388                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          150.745705                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs              81882                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           490.311377                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   150.745705                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.294425                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.294425                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           329804                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          329804                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        54430                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          54430                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         27578                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           15                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        82008                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           82008                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        82008                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          82008                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          151                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          177                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          177                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           27                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           27                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          328                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           328                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          328                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          328                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        54581                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        54581                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        27755                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        27755                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        82336                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        82336                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        82336                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        82336                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002767                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002767                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006377                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006377                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.642857                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.642857                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.003984                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.003984                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.003984                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.003984                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          222.772732                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           374.563169                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772732                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           175855                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          175855                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          174921                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       174921                       # number of overall hits
-system.cpu0.icache.overall_hits::total         174921                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       175388                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       175388                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       175388                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002663                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002663                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002663                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
-system.cpu0.icache.writebacks::total              215                       # number of writebacks
-system.cpu1.numCycles                          173297                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     167400                       # Number of instructions committed
-system.cpu1.committedOps                       167400                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               107326                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        34043                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      107326                       # number of integer instructions
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             254436                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes             94218                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        49494                       # number of memory refs
-system.cpu1.num_load_insts                      39345                       # Number of load instructions
-system.cpu1.num_store_insts                     10149                       # Number of store instructions
-system.cpu1.num_idle_cycles               7872.827276                       # Number of idle cycles
-system.cpu1.num_busy_cycles              165424.172724                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.954570                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.045430                       # Percentage of idle cycles
-system.cpu1.Branches                            35694                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                26475     15.81%     15.81% # Class of executed instruction
-system.cpu1.op_class::IntAlu                    71873     42.93%     58.74% # Class of executed instruction
-system.cpu1.op_class::IntMult                       0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     58.74% # Class of executed instruction
-system.cpu1.op_class::MemRead                   58935     35.20%     93.94% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  10149      6.06%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    167432                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           30.295170                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              21529                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               26                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           828.038462                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    30.295170                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.059170                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.059170                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.050781                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           198211                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          198211                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        39152                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          39152                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data         9968                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total          9968                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           16                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        49120                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           49120                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        49120                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          49120                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          185                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          185                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          102                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          102                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           61                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           61                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          287                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           287                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          287                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          287                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        39337                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        39337                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        10070                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        10070                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           77                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           77                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        49407                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        49407                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        49407                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        49407                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004703                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.004703                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.010129                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.010129                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.792208                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.792208                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005809                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005809                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005809                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005809                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.tags.replacements              278                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           76.752158                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             167074                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           466.687151                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.752158                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149907                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.149907                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           167790                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          167790                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       167074                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         167074                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       167074                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          167074                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       167074                       # number of overall hits
-system.cpu1.icache.overall_hits::total         167074                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          358                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          358                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          358                       # number of overall misses
-system.cpu1.icache.overall_misses::total          358                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       167432                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       167432                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       167432                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       167432                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       167432                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       167432                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002138                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002138                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks          278                       # number of writebacks
-system.cpu1.icache.writebacks::total              278                       # number of writebacks
-system.cpu2.numCycles                          173296                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     167335                       # Number of instructions committed
-system.cpu2.committedOps                       167335                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               114196                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        30577                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      114196                       # number of integer instructions
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             295784                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            111461                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        59830                       # number of memory refs
-system.cpu2.num_load_insts                      42793                       # Number of load instructions
-system.cpu2.num_store_insts                     17037                       # Number of store instructions
-system.cpu2.num_idle_cycles               7936.997017                       # Number of idle cycles
-system.cpu2.num_busy_cycles              165359.002983                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.954200                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.045800                       # Percentage of idle cycles
-system.cpu2.Branches                            32221                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                23013     13.75%     13.75% # Class of executed instruction
-system.cpu2.op_class::IntAlu                    75303     44.99%     58.74% # Class of executed instruction
-system.cpu2.op_class::IntMult                       0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     58.74% # Class of executed instruction
-system.cpu2.op_class::MemRead                   52014     31.08%     89.82% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  17037     10.18%    100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    167367                       # Class of executed instruction
-system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           29.575165                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              35457                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               27                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1313.222222                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    29.575165                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.057764                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.057764                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           27                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.052734                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           239521                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          239521                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42635                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42635                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        16864                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         16864                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        59499                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           59499                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        59499                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          59499                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          150                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          150                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          105                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           54                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          255                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           255                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          255                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          255                       # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        42785                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        42785                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        16969                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        16969                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           66                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        59754                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        59754                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        59754                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        59754                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003506                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003506                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006188                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.006188                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.818182                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.818182                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004267                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004267                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004267                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004267                       # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.tags.replacements              278                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           74.781471                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             167009                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           466.505587                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781471                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146058                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.146058                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           167725                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          167725                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       167009                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         167009                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       167009                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          167009                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       167009                       # number of overall hits
-system.cpu2.icache.overall_hits::total         167009                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          358                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          358                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          358                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           358                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          358                       # number of overall misses
-system.cpu2.icache.overall_misses::total          358                       # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       167367                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       167367                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       167367                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       167367                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       167367                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       167367                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002139                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002139                       # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          278                       # number of writebacks
-system.cpu2.icache.writebacks::total              278                       # number of writebacks
-system.cpu3.numCycles                          173297                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     167272                       # Number of instructions committed
-system.cpu3.committedOps                       167272                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               113295                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_func_calls                        633                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        30996                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      113295                       # number of integer instructions
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             290503                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            109270                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        58510                       # number of memory refs
-system.cpu3.num_load_insts                      42344                       # Number of load instructions
-system.cpu3.num_store_insts                     16166                       # Number of store instructions
-system.cpu3.num_idle_cycles               7999.282495                       # Number of idle cycles
-system.cpu3.num_busy_cycles              165297.717505                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.953841                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.046159                       # Percentage of idle cycles
-system.cpu3.Branches                            32639                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                23433     14.01%     14.01% # Class of executed instruction
-system.cpu3.op_class::IntAlu                    74851     44.74%     58.75% # Class of executed instruction
-system.cpu3.op_class::IntMult                       0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     58.75% # Class of executed instruction
-system.cpu3.op_class::MemRead                   52854     31.59%     90.34% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  16166      9.66%    100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    167304                       # Class of executed instruction
-system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           28.848199                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              33595                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               26                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1292.115385                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    28.848199                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.056344                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.056344                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.050781                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           234241                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          234241                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        42185                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          42185                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        15991                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         15991                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        58176                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           58176                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        58176                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          58176                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          151                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          109                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           52                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          260                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           260                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          260                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          260                       # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        42336                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        42336                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        16100                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        16100                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           64                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           64                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        58436                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        58436                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        58436                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        58436                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003567                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003567                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006770                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.006770                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.812500                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.812500                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004449                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.004449                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004449                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.004449                       # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.tags.replacements              279                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           72.874953                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             166945                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              359                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           465.027855                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874953                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142334                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.142334                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           167663                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          167663                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       166945                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         166945                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       166945                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          166945                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       166945                       # number of overall hits
-system.cpu3.icache.overall_hits::total         166945                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          359                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          359                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          359                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           359                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          359                       # number of overall misses
-system.cpu3.icache.overall_misses::total          359                       # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       167304                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       167304                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       167304                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       167304                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       167304                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       167304                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002146                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002146                       # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          279                       # number of writebacks
-system.cpu3.icache.writebacks::total              279                       # number of writebacks
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  367.545675                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1716                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      422                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.066351                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.966439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      239.426226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       56.170311                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       59.512205                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        6.721185                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        1.942787                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.935416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        0.965459                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.905646                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.003653                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000857                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000908                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000103                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000030                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005608                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          422                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          374                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.006439                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    19424                       # Number of tag accesses
-system.l2c.tags.data_accesses                   19424                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          495                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             495                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst           185                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst           296                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           355                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           358                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total              1194                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data            3                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                80                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          282                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           62                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst            3                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst            1                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total             348                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data            7                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total             75                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                3                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                1                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  559                       # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks          495                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total          495                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              82                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          358                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          358                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst          359                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          1542                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data           10                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data           10                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data           10                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total          101                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.975610                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.603854                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.173184                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.008380                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.002786                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.225681                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.700000                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.100000                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.100000                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.742574                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.008380                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.002786                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.008380                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.002786                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.membus.trans_dist::ReadResp                423                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              273                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              80                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               183                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              136                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           423                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1518                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1518                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        35776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   35776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               879                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     879    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 879                       # Request fanout histogram
-system.toL2Bus.snoop_filter.tot_requests         3918                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1709                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              2179                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean         1050                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              412                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             412                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          1542                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          637                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          712                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          696                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          618                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          997                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          624                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  6784                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        43648                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 233088                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3918                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.246554                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.199505                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1485     37.90%     37.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    951     24.27%     62.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    513     13.09%     75.27% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    969     24.73%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3918                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 22d94928b..e69de29bb 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,1638 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000264                       # Number of seconds simulated
-sim_ticks                                   263565500                       # Number of ticks simulated
-final_tick                                  263565500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 821706                       # Simulator instruction rate (inst/s)
-host_op_rate                                   821692                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              326627282                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262816                       # Number of bytes of host memory used
-host_seconds                                     0.81                       # Real time elapsed on the host
-sim_insts                                      663039                       # Number of instructions simulated
-sim_ops                                        663039                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             3456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         3456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                54                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            69204809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            40065942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             2428239                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3642358                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            13112490                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             5342126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1214119                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3885182                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               138895265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       69204809                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        2428239                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       13112490                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1214119                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           85959657                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           69204809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           40065942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            2428239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3642358                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           13112490                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            5342126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1214119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3885182                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              138895265                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          527131                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     158196                       # Number of instructions committed
-system.cpu0.committedOps                       158196                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               108956                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        25969                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      108956                       # number of integer instructions
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             315026                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110562                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        73832                       # number of memory refs
-system.cpu0.num_load_insts                      48881                       # Number of load instructions
-system.cpu0.num_store_insts                     24951                       # Number of store instructions
-system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
-system.cpu0.num_busy_cycles              527130.998000                       # Number of busy cycles
-system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
-system.cpu0.Branches                            26834                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                23561     14.89%     14.89% # Class of executed instruction
-system.cpu0.op_class::IntAlu                    60781     38.41%     53.29% # Class of executed instruction
-system.cpu0.op_class::IntMult                       0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::MemRead                   48965     30.94%     84.23% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  24951     15.77%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    158258                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          145.050771                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs              73302                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           438.934132                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.050771                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.283302                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.283302                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           295559                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          295559                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48703                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48703                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24717                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24717                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73420                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73420                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73420                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73420                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          168                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          168                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          351                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           351                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          351                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          351                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4817500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      4817500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6985500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      6985500                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       395000                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       395000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     11803000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     11803000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     11803000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     11803000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48871                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48871                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24900                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24900                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73771                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73771                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73771                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73771                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003438                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003438                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007349                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007349                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004758                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004758                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004758                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004758                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
-system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          168                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          168                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          351                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4649500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4649500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6802500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6802500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       369000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       369000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11452000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     11452000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11452000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     11452000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003438                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003438                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007349                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007349                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004758                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004758                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004758                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004758                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
-system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          211.380247                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             157792                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           337.884368                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   211.380247                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.412852                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.412852                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           158726                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          158726                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       157792                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         157792                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       157792                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          157792                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       157792                       # number of overall hits
-system.cpu0.icache.overall_hits::total         157792                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     20140500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     20140500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     20140500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     20140500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     20140500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     20140500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       158259                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       158259                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       158259                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       158259                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       158259                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       158259                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002951                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002951                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002951                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002951                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002951                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002951                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 43127.408994                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 43127.408994                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
-system.cpu0.icache.writebacks::total              215                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     19673500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     19673500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     19673500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     19673500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     19673500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     19673500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002951                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002951                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002951                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
-system.cpu1.numCycles                          527130                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     170790                       # Number of instructions committed
-system.cpu1.committedOps                       170790                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               110708                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        34050                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      110708                       # number of integer instructions
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             268858                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            101318                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        52827                       # number of memory refs
-system.cpu1.num_load_insts                      41019                       # Number of load instructions
-system.cpu1.num_store_insts                     11808                       # Number of store instructions
-system.cpu1.num_idle_cycles              73818.861681                       # Number of idle cycles
-system.cpu1.num_busy_cycles              453311.138319                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.859961                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.140039                       # Percentage of idle cycles
-system.cpu1.Branches                            35703                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                26483     15.50%     15.50% # Class of executed instruction
-system.cpu1.op_class::IntAlu                    74610     43.68%     59.18% # Class of executed instruction
-system.cpu1.op_class::IntMult                       0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.18% # Class of executed instruction
-system.cpu1.op_class::MemRead                   57921     33.91%     93.09% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  11808      6.91%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    170822                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           26.474097                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              25884                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           892.551724                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.474097                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051707                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.051707                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           211529                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          211529                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        40844                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          40844                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        11631                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         11631                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        52475                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           52475                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        52475                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          52475                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          167                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          167                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          105                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          272                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           272                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          272                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          272                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      1891500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      1891500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1642500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      1642500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       250000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       250000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      3534000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      3534000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      3534000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      3534000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        41011                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        41011                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        11736                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        11736                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        52747                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        52747                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        52747                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        52747                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004072                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.004072                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008947                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.008947                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005157                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005157                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005157                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005157                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4464.285714                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  4464.285714                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          167                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          272                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          272                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1724500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1724500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1537500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1537500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       194000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       194000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3262000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3262000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004072                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004072                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008947                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008947                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005157                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.005157                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005157                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.005157                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3464.285714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3464.285714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
-system.cpu1.icache.tags.replacements              280                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           66.953040                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             170457                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           465.729508                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    66.953040                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.130768                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.130768                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           171189                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          171189                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       170457                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         170457                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       170457                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          170457                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       170457                       # number of overall hits
-system.cpu1.icache.overall_hits::total         170457                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
-system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5688500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      5688500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      5688500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      5688500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      5688500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      5688500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       170823                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       170823                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       170823                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       170823                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       170823                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       170823                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002143                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002143                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002143                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002143                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002143                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002143                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15542.349727                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15542.349727                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks          280                       # number of writebacks
-system.cpu1.icache.writebacks::total              280                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5322500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5322500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5322500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5322500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5322500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5322500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002143                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002143                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002143                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
-system.cpu2.numCycles                          527130                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     168244                       # Number of instructions committed
-system.cpu2.committedOps                       168244                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               109603                       # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        33329                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      109603                       # number of integer instructions
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             267321                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            101101                       # number of times the integer registers were written
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        52443                       # number of memory refs
-system.cpu2.num_load_insts                      40463                       # Number of load instructions
-system.cpu2.num_store_insts                     11980                       # Number of store instructions
-system.cpu2.num_idle_cycles              74087.861169                       # Number of idle cycles
-system.cpu2.num_busy_cycles              453042.138831                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.859450                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.140550                       # Percentage of idle cycles
-system.cpu2.Branches                            34984                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                25761     15.31%     15.31% # Class of executed instruction
-system.cpu2.op_class::IntAlu                    74059     44.01%     59.32% # Class of executed instruction
-system.cpu2.op_class::IntMult                       0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.32% # Class of executed instruction
-system.cpu2.op_class::MemRead                   56476     33.56%     92.88% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  11980      7.12%    100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    168276                       # Class of executed instruction
-system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           27.444081                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              26343                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs           878.100000                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.444081                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.053602                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.053602                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           209996                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          209996                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        40285                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          40285                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        11801                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         11801                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           15                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        52086                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           52086                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        52086                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          52086                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          170                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          104                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          104                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          274                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           274                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          274                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          274                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2220000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      2220000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1703000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      1703000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       260000                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       260000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      3923000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      3923000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      3923000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      3923000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        40455                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        40455                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        11905                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        11905                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           73                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        52360                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        52360                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        52360                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        52360                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.004202                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.004202                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.008736                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.008736                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.794521                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.794521                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005233                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.005233                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005233                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.005233                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        16375                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total        16375                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4482.758621                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  4482.758621                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          170                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          274                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          274                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          274                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2050000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2050000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1599000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1599000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       202000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       202000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3649000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3649000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3649000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3649000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004202                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004202                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.008736                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.008736                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.794521                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.794521                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005233                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.005233                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005233                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.005233                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        15375                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        15375                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3482.758621                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3482.758621                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
-system.cpu2.icache.tags.replacements              280                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           69.363893                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             167911                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           458.773224                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    69.363893                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.135476                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.135476                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           168643                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          168643                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       167911                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         167911                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       167911                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          167911                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       167911                       # number of overall hits
-system.cpu2.icache.overall_hits::total         167911                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
-system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8088500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      8088500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      8088500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      8088500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      8088500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      8088500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       168277                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       168277                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       168277                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       168277                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       168277                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       168277                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002175                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002175                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002175                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002175                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002175                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002175                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 22099.726776                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 22099.726776                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          280                       # number of writebacks
-system.cpu2.icache.writebacks::total              280                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7722500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      7722500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      7722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7722500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      7722500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002175                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002175                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002175                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
-system.cpu3.numCycles                          527131                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     165809                       # Number of instructions committed
-system.cpu3.committedOps                       165809                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               112442                       # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        30690                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      112442                       # number of integer instructions
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             289238                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            110642                       # number of times the integer registers were written
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        57921                       # number of memory refs
-system.cpu3.num_load_insts                      41890                       # Number of load instructions
-system.cpu3.num_store_insts                     16031                       # Number of store instructions
-system.cpu3.num_idle_cycles              74358.001718                       # Number of idle cycles
-system.cpu3.num_busy_cycles              452772.998282                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.858938                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.141062                       # Percentage of idle cycles
-system.cpu3.Branches                            32344                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                23127     13.95%     13.95% # Class of executed instruction
-system.cpu3.op_class::IntAlu                    75479     45.51%     59.46% # Class of executed instruction
-system.cpu3.op_class::IntMult                       0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.46% # Class of executed instruction
-system.cpu3.op_class::MemRead                   51204     30.88%     90.33% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  16031      9.67%    100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    165841                       # Class of executed instruction
-system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           25.704074                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              34341                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1184.172414                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.704074                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050203                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.050203                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           231895                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          231895                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        41733                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          41733                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        15853                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         15853                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        57586                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           57586                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        57586                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          57586                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          150                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          150                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          109                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          259                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           259                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          259                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          259                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      1542500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      1542500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1810500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      1810500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       250500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       250500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      3353000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      3353000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      3353000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      3353000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41883                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41883                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        15962                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        15962                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           67                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        57845                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        57845                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        57845                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        57845                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003581                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003581                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006829                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.006829                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.835821                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.835821                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004477                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.004477                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004477                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.004477                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4473.214286                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  4473.214286                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          150                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          150                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          109                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          259                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          259                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1392500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1392500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1701500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1701500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       194500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       194500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3094000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3094000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3094000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3094000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003581                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003581                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.006829                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.006829                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.835821                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.835821                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004477                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.004477                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004477                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.004477                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9283.333333                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9283.333333                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3473.214286                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3473.214286                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
-system.cpu3.icache.tags.replacements              281                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           64.942208                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             165475                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           450.885559                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    64.942208                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.126840                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.126840                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           166209                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          166209                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       165475                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         165475                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       165475                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          165475                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       165475                       # number of overall hits
-system.cpu3.icache.overall_hits::total         165475                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
-system.cpu3.icache.overall_misses::total          367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5473500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      5473500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      5473500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      5473500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      5473500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      5473500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       165842                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       165842                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       165842                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       165842                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       165842                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       165842                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002213                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002213                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002213                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002213                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002213                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002213                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14914.168937                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14914.168937                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          281                       # number of writebacks
-system.cpu3.icache.writebacks::total              281                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5106500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5106500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5106500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5106500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5106500                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5106500                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002213                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002213                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002213                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  347.185045                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1714                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.995338                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.881447                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      230.714883                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       54.006864                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst        6.227742                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        0.835119                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       46.668024                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        6.066881                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        0.961095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.822991                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.003520                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000824                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000095                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000712                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000093                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005298                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    19669                       # Number of tag accesses
-system.l2c.tags.data_accesses                   19669                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          495                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             495                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst           182                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst           352                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           301                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           357                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total              1192                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data            3                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 352                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1218                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                352                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                301                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1218                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            14                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            14                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             15                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          285                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           14                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst           65                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst           10                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total             374                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total             78                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                14                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                65                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                23                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   594                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               14                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               16                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               65                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               23                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst               10                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
-system.l2c.overall_misses::total                  594                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      5892000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       837500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       905000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       836000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      8470500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     16965000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst       831500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3806500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst       555500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     22158500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data      3927500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data       118000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data       475500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data       119000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total      4640000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     16965000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data      9819500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst       831500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data       955500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      3806500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1380500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       555500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       955000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        35269000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     16965000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data      9819500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst       831500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data       955500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      3806500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1380500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       555500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       955000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       35269000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks          495                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total          495                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           14                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           14                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           15                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          366                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          366                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst          367                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          1566                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data           11                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data           11                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data           11                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total          104                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.974359                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.610278                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.038251                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.177596                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.027248                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.238825                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181818                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.727273                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.181818                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.750000                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.038251                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.177596                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.884615                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.027248                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.327815                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.038251                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.177596                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.884615                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.027248                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.327815                       # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59821.428571                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60333.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59714.285714                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 59651.408451                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59526.315789                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59392.857143                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58561.538462                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        55550                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 59247.326203                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        59000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59437.500000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        59500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 59526.315789                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 59392.857143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 59718.750000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 58561.538462                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 60021.739130                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst        55550                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 59687.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 59375.420875                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 59526.315789                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 59392.857143                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 59718.750000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 58561.538462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 60021.739130                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst        55550                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 59375.420875                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           11                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
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-system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 22                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst            11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total                22                       # number of overall MSHR hits
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           14                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           14                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          285                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           10                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           54                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            5                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total          354                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data           66                       # number of ReadSharedReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::cpu2.data            7                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total           76                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu2.inst           54                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           22                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            5                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu2.data           22                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       271000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       269000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       381000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      1454000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4902000                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       696000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      7050500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     14115000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       500500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      2674000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       247500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     17537000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      3267500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data        49500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       346500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        99000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total      3762500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     14115000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data      8169500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst       500500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       747000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      2674000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1101500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       247500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       795000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     28350000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     14115000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data      8169500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst       500500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       747000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      2674000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1101500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       247500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       795000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     28350000                       # number of overall MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.974359                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.226054                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.636364                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.730769                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19357.142857                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19214.285714                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        19050                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19131.578947                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49821.428571                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50333.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49714.285714                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 49651.408451                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst        50050                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        49500                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        49500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        49500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        49500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        50050                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        49800                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        49500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 49562.937063                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        50050                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        49800                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        49500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 49562.937063                       # average overall mshr miss latency
-system.membus.trans_dist::ReadResp                430                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              271                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              261                       # Total snoops (count)
-system.membus.snoop_fanout::samples               915                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     915    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 915                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              685132                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2860000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         3976                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1120                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1854                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              2221                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean         1056                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             273                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            273                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              424                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             424                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          1566                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          655                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          579                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1015                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          360                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5866                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        43648                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        41472                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 183616                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1028                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             2918                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.265250                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.153418                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1002     34.34%     34.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    794     27.21%     61.55% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    468     16.04%     77.59% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    654     22.41%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               2918                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            3048992                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              1.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy            700999                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            500989                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            550995                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            435970                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            554485                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            441968                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            552992                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            411482                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 7c2d41959..b7f3d9217 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.010022                       # Nu
 sim_ticks                                    10021833                       # Number of ticks simulated
 final_tick                                   10021833                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 141404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425972                       # Number of bytes of host memory used
-host_seconds                                    70.87                       # Real time elapsed on the host
+host_tick_rate                                 162199                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 417868                       # Number of bytes of host memory used
+host_seconds                                    61.79                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39622272                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index 10214a209..b8eac504c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.007437                       # Nu
 sim_ticks                                     7436579                       # Number of ticks simulated
 final_tick                                    7436579                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  32317                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 403848                       # Number of bytes of host memory used
-host_seconds                                   230.12                       # Real time elapsed on the host
+host_tick_rate                                  74529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 420508                       # Number of bytes of host memory used
+host_seconds                                    99.78                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39411840                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 8f87abafb..d149e53a7 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.006099                       # Nu
 sim_ticks                                     6099346                       # Number of ticks simulated
 final_tick                                    6099346                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  34740                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 404344                       # Number of bytes of host memory used
-host_seconds                                   175.57                       # Real time elapsed on the host
+host_tick_rate                                  81040                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 421980                       # Number of bytes of host memory used
+host_seconds                                    75.26                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39765376                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 02b6c9c1b..2391b011d 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.004723                       # Nu
 sim_ticks                                     4722948                       # Number of ticks simulated
 final_tick                                    4722948                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  43612                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 429416                       # Number of bytes of host memory used
-host_seconds                                   108.30                       # Real time elapsed on the host
+host_tick_rate                                  53510                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 421672                       # Number of bytes of host memory used
+host_seconds                                    88.26                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     38973248                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index ac17b1f35..87ea51c89 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.007679                       # Nu
 sim_ticks                                     7678882                       # Number of ticks simulated
 final_tick                                    7678882                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 131227                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425824                       # Number of bytes of host memory used
-host_seconds                                    58.52                       # Real time elapsed on the host
+host_tick_rate                                 120821                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 418672                       # Number of bytes of host memory used
+host_seconds                                    63.56                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39687936                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 30ddbd92e..f24c7c909 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000502                       # Nu
 sim_ticks                                   501584000                       # Number of ticks simulated
 final_tick                                  501584000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              112049096                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235328                       # Number of bytes of host memory used
-host_seconds                                     4.48                       # Real time elapsed on the host
+host_tick_rate                               82658959                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231728                       # Number of bytes of host memory used
+host_seconds                                     6.07                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0                 77173                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index 35b91ee55..b05d177c6 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000500                       # Nu
 sim_ticks                                   500337000                       # Number of ticks simulated
 final_tick                                  500337000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                               94931123                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234040                       # Number of bytes of host memory used
-host_seconds                                     5.27                       # Real time elapsed on the host
+host_tick_rate                               90464630                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231728                       # Number of bytes of host memory used
+host_seconds                                     5.53                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0                 75919                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 381569cba..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,152 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.044221                       # Number of seconds simulated
-sim_ticks                                 44221003000                       # Number of ticks simulated
-final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1271644                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1271643                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              636550745                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229384                       # Number of bytes of host memory used
-host_seconds                                    69.47                       # Real time elapsed on the host
-sim_insts                                    88340673                       # Number of instructions simulated
-sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         353752292                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         126702647                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            480454939                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    353752292                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       353752292                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       91652896                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          91652896                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst           88438073                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           20276638                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             108714711                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          14613377                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             14613377                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999644241                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2865214229                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10864858470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999644241                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999644241                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          2072610067                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2072610067                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999644241                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4937824296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            12937468537                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20276638                       # DTB read hits
-system.cpu.dtb.read_misses                      90148                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
-system.cpu.dtb.write_hits                    14613377                       # DTB write hits
-system.cpu.dtb.write_misses                      7252                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
-system.cpu.dtb.data_hits                     34890015                       # DTB hits
-system.cpu.dtb.data_misses                      97400                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
-system.cpu.itb.fetch_hits                    88438073                       # ITB hits
-system.cpu.itb.fetch_misses                      3934                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                88442007                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    88340673                       # Number of instructions committed
-system.cpu.committedOps                      88340673                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
-system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     78039444                       # number of integer instructions
-system.cpu.num_fp_insts                        267757                       # number of float instructions
-system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      34987415                       # number of memory refs
-system.cpu.num_load_insts                    20366786                       # Number of load instructions
-system.cpu.num_store_insts                   14620629                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                   88442007                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          13754477                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                  44394799     50.20%     60.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  114304      0.13%     60.27% # Class of executed instruction
-system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
-system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
-system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv                   37764      0.04%     60.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 20366786     23.03%     83.47% # Class of executed instruction
-system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   88438073                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           108714711                       # Transaction distribution
-system.membus.trans_dist::ReadResp          108714711                       # Transaction distribution
-system.membus.trans_dist::WriteReq           14613377                       # Transaction distribution
-system.membus.trans_dist::WriteResp          14613377                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    176876146                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     69780030                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              246656176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    353752292                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    218355543                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               572107835                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         123328088                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.717096                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.450410                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                34890015     28.29%     28.29% # Request fanout histogram
-system.membus.snoop_fanout::1                88438073     71.71%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           123328088                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index e76d0cce6..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,546 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.134742                       # Number of seconds simulated
-sim_ticks                                134741611500                       # Number of ticks simulated
-final_tick                               134741611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1303886                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1303885                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1988750581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260188                       # Number of bytes of host memory used
-host_seconds                                    67.75                       # Real time elapsed on the host
-sim_insts                                    88340673                       # Number of instructions simulated
-sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            367360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10138112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10505472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       367360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          367360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7320448                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7320448                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5740                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158408                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                164148                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114382                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114382                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2726403                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75241137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                77967540                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2726403                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2726403                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54329527                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54329527                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54329527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2726403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75241137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              132297067                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20276638                       # DTB read hits
-system.cpu.dtb.read_misses                      90148                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
-system.cpu.dtb.write_hits                    14613377                       # DTB write hits
-system.cpu.dtb.write_misses                      7252                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
-system.cpu.dtb.data_hits                     34890015                       # DTB hits
-system.cpu.dtb.data_misses                      97400                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
-system.cpu.itb.fetch_hits                    88438074                       # ITB hits
-system.cpu.itb.fetch_misses                      3934                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                88442008                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        269483223                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    88340673                       # Number of instructions committed
-system.cpu.committedOps                      88340673                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
-system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     78039444                       # number of integer instructions
-system.cpu.num_fp_insts                        267757                       # number of float instructions
-system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      34987415                       # number of memory refs
-system.cpu.num_load_insts                    20366786                       # Number of load instructions
-system.cpu.num_store_insts                   14620629                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  269483223                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          13754477                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                  44394799     50.20%     60.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  114304      0.13%     60.27% # Class of executed instruction
-system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
-system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
-system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv                   37764      0.04%     60.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 20366786     23.03%     83.47% # Class of executed instruction
-system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   88438073                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            200248                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4078.397630                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34685671                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204344                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            169.741568                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         983457500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4078.397630                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995703                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995703                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3595                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          69984374                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         69984374                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14469799                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34685671                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34685671                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34685671                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34685671                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        60766                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         60766                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       143578                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       143578                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       204344                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         204344                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       204344                       # number of overall misses
-system.cpu.dcache.overall_misses::total        204344                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2138978000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2138978000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8279807000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8279807000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  10418785000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  10418785000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  10418785000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  10418785000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002997                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002997                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009825                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009825                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.005857                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.005857                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.005857                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.005857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 50986.498258                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 50986.498258                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       168278                       # number of writebacks
-system.cpu.dcache.writebacks::total            168278                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        60766                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143578                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143578                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       204344                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204344                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       204344                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204344                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2078212000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2078212000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8136229000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8136229000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10214441000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10214441000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10214441000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10214441000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009825                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements             74391                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1870.507754                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             76436                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1156.021220                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1870.507754                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.913334                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.913334                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2045                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          109                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          191                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1708                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998535                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         176952584                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        176952584                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88361638                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88361638                       # number of overall hits
-system.cpu.icache.overall_hits::total        88361638                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        76436                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         76436                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        76436                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          76436                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        76436                       # number of overall misses
-system.cpu.icache.overall_misses::total         76436                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1275518500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1275518500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1275518500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1275518500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1275518500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1275518500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     88438074                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     88438074                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     88438074                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     88438074                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     88438074                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     88438074                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000864                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000864                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000864                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000864                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000864                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000864                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16687.405149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16687.405149                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        74391                       # number of writebacks
-system.cpu.icache.writebacks::total             74391                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        76436                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        76436                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        76436                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        76436                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        76436                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1199082500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1199082500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1199082500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1199082500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1199082500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1199082500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000864                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000864                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000864                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements           131998                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30708.485304                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             247404                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164074                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.507881                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1667.759999                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1642.825119                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.836118                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.050896                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.050135                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.937149                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32076                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          731                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9441                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        21639                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4751004                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4751004                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168278                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168278                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        74391                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        74391                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12696                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12696                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        70696                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        70696                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33240                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        33240                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        70696                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        45936                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          116632                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        70696                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        45936                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         116632                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130882                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130882                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         5740                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         5740                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27526                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27526                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         5740                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158408                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        164148                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         5740                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158408                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       164148                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7787542500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7787542500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    341866000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    341866000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1637990000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1637990000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    341866000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   9425532500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   9767398500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    341866000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   9425532500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   9767398500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168278                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168278                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        74391                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        74391                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        76436                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        76436                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        60766                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        60766                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        76436                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       204344                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       280780                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        76436                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       204344                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       280780                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911574                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911574                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.075096                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.075096                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.452984                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.452984                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.075096                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.775203                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.584614                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.075096                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.775203                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.584614                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       114382                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114382                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          105                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          105                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130882                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130882                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         5740                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         5740                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27526                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27526                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         5740                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       164148                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         5740                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       164148                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6478722500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6478722500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    284466000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    284466000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1362730000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1362730000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    284466000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7841452500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8125918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    284466000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7841452500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8125918500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911574                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911574                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.075096                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.075096                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.452984                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452984                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.075096                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775203                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.584614                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.075096                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775203                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.584614                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       555419                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       274639                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3875                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3875                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        137202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       282660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        74391                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        49586                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        76436                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        60766                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       227263                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       608936                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            836199                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9652928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23847808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           33500736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      131998                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       412778                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009388                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.096434                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             408903     99.06%     99.06% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3875      0.94%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         412778                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      520378500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     114654000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     306516000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              33266                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       114382                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            13845                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130882                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130882                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33266                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       456523                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 456523                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17825920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17825920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            292375                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  292375    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              292375                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           750324500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          820740000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index bcdad61b2..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,243 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.048960                       # Number of seconds simulated
-sim_ticks                                 48960022500                       # Number of ticks simulated
-final_tick                                48960022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 991674                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1268214                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              684673258                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242788                       # Number of bytes of host memory used
-host_seconds                                    71.51                       # Real time elapsed on the host
-sim_insts                                    70913204                       # Number of instructions simulated
-sim_ops                                      90688159                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         312580364                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         106573345                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            419153709                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    312580364                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       312580364                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       78660211                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78660211                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst           78145091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           22919730                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             101064821                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          19865820                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             19865820                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6384399925                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2176742157                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8561142083                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6384399925                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6384399925                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1606621218                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1606621218                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6384399925                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3783363376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10167763301                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         97920046                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    70913204                       # Number of instructions committed
-system.cpu.committedOps                      90688159                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              81528528                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
-system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      9253630                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     81528528                       # number of integer instructions
-system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           141479386                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           53916335                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            266608097                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            36877111                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      43422001                       # number of memory refs
-system.cpu.num_load_insts                    22866262                       # Number of load instructions
-system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               97920045.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          13741468                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  47187979     52.03%     52.03% # Class of executed instruction
-system.cpu.op_class::IntMult                    80119      0.09%     52.12% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::MemRead                 22866262     25.21%     77.33% # Class of executed instruction
-system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   90690106                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           100925158                       # Transaction distribution
-system.membus.trans_dist::ReadResp          100941077                       # Transaction distribution
-system.membus.trans_dist::WriteReq           19849901                       # Transaction distribution
-system.membus.trans_dist::WriteResp          19849901                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq            123744                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp           123744                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq         15919                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq          15919                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp         15919                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    156290182                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     85571100                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              241861282                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    312580364                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    185233556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               497813920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         120930641                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.646198                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.478149                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                42785550     35.38%     35.38% # Request fanout histogram
-system.membus.snoop_fanout::1                78145091     64.62%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           120930641                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 2518d4d22..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,662 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.128077                       # Number of seconds simulated
-sim_ticks                                128076834500                       # Number of ticks simulated
-final_tick                               128076834500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 775777                       # Simulator instruction rate (inst/s)
-host_op_rate                                   990450                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1411878896                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277764                       # Number of bytes of host memory used
-host_seconds                                    90.71                       # Real time elapsed on the host
-sim_insts                                    70373651                       # Number of instructions simulated
-sim_ops                                      89847385                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            233152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7925248                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8158400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       233152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          233152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5513600                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5513600                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3643                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             123832                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                127475                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           86150                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                86150                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1820407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             61878856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                63699263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1820407                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1820407                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          43049159                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               43049159                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          43049159                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1820407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            61878856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              106748422                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        256153669                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    70373651                       # Number of instructions committed
-system.cpu.committedOps                      89847385                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              81528528                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
-system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      9253630                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     81528528                       # number of integer instructions
-system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           141328550                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           53916335                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            334802072                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            36877111                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      43422001                       # number of memory refs
-system.cpu.num_load_insts                    22866262                       # Number of load instructions
-system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               256153668.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          13741468                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  47187979     52.03%     52.03% # Class of executed instruction
-system.cpu.op_class::IntMult                    80119      0.09%     52.12% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.12% # Class of executed instruction
-system.cpu.op_class::MemRead                 22866262     25.21%     77.33% # Class of executed instruction
-system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   90690106                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            155902                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4075.927155                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42601677                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            266.263810                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1109655500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4075.927155                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995099                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995099                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          787                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3263                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22743361                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22743361                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83609                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83609                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42486230                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42486230                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42569839                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42569839                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        36706                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         36706                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        40135                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        40135                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       143738                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         143738                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       183873                       # number of overall misses
-system.cpu.dcache.overall_misses::total        183873                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    577584000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    577584000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   6405138000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   6405138000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   6982722000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   6982722000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   6982722000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   6982722000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       123744                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       123744                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42629968                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42629968                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42753712                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42753712                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001611                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.001611                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324339                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.324339                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.003372                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.003372                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.004301                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.004301                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 48579.512725                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37975.787636                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       128175                       # number of writebacks
-system.cpu.dcache.writebacks::total            128175                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7598                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         7598                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7598                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7598                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7598                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7598                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23858                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23858                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136140                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    495022500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    495022500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   6298106000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   6298106000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1201109000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1201109000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6793128500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6793128500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7994237500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7994237500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.192801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.192801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements             16890                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1732.356634                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78126184                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             18908                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           4131.911572                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1732.356634                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.845877                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.845877                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          294                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1645                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         156309092                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        156309092                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78126184                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78126184                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78126184                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78126184                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78126184                       # number of overall hits
-system.cpu.icache.overall_hits::total        78126184                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        18908                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         18908                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        18908                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
-system.cpu.icache.overall_misses::total         18908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    426200500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    426200500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    426200500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    426200500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    426200500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    426200500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78145092                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78145092                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78145092                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78145092                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78145092                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78145092                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000242                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000242                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000242                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22540.749947                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22540.749947                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        16890                       # number of writebacks
-system.cpu.icache.writebacks::total             16890                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        18908                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        18908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    407292500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    407292500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    407292500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    407292500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    407292500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    407292500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements            95333                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30336.891531                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             114380                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126455                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.904511                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1088.258663                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1490.027343                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.847125                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.033211                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.045472                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.925808                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1225                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        13921                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15196                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          624                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949768                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3017503                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3017503                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       128175                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       128175                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        15790                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        15790                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4751                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4751                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        15265                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        15265                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31415                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        31415                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        15265                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        36166                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           51431                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        15265                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        36166                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          51431                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102281                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102281                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3643                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3643                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21551                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        21551                       # number of ReadSharedReq misses
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-system.cpu.l2cache.demand_misses::cpu.data       123832                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        127475                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3643                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       123832                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       127475                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6087670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6087670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    217265500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    217265500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1284434000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1284434000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    217265500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7372104500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7589370000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    217265500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7372104500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7589370000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       128175                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       128175                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        15790                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        15790                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107032                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107032                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        18908                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        18908                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        52966                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        52966                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data       159998                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       178906                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        18908                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       159998                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955611                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955611                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.192670                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.192670                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.406884                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.406884                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192670                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.773960                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.712525                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192670                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.773960                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.712525                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
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-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        86150                       # number of writebacks
-system.cpu.l2cache.writebacks::total            86150                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          104                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          104                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102281                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102281                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3643                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3643                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21551                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21551                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3643                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       123832                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       127475                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3643                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       123832                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       127475                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5064860500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5064860500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    180835500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    180835500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1068924000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1068924000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    180835500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6133784500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   6314620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    180835500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6133784500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   6314620000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955611                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955611                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.192670                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.192670                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.406884                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.406884                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.192670                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773960                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.712525                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.192670                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773960                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.712525                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       351698                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       172817                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3696                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3119                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3089                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           30                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       214325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        16890                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        36910                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107032                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107032                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        18908                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        52966                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54706                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       475898                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            530604                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2291072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18443072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           20734144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       95333                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       274239                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025051                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.156979                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             267399     97.51%     97.51% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               6810      2.48%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                 30      0.01%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         274239                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      320914000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      28362000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     239997000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              25194                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        86150                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6168                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102281                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102281                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         25194                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       347268                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 347268                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13672000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13672000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            219817                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  219817    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              219817                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           568080092                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          637375000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 3ed030f96..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,124 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.068149                       # Number of seconds simulated
-sim_ticks                                 68148677000                       # Number of ticks simulated
-final_tick                                68148677000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1843276                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1867142                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              934655607                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225200                       # Number of bytes of host memory used
-host_seconds                                    72.91                       # Real time elapsed on the host
-sim_insts                                   134398959                       # Number of instructions simulated
-sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         538214320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            685773680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    538214320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       538214320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       89882950                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          89882950                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          134553580                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           37231300                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             171784880                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          20864304                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             20864304                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data              15916                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                 15916                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7897648842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2165256414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10062905256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7897648842                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7897648842                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1318924357                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1318924357                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7897648842                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3484180771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11381829614                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        136297355                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398959                       # Number of instructions committed
-system.cpu.committedOps                     136139187                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187757                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                2326976                       # Number of float alu accesses
-system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898968                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187757                       # number of integer instructions
-system.cpu.num_fp_insts                       2326976                       # number of float instructions
-system.cpu.num_int_register_reads           263032419                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147731                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              4725606                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160261                       # number of memory refs
-system.cpu.num_load_insts                    37275864                       # Number of load instructions
-system.cpu.num_store_insts                   20884397                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               136297354.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          12719094                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  66342067     48.68%     57.07% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::MemRead                 37296718     27.36%     84.68% # Class of executed instruction
-system.cpu.op_class::MemWrite                20884397     15.32%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  136293808                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           171784880                       # Transaction distribution
-system.membus.trans_dist::ReadResp          171784880                       # Transaction distribution
-system.membus.trans_dist::WriteReq           20864304                       # Transaction distribution
-system.membus.trans_dist::WriteResp          20864304                       # Transaction distribution
-system.membus.trans_dist::SwapReq               15916                       # Transaction distribution
-system.membus.trans_dist::SwapResp              15916                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    269107160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    116223040                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              385330200                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    538214320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    237569638                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               775783958                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         192665100                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.698381                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.458961                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                58111520     30.16%     30.16% # Request fanout histogram
-system.membus.snoop_fanout::1               134553580     69.84%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           192665100                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 97bc2f274..e69de29bb 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,535 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.203116                       # Number of seconds simulated
-sim_ticks                                203115946500                       # Number of ticks simulated
-final_tick                               203115946500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1277402                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1293942                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1930526358                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259920                       # Number of bytes of host memory used
-host_seconds                                   105.21                       # Real time elapsed on the host
-sim_insts                                   134398959                       # Number of instructions simulated
-sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            525056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7828352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8353408                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       525056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          525056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5457280                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5457280                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8204                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             122318                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                130522                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           85270                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                85270                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2585006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             38541297                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                41126303                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2585006                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2585006                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          26867807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               26867807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          26867807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2585006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38541297                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               67994110                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        406231893                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398959                       # Number of instructions committed
-system.cpu.committedOps                     136139187                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187757                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                2326976                       # Number of float alu accesses
-system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898968                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187757                       # number of integer instructions
-system.cpu.num_fp_insts                       2326976                       # number of float instructions
-system.cpu.num_int_register_reads           263032419                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147730                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              4725606                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160261                       # number of memory refs
-system.cpu.num_load_insts                    37275864                       # Number of load instructions
-system.cpu.num_store_insts                   20884397                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               406231892.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          12719094                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  66342067     48.68%     57.07% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
-system.cpu.op_class::MemRead                 37296718     27.36%     84.68% # Class of executed instruction
-system.cpu.op_class::MemWrite                20884397     15.32%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  136293808                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            146583                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.268923                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            57960841                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            150679                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            384.664359                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         822359500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.268923                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997868                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997868                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          474                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3586                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         116373719                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        116373719                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     37185800                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37185800                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20759140                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data        15901                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total           15901                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data      57944940                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         57944940                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     57944940                       # number of overall hits
-system.cpu.dcache.overall_hits::total        57944940                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        45500                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         45500                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       105164                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       105164                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data           15                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total            15                       # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data       150664                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         150664                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       150664                       # number of overall misses
-system.cpu.dcache.overall_misses::total        150664                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1623315500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1623315500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   6329554000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   6329554000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data       441000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total       441000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7952869500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7952869500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7952869500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7952869500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data        15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total        15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     58095604                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     58095604                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     58095604                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     58095604                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001222                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.001222                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005040                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005040                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000942                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total     0.000942                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002593                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        29400                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        29400                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52785.466336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52785.466336                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       123865                       # number of writebacks
-system.cpu.dcache.writebacks::total            123865                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45500                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        45500                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       105164                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       105164                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data           15                       # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total           15                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       150664                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       150664                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       150664                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       150664                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1577815500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1577815500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   6224390000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   6224390000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       426000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total       426000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7802205500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   7802205500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7802205500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7802205500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005040                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000942                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.000942                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        28400                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        28400                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements            184976                       # number of replacements
-system.cpu.icache.tags.tagsinuse          2004.181265                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           134366557                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            187024                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            718.445531                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      144582800500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  2004.181265                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.978604                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.978604                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          456                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1427                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         269294186                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        269294186                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    134366557                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       134366557                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     134366557                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        134366557                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    134366557                       # number of overall hits
-system.cpu.icache.overall_hits::total       134366557                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       187024                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        187024                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       187024                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
-system.cpu.icache.overall_misses::total        187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2835239000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2835239000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2835239000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2835239000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2835239000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2835239000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    134553581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    134553581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    134553581                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    134553581                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    134553581                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    134553581                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001390                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001390                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001390                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15159.760245                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15159.760245                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       184976                       # number of writebacks
-system.cpu.icache.writebacks::total            184976                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       187024                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       187024                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       187024                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2648215000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2648215000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2648215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2648215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2648215000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2648215000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements            99022                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30843.699683                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             433832                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           130065                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.335501                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3249.863620                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1304.666895                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.802282                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.099178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.039815                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.941275                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31043                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          566                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11257                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18470                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          557                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.947357                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5588812                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5588812                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       123865                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       123865                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       184923                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       184923                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         3915                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         3915                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       178820                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       178820                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        24446                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        24446                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       178820                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        28361                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          207181                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       178820                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        28361                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         207181                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       101264                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       101264                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8204                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         8204                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21054                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        21054                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         8204                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       122318                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        130522                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         8204                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       122318                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       130522                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6025890000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6025890000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    488461500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    488461500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1252834000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1252834000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    488461500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7278724000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7767185500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    488461500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7278724000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7767185500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       123865                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       123865                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       184923                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       184923                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       105179                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       105179                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       187024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       187024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        45500                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        45500                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       187024                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       150679                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       337703                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       187024                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       150679                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       337703                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.962778                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.962778                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.043866                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.043866                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.462725                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.462725                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.043866                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.811779                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.386499                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.043866                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.811779                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.386499                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        85270                       # number of writebacks
-system.cpu.l2cache.writebacks::total            85270                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           96                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total           96                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101264                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       101264                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8204                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8204                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21054                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21054                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         8204                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       122318                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       130522                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         8204                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       122318                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       130522                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5013250000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5013250000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    406421500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    406421500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1042294000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1042294000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    406421500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6055544000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   6461965500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    406421500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6055544000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   6461965500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.962778                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.962778                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043866                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043866                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.462725                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.462725                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043866                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.811779                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.386499                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043866                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.811779                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.386499                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       669262                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       331559                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests           66                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3547                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3547                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        232524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       209135                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       184976                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        36470                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       105179                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       105179                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       187024                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        45500                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       559024                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       447941                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1006965                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     23808000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     17570816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           41378816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       99022                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       436725                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.008273                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.090579                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             433112     99.17%     99.17% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3613      0.83%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         436725                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      643472000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     280536000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     226018500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              29258                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        85270                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            10301                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            101264                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           101264                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         29258                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       356615                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 356615                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13810688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13810688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            226093                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  226093    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              226093                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           568574500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          652610000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
index 18987ac29..6e51bc804 100644
--- a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
+++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.010000                       # Nu
 sim_ticks                                 10000000000                       # Number of ticks simulated
 final_tick                                10000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              995173175                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1449604                       # Number of bytes of host memory used
-host_seconds                                    10.05                       # Real time elapsed on the host
+host_tick_rate                              621801419                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1442452                       # Number of bytes of host memory used
+host_seconds                                    16.08                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::l0subsys0.tester0      2151552                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
index 2da8cfc3e..bdf77ebe4 100644
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000014                       # Nu
 sim_ticks                                       14181                       # Number of ticks simulated
 final_tick                                      14181                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 116506                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 464616                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                                 154609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 480252                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::dir_cntrl0         16576                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index 5cadbdde3..16afa43a3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000043                       # Nu
 sim_ticks                                       43191                       # Number of ticks simulated
 final_tick                                      43191                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 428274                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 410016                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                 667875                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406088                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        57728                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 1db6620aa..75f44776f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000054                       # Nu
 sim_ticks                                       54211                       # Number of ticks simulated
 final_tick                                      54211                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 316777                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 410608                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_tick_rate                                 538772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406688                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        54016                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 851456fb6..f8400a6e4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                       50141                       # Number of ticks simulated
 final_tick                                      50141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 395128                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389312                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                                 969830                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406616                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        50624                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 5a3d40466..c2eacbfda 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                       29561                       # Number of ticks simulated
 final_tick                                      29561                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 334780                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 410240                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                 593739                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406316                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        56000                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index d1da3d54a..3208bfd4e 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000038                       # Nu
 sim_ticks                                       37741                       # Number of ticks simulated
 final_tick                                      37741                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 544029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 408776                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                 877206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404076                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        60992                       # Number of bytes read from this memory
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index 14d004205..238ebf7d9 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                             4618007467                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 202228                       # Number of bytes of host memory used
-host_seconds                                    21.65                       # Real time elapsed on the host
+host_tick_rate                             9064709748                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219696                       # Number of bytes of host memory used
+host_seconds                                    11.03                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu              106649408                       # Number of bytes read from this memory
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
index 710d324a6..cbbc1075a 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            15880275218                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204660                       # Number of bytes of host memory used
-host_seconds                                     6.30                       # Real time elapsed on the host
+host_tick_rate                            16220790107                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221740                       # Number of bytes of host memory used
+host_seconds                                     6.17                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu                     64                       # Number of bytes read from this memory
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 46baca50d..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,152 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.045952                       # Number of seconds simulated
-sim_ticks                                 45951567500                       # Number of ticks simulated
-final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1065115                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1065115                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              532557762                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224960                       # Number of bytes of host memory used
-host_seconds                                    86.28                       # Real time elapsed on the host
-sim_insts                                    91903056                       # Number of instructions simulated
-sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         367612356                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         108337521                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            475949877                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    367612356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       367612356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       30920974                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          30920974                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst           91903089                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           19996198                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             111899287                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data           6501103                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              6501103                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999995996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2357645819                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10357641815                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999995996                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999995996                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           672903574                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              672903574                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999995996                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3030549393                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11030545389                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     19996198                       # DTB read hits
-system.cpu.dtb.read_misses                         10                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
-system.cpu.dtb.write_hits                     6501103                       # DTB write hits
-system.cpu.dtb.write_misses                        23                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
-system.cpu.dtb.data_hits                     26497301                       # DTB hits
-system.cpu.dtb.data_misses                         33                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
-system.cpu.itb.fetch_hits                    91903089                       # ITB hits
-system.cpu.itb.fetch_misses                        47                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                91903136                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    91903056                       # Number of instructions committed
-system.cpu.committedOps                      91903056                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
-system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     79581109                       # number of integer instructions
-system.cpu.num_fp_insts                       6862064                       # number of float instructions
-system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      26497334                       # number of memory refs
-system.cpu.num_load_insts                    19996208                       # Number of load instructions
-system.cpu.num_store_insts                    6501126                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                   91903136                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          10240685                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  51001454     55.49%     63.90% # Class of executed instruction
-system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 2732553      2.97%     67.37% # Class of executed instruction
-system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
-system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv                  754822      0.82%     71.17% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                    318      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::MemRead                 19996208     21.76%     92.93% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6501126      7.07%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91903089                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           111899287                       # Transaction distribution
-system.membus.trans_dist::ReadResp          111899287                       # Transaction distribution
-system.membus.trans_dist::WriteReq            6501103                       # Transaction distribution
-system.membus.trans_dist::WriteResp           6501103                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    183806178                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     52994602                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              236800780                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    367612356                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    139258495                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               506870851                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         118400390                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.776206                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.416786                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                26497301     22.38%     22.38% # Request fanout histogram
-system.membus.snoop_fanout::1                91903089     77.62%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           118400390                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index c2aa1fab9..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,534 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.118763                       # Number of seconds simulated
-sim_ticks                                118762761500                       # Number of ticks simulated
-final_tick                               118762761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1409040                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1409039                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1820846467                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 255756                       # Number of bytes of host memory used
-host_seconds                                    65.22                       # Real time elapsed on the host
-sim_insts                                    91903056                       # Number of instructions simulated
-sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               304960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       167744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          167744                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2621                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  4765                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1412429                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1155379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2567808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1412429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1412429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1412429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1155379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2567808                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     19996198                       # DTB read hits
-system.cpu.dtb.read_misses                         10                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
-system.cpu.dtb.write_hits                     6501103                       # DTB write hits
-system.cpu.dtb.write_misses                        23                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
-system.cpu.dtb.data_hits                     26497301                       # DTB hits
-system.cpu.dtb.data_misses                         33                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
-system.cpu.itb.fetch_hits                    91903090                       # ITB hits
-system.cpu.itb.fetch_misses                        47                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                91903137                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        237525523                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    91903056                       # Number of instructions committed
-system.cpu.committedOps                      91903056                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
-system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     79581109                       # number of integer instructions
-system.cpu.num_fp_insts                       6862064                       # number of float instructions
-system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      26497334                       # number of memory refs
-system.cpu.num_load_insts                    19996208                       # Number of load instructions
-system.cpu.num_store_insts                    6501126                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  237525523                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          10240685                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  51001454     55.49%     63.90% # Class of executed instruction
-system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 2732553      2.97%     67.37% # Class of executed instruction
-system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
-system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv                  754822      0.82%     71.17% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                    318      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.17% # Class of executed instruction
-system.cpu.op_class::MemRead                 19996208     21.76%     92.93% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6501126      7.07%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91903089                       # Class of executed instruction
-system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1441.946319                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26495078                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2223                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11918.613585                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1441.946319                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.352038                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.352038                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          491                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6499355                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26495078                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26495078                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26495078                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26495078                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          475                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           475                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1748                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1748                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2223                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2223                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2223                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2223                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     26856500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     26856500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    107103000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    107103000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    133959500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    133959500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    133959500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    133959500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000269                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000269                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000084                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000084                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56540                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        56540                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60260.683761                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60260.683761                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
-system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1748                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2223                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26381500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     26381500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    105355000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    105355000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    131736500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    131736500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    131736500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    131736500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        55540                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        55540                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements              6681                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1417.953327                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            91894580                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8510                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10798.423032                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1417.953327                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.692360                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.692360                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          585                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          953                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         183814690                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        183814690                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         91894580                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     91894580                       # number of overall hits
-system.cpu.icache.overall_hits::total        91894580                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8510                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8510                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8510                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8510                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8510                       # number of overall misses
-system.cpu.icache.overall_misses::total          8510                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    239145000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    239145000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    239145000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    239145000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    239145000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    239145000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     91903090                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     91903090                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     91903090                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     91903090                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     91903090                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     91903090                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28101.645123                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28101.645123                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         6681                       # number of writebacks
-system.cpu.icache.writebacks::total              6681                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8510                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         8510                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         8510                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         8510                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         8510                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         8510                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    230635000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    230635000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    230635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    230635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    230635000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    230635000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000093                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000093                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2073.923151                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              12687                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3109                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.080733                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.795341                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1704.894227                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   351.233582                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052029                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.010719                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.063291                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3109                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          703                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2096                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.094879                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           145425                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          145425                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks          107                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total          107                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         6681                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         6681                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5889                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         5889                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           53                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           53                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         5889                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            5968                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         5889                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           5968                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1722                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1722                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2621                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2621                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          422                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          422                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2621                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2144                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          4765                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2621                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         4765                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    102460000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    102460000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    155964000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    155964000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     25110500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     25110500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    155964000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    127570500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    283534500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    155964000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    127570500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    283534500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks          107                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total          107                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         6681                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         6681                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8510                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         8510                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          475                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          475                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8510                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        10733                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8510                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        10733                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.985126                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.307991                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.307991                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.888421                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.307991                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.443958                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.307991                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.443958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2621                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2621                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          422                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          422                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2621                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4765                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2621                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4765                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     85240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     85240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    129754000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    129754000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     20890500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     20890500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    129754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    106130500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    235884500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    129754000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    106130500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    235884500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985126                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.307991                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.888421                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.443958                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.443958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        17571                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         6838                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          8985                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         6681                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1748                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1748                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         8510                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          475                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23701                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             28304                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       972224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1121344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        10733                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              10733    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          10733                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       15573500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      12765000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3334500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3043                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1722                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3043                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         9530                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   9530                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       304960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  304960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              4765                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    4765    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                4765                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4782000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           23825000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 177b96346..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,243 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.099596                       # Number of seconds simulated
-sim_ticks                                 99596491500                       # Number of ticks simulated
-final_tick                                99596491500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 695621                       # Simulator instruction rate (inst/s)
-host_op_rate                                   733297                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              402056906                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242228                       # Number of bytes of host memory used
-host_seconds                                   247.72                       # Real time elapsed on the host
-sim_insts                                   172317410                       # Number of instructions simulated
-sim_ops                                     181650342                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         759440208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         110533661                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            869973869                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    759440208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       759440208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       45252940                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          45252940                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          189860052                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           27777721                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             217637773                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          12386694                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             12386694                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7625170290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1109814807                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8734985097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7625170290                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7625170290                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           454362792                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              454362792                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7625170290                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          1564177600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9189347890                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        199192984                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   172317410                       # Number of instructions committed
-system.cpu.committedOps                     181650342                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             143085668                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
-system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    143085668                       # number of integer instructions
-system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           241970171                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            543309970                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           190815535                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      40540779                       # number of memory refs
-system.cpu.num_load_insts                    27896144                       # Number of load instructions
-system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               199192983.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          40300312                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 138988213     76.51%     76.51% # Class of executed instruction
-system.cpu.op_class::IntMult                   908940      0.50%     77.01% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68% # Class of executed instruction
-system.cpu.op_class::MemRead                 27896144     15.36%     93.04% # Class of executed instruction
-system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  181650743                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           217614903                       # Transaction distribution
-system.membus.trans_dist::ReadResp          217637310                       # Transaction distribution
-system.membus.trans_dist::WriteReq           12364287                       # Transaction distribution
-system.membus.trans_dist::WriteResp          12364287                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq               463                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp              463                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq         22407                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq          22407                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp         22407                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    379720104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     80328830                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              460048934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    759440208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    155786601                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               915226809                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         230024467                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.825391                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.379633                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                40164415     17.46%     17.46% # Request fanout histogram
-system.membus.snoop_fanout::1               189860052     82.54%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           230024467                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index d21481ee3..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,644 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.230198                       # Number of seconds simulated
-sim_ticks                                230197694500                       # Number of ticks simulated
-final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 927075                       # Simulator instruction rate (inst/s)
-host_op_rate                                   977372                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1241896591                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272260                       # Number of bytes of host memory used
-host_seconds                                   185.36                       # Real time elapsed on the host
-sim_insts                                   171842484                       # Number of instructions simulated
-sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            110336                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               220992                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       110656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          110656                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               480700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               479310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  960010                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          480700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             480700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              480700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              479310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 960010                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        460395389                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   171842484                       # Number of instructions committed
-system.cpu.committedOps                     181165371                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             143085668                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
-system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    143085668                       # number of integer instructions
-system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           242291225                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            626384530                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           190815535                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      40540779                       # number of memory refs
-system.cpu.num_load_insts                    27896144                       # Number of load instructions
-system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               460395388.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          40300312                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 138988213     76.51%     76.51% # Class of executed instruction
-system.cpu.op_class::IntMult                   908940      0.50%     77.01% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     77.01% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68% # Class of executed instruction
-system.cpu.op_class::MemRead                 27896144     15.36%     93.04% # Class of executed instruction
-system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  181650743                       # Class of executed instruction
-system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.571253                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.571253                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332903                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332903                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40117350                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40117350                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40117812                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40117812                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          688                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           688                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         1788                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     39940000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     39940000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     67838500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     67838500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    107778500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    107778500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    107778500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    107778500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40119138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40119138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40119601                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40119601                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000045                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60278.803132                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60245.108999                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
-system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          688                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1788                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39252000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     39252000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     66738500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     66738500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        61000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        61000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    105990500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    105990500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    106051500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    106051500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements              1506                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1147.958164                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           189857002                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              3051                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          62227.794821                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1147.958164                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.560526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.560526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          270                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          942                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.754395                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         379723157                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        379723157                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    189857002                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       189857002                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     189857002                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        189857002                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    189857002                       # number of overall hits
-system.cpu.icache.overall_hits::total       189857002                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         3051                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          3051                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         3051                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
-system.cpu.icache.overall_misses::total          3051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    124592000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    124592000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    124592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    124592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    124592000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    124592000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    189860053                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    189860053                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    189860053                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    189860053                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    189860053                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    189860053                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40836.447067                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40836.447067                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         1506                       # number of writebacks
-system.cpu.icache.writebacks::total              1506                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3051                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         3051                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         3051                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    121541000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    121541000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    121541000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    121541000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    121541000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    121541000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1675.610098                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2846                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2369                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.201351                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.037805                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.001518                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   503.570775                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035675                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.051136                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1679                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.072296                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            54045                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           54045                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         1448                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         1448                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1322                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1322                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           57                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           57                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1322                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           65                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1387                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1322                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           65                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1387                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1092                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1092                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1729                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1729                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          632                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          632                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1729                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1724                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3453                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     65004500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     65004500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    102968000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    102968000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     37629500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     37629500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    102968000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    102634000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    205602000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    102968000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    102634000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    205602000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         1448                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         1448                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1100                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1100                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         3051                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         3051                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          689                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          689                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         3051                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1789                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         4840                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         3051                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1789                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         4840                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992727                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992727                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.566699                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.566699                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.917271                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.917271                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.566699                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.963667                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.713430                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1729                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1729                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          632                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          632                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1729                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1724                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3453                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1729                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1724                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3453                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     54084500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     54084500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     85678000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     85678000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     85678000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     85394000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    171072000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     85678000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     85394000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    171072000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992727                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992727                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.566699                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.917271                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.917271                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.713430                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.713430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests         6386                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         1644                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests           64                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         1506                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1100                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1100                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         3051                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          689                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         7608                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3618                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             11226                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       291648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       115520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             407168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         4840                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.033471                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.179882                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               4678     96.65%     96.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                162      3.35%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           4840                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        4715000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       4576500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2683500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2361                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         6906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   6906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       220992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  220992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3453                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3453    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3453                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             3601500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           17265000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index cdb442c20..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,124 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.096723                       # Number of seconds simulated
-sim_ticks                                 96722945000                       # Number of ticks simulated
-final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 966666                       # Simulator instruction rate (inst/s)
-host_op_rate                                   966667                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              483336155                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225024                       # Number of bytes of host memory used
-host_seconds                                   200.12                       # Real time elapsed on the host
-sim_insts                                   193444518                       # Number of instructions simulated
-sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         773782140                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         223463413                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            997245553                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    773782140                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       773782140                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       72065412                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          72065412                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          193445535                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           57735068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             251180603                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          18976439                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             18976439                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data              22406                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                 22406                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999985319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2310345420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10310330739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999985319                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999985319                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           745070490                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              745070490                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999985319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3055415910                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11055401229                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  401                       # Number of system calls
-system.cpu.numCycles                        193445891                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   193444518                       # Number of instructions committed
-system.cpu.committedOps                     193444756                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             167974806                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
-system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8665106                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    167974806                       # number of integer instructions
-system.cpu.num_fp_insts                       1970372                       # number of float instructions
-system.cpu.num_int_register_reads           352617941                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          163060124                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      76733958                       # number of memory refs
-system.cpu.num_load_insts                    57735091                       # Number of load instructions
-system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               193445890.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          15132745                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     59.88% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     59.88% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  875036      0.45%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::MemRead                 57735103     29.85%     90.18% # Class of executed instruction
-system.cpu.op_class::MemWrite                18998867      9.82%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  193445773                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           251180603                       # Transaction distribution
-system.membus.trans_dist::ReadResp          251180603                       # Transaction distribution
-system.membus.trans_dist::WriteReq           18976439                       # Transaction distribution
-system.membus.trans_dist::WriteResp          18976439                       # Transaction distribution
-system.membus.trans_dist::SwapReq               22406                       # Transaction distribution
-system.membus.trans_dist::SwapResp              22406                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    386891070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    153467826                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              540358896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    773782140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    295708073                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              1069490213                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         270179448                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.715989                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.450942                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                76733913     28.40%     28.40% # Request fanout histogram
-system.membus.snoop_fanout::1               193445535     71.60%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           270179448                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index c87fb96c4..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,515 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.270600                       # Number of seconds simulated
-sim_ticks                                270599529500                       # Number of ticks simulated
-final_tick                               270599529500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1248385                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1248386                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1746300725                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 255364                       # Number of bytes of host memory used
-host_seconds                                   154.96                       # Real time elapsed on the host
-sim_insts                                   193444518                       # Number of instructions simulated
-sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            100864                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               331072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       230208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          230208                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3597                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1576                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5173                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               850733                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               372743                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1223476                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          850733                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             850733                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              850733                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              372743                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1223476                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  401                       # Number of system calls
-system.cpu.numCycles                        541199059                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   193444518                       # Number of instructions committed
-system.cpu.committedOps                     193444756                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             167974806                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
-system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8665106                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    167974806                       # number of integer instructions
-system.cpu.num_fp_insts                       1970372                       # number of float instructions
-system.cpu.num_int_register_reads           352617941                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          163060123                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      76733958                       # number of memory refs
-system.cpu.num_load_insts                    57735091                       # Number of load instructions
-system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               541199058.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          15132745                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              13329871      6.89%      6.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                 102506896     52.99%     59.88% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     59.88% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     59.88% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  875036      0.45%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.33% # Class of executed instruction
-system.cpu.op_class::MemRead                 57735103     29.85%     90.18% # Class of executed instruction
-system.cpu.op_class::MemWrite                18998867      9.82%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  193445773                       # Class of executed instruction
-system.cpu.dcache.tags.replacements                 2                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1237.159344                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            76732337                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1576                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          48688.031091                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1237.159344                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.302041                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.302041                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1574                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1237                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.384277                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         153469402                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        153469402                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     57734570                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        57734570                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18975362                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data        22405                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total           22405                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data      76709932                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         76709932                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     76709932                       # number of overall hits
-system.cpu.dcache.overall_hits::total        76709932                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           498                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1077                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1077                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data            1                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total             1                       # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data         1575                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1575                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1575                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1575                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     30877500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     30877500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     66775000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     66775000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        62000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        62000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     97652500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     97652500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     97652500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     97652500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     57735068                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     57735068                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18976439                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18976439                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data        22406                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total        22406                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     76711507                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     76711507                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     76711507                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     76711507                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000009                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000009                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000057                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000057                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000045                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total     0.000045                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000021                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000021                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000021                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000021                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        62000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        62000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62001.587302                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62001.587302                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
-system.cpu.dcache.writebacks::total                 2                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1077                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1077                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data            1                       # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total            1                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1575                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1575                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1575                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1575                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     30379500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     30379500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     65698000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     65698000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        61000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        61000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     96077500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     96077500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     96077500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     96077500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000057                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000057                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000021                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000021                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        61000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        61000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements             10362                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1591.528232                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           193433248                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12288                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15741.638021                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1591.528232                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.777113                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.777113                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1926                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          624                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          514                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          687                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.940430                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         386903360                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        386903360                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    193433248                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       193433248                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     193433248                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        193433248                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    193433248                       # number of overall hits
-system.cpu.icache.overall_hits::total       193433248                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12288                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12288                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12288                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12288                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12288                       # number of overall misses
-system.cpu.icache.overall_misses::total         12288                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    336231000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    336231000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    336231000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    336231000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    336231000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    336231000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    193445536                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    193445536                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    193445536                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    193445536                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    193445536                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    193445536                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000064                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000064                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000064                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000064                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000064                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000064                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27362.548828                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27362.548828                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        10362                       # number of writebacks
-system.cpu.icache.writebacks::total             10362                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12288                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12288                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12288                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12288                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12288                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    323943000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    323943000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    323943000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    323943000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    323943000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    323943000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000064                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000064                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000064                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2678.246108                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              19053                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4097                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.650476                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     0.000456                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2275.203530                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   403.042121                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069434                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.081734                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4097                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          625                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2688                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.125031                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           198999                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          198999                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks            2                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total            2                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        10362                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        10362                       # number of WritebackClean hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8691                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8691                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8691                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8691                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8691                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8691                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1078                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1078                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3597                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3597                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          498                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          498                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3597                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1576                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5173                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3597                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1576                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5173                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     64142000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     64142000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    214049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    214049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     29632000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     29632000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    214049500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     93774000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    307823500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    214049500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     93774000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    307823500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks            2                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total            2                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        10362                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        10362                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1078                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1078                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12288                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        12288                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          498                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          498                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        12288                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1576                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13864                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        12288                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1576                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13864                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.292725                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.292725                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.292725                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.373125                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.292725                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.373125                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1078                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1078                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3597                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3597                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          498                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          498                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3597                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1576                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3597                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1576                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     53362000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     53362000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    178079500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    178079500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     24652000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     24652000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    178079500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     78014000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    256093500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    178079500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     78014000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    256093500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.292725                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.373125                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.373125                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        24228                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        10365                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         12786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        10362                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1078                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1078                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12288                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          498                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        34938                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             38092                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1449600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       100992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1550592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13864                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000072                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.008493                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13863     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  1      0.01%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13864                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       22478000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18432000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2364000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4095                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1078                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1078                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4095                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10346                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10346                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       331072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  331072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5173                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5173    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5173                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             5203000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           25865000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 5a46e9bad..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,127 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.131393                       # Number of seconds simulated
-sim_ticks                                131393279000                       # Number of ticks simulated
-final_tick                               131393279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 550181                       # Simulator instruction rate (inst/s)
-host_op_rate                                   922154                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              547357033                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269224                       # Number of bytes of host memory used
-host_seconds                                   240.05                       # Real time elapsed on the host
-sim_insts                                   132071193                       # Number of instructions simulated
-sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1387954936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         310423752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1698378688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1387954936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1387954936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       99822191                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          99822191                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          173494367                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           56682005                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             230176372                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          20515731                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             20515731                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          10563363260                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2362554267                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             12925917527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     10563363260                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        10563363260                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           759720678                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              759720678                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         10563363260                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3122274945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13685638205                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        262786559                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   132071193                       # Number of instructions committed
-system.cpu.committedOps                     221363385                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             219019986                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
-system.cpu.num_func_calls                     1595632                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    219019986                       # number of integer instructions
-system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           519996939                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          201355989                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads             96962463                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            56242058                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      77165304                       # number of memory refs
-system.cpu.num_load_insts                    56649587                       # Number of load instructions
-system.cpu.num_store_insts                   20515717                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               262786558.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          12326938                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
-system.cpu.op_class::IntAlu                 134111833     60.58%     61.12% # Class of executed instruction
-system.cpu.op_class::IntMult                   772953      0.35%     61.47% # Class of executed instruction
-system.cpu.op_class::IntDiv                   7031501      3.18%     64.64% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 1105073      0.50%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::MemRead                 56649587     25.59%     90.73% # Class of executed instruction
-system.cpu.op_class::MemWrite                20515717      9.27%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  221363385                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           230176372                       # Transaction distribution
-system.membus.trans_dist::ReadResp          230176372                       # Transaction distribution
-system.membus.trans_dist::WriteReq           20515731                       # Transaction distribution
-system.membus.trans_dist::WriteResp          20515731                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    346988734                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total    346988734                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    154395472                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total    154395472                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              501384206                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1387954936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total   1387954936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    410245943                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total    410245943                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              1798200879                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         250692103                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.692062                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.461641                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                77197736     30.79%     30.79% # Request fanout histogram
-system.membus.snoop_fanout::1               173494367     69.21%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           250692103                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 25c6ff3ba..e69de29bb 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,507 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.250987                       # Number of seconds simulated
-sim_ticks                                250987138500                       # Number of ticks simulated
-final_tick                               250987138500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 637690                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1068827                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1211861746                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298388                       # Number of bytes of host memory used
-host_seconds                                   207.11                       # Real time elapsed on the host
-sim_insts                                   132071193                       # Number of instructions simulated
-sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            121280                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               303040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       181760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          181760                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2840                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1895                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  4735                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               724181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               483212                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1207393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          724181                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             724181                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              724181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              483212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1207393                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        501974277                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   132071193                       # Number of instructions committed
-system.cpu.committedOps                     221363385                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             219019986                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
-system.cpu.num_func_calls                     1595632                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    219019986                       # number of integer instructions
-system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           519996939                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          201355989                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads             96962463                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            56242058                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      77165304                       # number of memory refs
-system.cpu.num_load_insts                    56649587                       # Number of load instructions
-system.cpu.num_store_insts                   20515717                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               501974276.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          12326938                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               1176721      0.53%      0.53% # Class of executed instruction
-system.cpu.op_class::IntAlu                 134111833     60.58%     61.12% # Class of executed instruction
-system.cpu.op_class::IntMult                   772953      0.35%     61.47% # Class of executed instruction
-system.cpu.op_class::IntDiv                   7031501      3.18%     64.64% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 1105073      0.50%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.14% # Class of executed instruction
-system.cpu.op_class::MemRead                 56649587     25.59%     90.73% # Class of executed instruction
-system.cpu.op_class::MemWrite                20515717      9.27%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  221363385                       # Class of executed instruction
-system.cpu.dcache.tags.replacements                41                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.414730                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            77195831                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1905                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40522.745932                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.414730                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332865                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332865                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1864                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          472                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1328                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.455078                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         154397377                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        154397377                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     56681678                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        56681678                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514153                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514153                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      77195831                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         77195831                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     77195831                       # number of overall hits
-system.cpu.dcache.overall_hits::total        77195831                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          327                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           327                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1578                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1578                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1905                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1905                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1905                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1905                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     19933500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     19933500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     97691000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     97691000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    117624500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    117624500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    117624500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    117624500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     56682005                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     56682005                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     77197736                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     77197736                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     77197736                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     77197736                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000006                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000077                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000077                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61745.144357                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61745.144357                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks            7                       # number of writebacks
-system.cpu.dcache.writebacks::total                 7                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          327                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          327                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1578                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1578                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1905                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1905                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1905                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1905                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     19606500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     19606500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     96113000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     96113000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    115719500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    115719500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    115719500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    115719500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000077                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000077                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357                       # average overall mshr miss latency
-system.cpu.icache.tags.replacements              2836                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1455.245085                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           173489673                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4694                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          36959.879207                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1455.245085                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.710569                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.710569                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          415                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          869                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         346993428                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        346993428                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    173489673                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       173489673                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     173489673                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        173489673                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    173489673                       # number of overall hits
-system.cpu.icache.overall_hits::total       173489673                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4694                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4694                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4694                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4694                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4694                       # number of overall misses
-system.cpu.icache.overall_misses::total          4694                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    200232500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    200232500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    200232500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    200232500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    200232500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    200232500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    173494367                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    173494367                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    173494367                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    173494367                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    173494367                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    173494367                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000027                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000027                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42657.115467                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42657.115467                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         2836                       # number of writebacks
-system.cpu.icache.writebacks::total              2836                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4694                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4694                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4694                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4694                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4694                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4694                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195538500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    195538500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195538500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    195538500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195538500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    195538500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000027                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467                       # average overall mshr miss latency
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2058.105553                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               4732                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3164                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.495575                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     0.021821                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1829.911143                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   228.172589                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055844                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.062808                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3164                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          497                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2064                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.096558                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            80550                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           80550                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks            7                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total            7                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2836                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         2836                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1854                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1854                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data            7                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total            7                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1854                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           10                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1864                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1854                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           10                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1864                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1575                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1575                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2840                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2840                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          320                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          320                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2840                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1895                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          4735                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2840                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1895                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         4735                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     93713500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     93713500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    169013000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    169013000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     19042000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     19042000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    169013000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    112755500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    281768500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    169013000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    112755500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    281768500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks            7                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total            7                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         2836                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         2836                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4694                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4694                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          327                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          327                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4694                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6599                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4694                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6599                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.998099                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.998099                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.605028                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.605028                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.978593                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.978593                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.605028                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.994751                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.717533                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.605028                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.994751                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.717533                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1575                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1575                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2840                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2840                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          320                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          320                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2840                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1895                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4735                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2840                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1895                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4735                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     77963500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     77963500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    140613000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    140613000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15842000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15842000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    140613000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     93805500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    234418500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    140613000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     93805500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    234418500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.998099                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.998099                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.605028                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.978593                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.978593                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.717533                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.717533                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests         9476                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         2878                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          5021                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2836                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           34                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4694                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          327                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12224                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3851                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             16075                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       481920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       122368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             604288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6599                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000152                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012310                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               6598     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  1      0.02%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6599                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7581000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7041000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2857500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3160                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1575                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1575                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3160                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         9470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total         9470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   9470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       303040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       303040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  303040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              4735                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    4735    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                4735                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4771000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           23675000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
-- 
cgit v1.2.3