From 84f138ba96201431513eb2ae5f847389ac731aa2 Mon Sep 17 00:00:00 2001
From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Thu, 21 Jul 2016 17:19:18 +0100
Subject: stats: update references

---
 .../ref/alpha/linux/minor-timing/config.ini        |  58 +-
 .../00.hello/ref/alpha/linux/minor-timing/simerr   |   1 +
 .../00.hello/ref/alpha/linux/minor-timing/simout   |  10 +-
 .../ref/alpha/linux/minor-timing/stats.txt         | 552 +++++++++---------
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  |  57 +-
 .../se/00.hello/ref/alpha/linux/o3-timing/simerr   |   1 +
 .../se/00.hello/ref/alpha/linux/o3-timing/simout   |  10 +-
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   |  10 +-
 .../ref/alpha/linux/simple-atomic/config.ini       |  22 +-
 .../00.hello/ref/alpha/linux/simple-atomic/simerr  |   1 +
 .../00.hello/ref/alpha/linux/simple-atomic/simout  |   8 +-
 .../ref/alpha/linux/simple-atomic/stats.txt        |   9 +-
 .../ref/alpha/linux/simple-timing/config.ini       |  57 +-
 .../00.hello/ref/alpha/linux/simple-timing/simerr  |   1 +
 .../00.hello/ref/alpha/linux/simple-timing/simout  |   8 +-
 .../ref/alpha/linux/simple-timing/stats.txt        |  12 +-
 .../ref/alpha/tru64/minor-timing/config.ini        |  58 +-
 .../00.hello/ref/alpha/tru64/minor-timing/simerr   |   1 +
 .../00.hello/ref/alpha/tru64/minor-timing/simout   |  12 +-
 .../ref/alpha/tru64/minor-timing/stats.txt         | 508 ++++++++--------
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  |  57 +-
 .../se/00.hello/ref/alpha/tru64/o3-timing/simerr   |   1 +
 .../se/00.hello/ref/alpha/tru64/o3-timing/simout   |  12 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   |  12 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |  22 +-
 .../00.hello/ref/alpha/tru64/simple-atomic/simerr  |   1 +
 .../00.hello/ref/alpha/tru64/simple-atomic/simout  |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  11 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |  57 +-
 .../00.hello/ref/alpha/tru64/simple-timing/simerr  |   1 +
 .../00.hello/ref/alpha/tru64/simple-timing/simout  |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  10 +-
 .../00.hello/ref/arm/linux/minor-timing/config.ini |  78 ++-
 .../se/00.hello/ref/arm/linux/minor-timing/simerr  |   1 +
 .../se/00.hello/ref/arm/linux/minor-timing/simout  |  12 +-
 .../00.hello/ref/arm/linux/minor-timing/stats.txt  | 648 +++++++++++----------
 .../ref/arm/linux/o3-timing-checker/config.ini     | 102 +++-
 .../ref/arm/linux/o3-timing-checker/simerr         |   2 +
 .../ref/arm/linux/o3-timing-checker/simout         |   8 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt      |  12 +-
 .../se/00.hello/ref/arm/linux/o3-timing/config.ini |  82 ++-
 .../se/00.hello/ref/arm/linux/o3-timing/simerr     |   1 +
 .../se/00.hello/ref/arm/linux/o3-timing/simout     |   8 +-
 .../se/00.hello/ref/arm/linux/o3-timing/stats.txt  |  12 +-
 .../linux/simple-atomic-dummychecker/config.ini    |  67 ++-
 .../arm/linux/simple-atomic-dummychecker/simerr    |   2 +
 .../arm/linux/simple-atomic-dummychecker/simout    |  10 +-
 .../arm/linux/simple-atomic-dummychecker/stats.txt |   9 +-
 .../ref/arm/linux/simple-atomic/config.ini         |  42 +-
 .../se/00.hello/ref/arm/linux/simple-atomic/simerr |   1 +
 .../se/00.hello/ref/arm/linux/simple-atomic/simout |   8 +-
 .../00.hello/ref/arm/linux/simple-atomic/stats.txt |   9 +-
 .../ref/arm/linux/simple-timing/config.ini         |  77 ++-
 .../se/00.hello/ref/arm/linux/simple-timing/simerr |   1 +
 .../se/00.hello/ref/arm/linux/simple-timing/simout |   8 +-
 .../00.hello/ref/arm/linux/simple-timing/stats.txt |  12 +-
 .../00.hello/ref/mips/linux/o3-timing/config.ini   |  57 +-
 .../se/00.hello/ref/mips/linux/o3-timing/simerr    |   1 +
 .../se/00.hello/ref/mips/linux/o3-timing/simout    |  10 +-
 .../se/00.hello/ref/mips/linux/o3-timing/stats.txt |  10 +-
 .../ref/mips/linux/simple-atomic/config.ini        |  22 +-
 .../00.hello/ref/mips/linux/simple-atomic/simerr   |   1 +
 .../00.hello/ref/mips/linux/simple-atomic/simout   |   8 +-
 .../ref/mips/linux/simple-atomic/stats.txt         |   9 +-
 .../ref/mips/linux/simple-timing/config.ini        |  57 +-
 .../00.hello/ref/mips/linux/simple-timing/simerr   |   1 +
 .../00.hello/ref/mips/linux/simple-timing/simout   |   8 +-
 .../ref/mips/linux/simple-timing/stats.txt         |  12 +-
 .../00.hello/ref/power/linux/o3-timing/config.ini  |  57 +-
 .../se/00.hello/ref/power/linux/o3-timing/simerr   |   1 +
 .../se/00.hello/ref/power/linux/o3-timing/simout   |  12 +-
 .../00.hello/ref/power/linux/o3-timing/stats.txt   |  12 +-
 .../ref/power/linux/simple-atomic/config.ini       |  22 +-
 .../00.hello/ref/power/linux/simple-atomic/simerr  |   1 +
 .../00.hello/ref/power/linux/simple-atomic/simout  |  10 +-
 .../ref/power/linux/simple-atomic/stats.txt        |   9 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  22 +-
 .../00.hello/ref/sparc/linux/simple-atomic/simerr  |   1 +
 .../00.hello/ref/sparc/linux/simple-atomic/simout  |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   9 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  57 +-
 .../00.hello/ref/sparc/linux/simple-timing/simerr  |   1 +
 .../00.hello/ref/sparc/linux/simple-timing/simout  |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |  12 +-
 .../se/00.hello/ref/x86/linux/o3-timing/config.ini |  72 ++-
 .../se/00.hello/ref/x86/linux/o3-timing/simerr     |   1 +
 .../se/00.hello/ref/x86/linux/o3-timing/simout     |  12 +-
 .../se/00.hello/ref/x86/linux/o3-timing/stats.txt  |  12 +-
 .../ref/x86/linux/simple-atomic/config.ini         |  37 +-
 .../se/00.hello/ref/x86/linux/simple-atomic/simerr |   1 +
 .../se/00.hello/ref/x86/linux/simple-atomic/simout |  10 +-
 .../00.hello/ref/x86/linux/simple-atomic/stats.txt |  11 +-
 .../ref/x86/linux/simple-timing/config.ini         |  72 ++-
 .../se/00.hello/ref/x86/linux/simple-timing/simerr |   1 +
 .../se/00.hello/ref/x86/linux/simple-timing/simout |  10 +-
 .../00.hello/ref/x86/linux/simple-timing/stats.txt |  12 +-
 .../ref/alpha/linux/o3-timing-mt/config.ini        |  59 +-
 .../ref/alpha/linux/o3-timing-mt/simerr            |   2 +
 .../ref/alpha/linux/o3-timing-mt/simout            |  10 +-
 .../ref/alpha/linux/o3-timing-mt/stats.txt         |  10 +-
 .../ref/sparc/linux/o3-timing/config.ini           |  57 +-
 .../02.insttest/ref/sparc/linux/o3-timing/simerr   |   1 +
 .../02.insttest/ref/sparc/linux/o3-timing/simout   |  12 +-
 .../ref/sparc/linux/o3-timing/stats.txt            |  12 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  22 +-
 .../ref/sparc/linux/simple-atomic/simerr           |   1 +
 .../ref/sparc/linux/simple-atomic/simout           |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |  11 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  57 +-
 .../ref/sparc/linux/simple-timing/simerr           |   1 +
 .../ref/sparc/linux/simple-timing/simout           |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |  12 +-
 .../alpha/linux/learning-gem5-p1-simple/config.ini |  20 +
 .../ref/alpha/linux/learning-gem5-p1-simple/simerr |   1 +
 .../ref/alpha/linux/learning-gem5-p1-simple/simout |   8 +-
 .../alpha/linux/learning-gem5-p1-simple/stats.txt  |   9 +-
 .../linux/learning-gem5-p1-two-level/config.ini    |  55 ++
 .../alpha/linux/learning-gem5-p1-two-level/simerr  |   1 +
 .../alpha/linux/learning-gem5-p1-two-level/simout  |   8 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |  10 +-
 .../arm/linux/learning-gem5-p1-simple/config.ini   |  40 ++
 .../ref/arm/linux/learning-gem5-p1-simple/simerr   |   1 +
 .../ref/arm/linux/learning-gem5-p1-simple/simout   |   8 +-
 .../arm/linux/learning-gem5-p1-simple/stats.txt    |  11 +-
 .../linux/learning-gem5-p1-two-level/config.ini    |  75 +++
 .../arm/linux/learning-gem5-p1-two-level/simerr    |   1 +
 .../arm/linux/learning-gem5-p1-two-level/simout    |   8 +-
 .../arm/linux/learning-gem5-p1-two-level/stats.txt |  12 +-
 .../mips/linux/learning-gem5-p1-simple/config.ini  |  20 +
 .../ref/mips/linux/learning-gem5-p1-simple/simerr  |   1 +
 .../ref/mips/linux/learning-gem5-p1-simple/simout  |   8 +-
 .../mips/linux/learning-gem5-p1-simple/stats.txt   |   9 +-
 .../linux/learning-gem5-p1-two-level/config.ini    |  55 ++
 .../mips/linux/learning-gem5-p1-two-level/simerr   |   1 +
 .../mips/linux/learning-gem5-p1-two-level/simout   |   8 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |  10 +-
 .../sparc/linux/learning-gem5-p1-simple/config.ini |  20 +
 .../ref/sparc/linux/learning-gem5-p1-simple/simerr |   1 +
 .../ref/sparc/linux/learning-gem5-p1-simple/simout |  10 +-
 .../sparc/linux/learning-gem5-p1-simple/stats.txt  |   9 +-
 .../linux/learning-gem5-p1-two-level/config.ini    |  55 ++
 .../sparc/linux/learning-gem5-p1-two-level/simerr  |   1 +
 .../sparc/linux/learning-gem5-p1-two-level/simout  |  10 +-
 .../linux/learning-gem5-p1-two-level/stats.txt     |  10 +-
 .../x86/linux/learning-gem5-p1-simple/config.ini   |  35 ++
 .../ref/x86/linux/learning-gem5-p1-simple/simerr   |   1 +
 .../ref/x86/linux/learning-gem5-p1-simple/simout   |  10 +-
 .../x86/linux/learning-gem5-p1-simple/stats.txt    |  11 +-
 .../linux/learning-gem5-p1-two-level/config.ini    |  70 +++
 .../x86/linux/learning-gem5-p1-two-level/simerr    |   1 +
 .../x86/linux/learning-gem5-p1-two-level/simout    |  10 +-
 .../x86/linux/learning-gem5-p1-two-level/stats.txt |  12 +-
 .../10.mcf/ref/arm/linux/simple-atomic/config.ini  |  44 +-
 .../se/10.mcf/ref/arm/linux/simple-atomic/simerr   |   1 +
 .../se/10.mcf/ref/arm/linux/simple-atomic/simout   |   8 +-
 .../10.mcf/ref/arm/linux/simple-atomic/stats.txt   |  11 +-
 .../10.mcf/ref/arm/linux/simple-timing/config.ini  |  79 ++-
 .../se/10.mcf/ref/arm/linux/simple-timing/simerr   |   1 +
 .../se/10.mcf/ref/arm/linux/simple-timing/simout   |   8 +-
 .../10.mcf/ref/arm/linux/simple-timing/stats.txt   |  12 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  24 +-
 .../se/10.mcf/ref/sparc/linux/simple-atomic/simerr |   1 +
 .../se/10.mcf/ref/sparc/linux/simple-atomic/simout |  10 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |  11 +-
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |  39 +-
 .../se/10.mcf/ref/x86/linux/simple-atomic/simerr   |   1 +
 .../se/10.mcf/ref/x86/linux/simple-atomic/simout   |  10 +-
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |  11 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |  22 +-
 .../se/30.eon/ref/alpha/tru64/simple-atomic/simerr |   1 +
 .../se/30.eon/ref/alpha/tru64/simple-atomic/simout |  10 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |  11 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini        | 142 ++++-
 .../ref/sparc/linux/o3-timing-mp/simerr            |   5 +
 .../ref/sparc/linux/o3-timing-mp/simout            |  72 +--
 .../ref/sparc/linux/o3-timing-mp/stats.txt         |  12 +-
 .../ref/sparc/linux/simple-atomic-mp/config.ini    | 142 ++++-
 .../ref/sparc/linux/simple-atomic-mp/simerr        |   5 +
 .../ref/sparc/linux/simple-atomic-mp/simout        |  10 +-
 .../ref/sparc/linux/simple-atomic-mp/stats.txt     |  12 +-
 .../ref/sparc/linux/simple-timing-mp/config.ini    | 142 ++++-
 .../ref/sparc/linux/simple-timing-mp/simerr        |   5 +
 .../ref/sparc/linux/simple-timing-mp/simout        |  60 +-
 .../ref/sparc/linux/simple-timing-mp/stats.txt     |  12 +-
 .../ref/null/none/memtest-filter/config.ini        | 150 +++++
 .../50.memtest/ref/null/none/memtest-filter/simerr | 146 ++---
 .../50.memtest/ref/null/none/memtest-filter/simout |  12 +-
 .../ref/null/none/memtest-filter/stats.txt         |   8 +-
 .../se/50.memtest/ref/null/none/memtest/config.ini | 150 +++++
 .../se/50.memtest/ref/null/none/memtest/simerr     | 146 ++---
 .../se/50.memtest/ref/null/none/memtest/simout     |  12 +-
 .../se/50.memtest/ref/null/none/memtest/stats.txt  |   8 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |  22 +-
 .../50.vortex/ref/alpha/tru64/simple-atomic/simerr |   1 +
 .../50.vortex/ref/alpha/tru64/simple-atomic/simout |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  11 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |  57 +-
 .../50.vortex/ref/alpha/tru64/simple-timing/simerr |   1 +
 .../50.vortex/ref/alpha/tru64/simple-timing/simout |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  12 +-
 .../ref/arm/linux/simple-atomic/config.ini         |  42 +-
 .../50.vortex/ref/arm/linux/simple-atomic/simerr   |   1 +
 .../50.vortex/ref/arm/linux/simple-atomic/simout   |   8 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |  11 +-
 .../ref/arm/linux/simple-timing/config.ini         |  77 ++-
 .../50.vortex/ref/arm/linux/simple-timing/simerr   |   1 +
 .../50.vortex/ref/arm/linux/simple-timing/simout   |   8 +-
 .../ref/arm/linux/simple-timing/stats.txt          |  12 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  22 +-
 .../50.vortex/ref/sparc/linux/simple-atomic/simerr |   1 +
 .../50.vortex/ref/sparc/linux/simple-atomic/simout |   8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |  11 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  57 +-
 .../50.vortex/ref/sparc/linux/simple-timing/simerr |   1 +
 .../50.vortex/ref/sparc/linux/simple-timing/simout |   8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |  12 +-
 .../51.memcheck/ref/null/none/memcheck/stats.txt   |  16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |  22 +-
 .../70.twolf/ref/alpha/tru64/simple-atomic/simerr  |   1 +
 .../70.twolf/ref/alpha/tru64/simple-atomic/simout  |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  11 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |  57 +-
 .../70.twolf/ref/alpha/tru64/simple-timing/simerr  |   1 +
 .../70.twolf/ref/alpha/tru64/simple-timing/simout  |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  12 +-
 .../ref/arm/linux/simple-atomic/config.ini         |  42 +-
 .../se/70.twolf/ref/arm/linux/simple-atomic/simerr |   1 +
 .../se/70.twolf/ref/arm/linux/simple-atomic/simout |  10 +-
 .../70.twolf/ref/arm/linux/simple-atomic/stats.txt |  11 +-
 .../ref/arm/linux/simple-timing/config.ini         |  77 ++-
 .../se/70.twolf/ref/arm/linux/simple-timing/simerr |   1 +
 .../se/70.twolf/ref/arm/linux/simple-timing/simout |  10 +-
 .../70.twolf/ref/arm/linux/simple-timing/stats.txt |  12 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  22 +-
 .../70.twolf/ref/sparc/linux/simple-atomic/simerr  |   1 +
 .../70.twolf/ref/sparc/linux/simple-atomic/simout  |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |  11 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  57 +-
 .../70.twolf/ref/sparc/linux/simple-timing/simerr  |   1 +
 .../70.twolf/ref/sparc/linux/simple-timing/simout  |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |  12 +-
 .../ref/x86/linux/simple-atomic/config.ini         |  37 +-
 .../se/70.twolf/ref/x86/linux/simple-atomic/simerr |   1 +
 .../se/70.twolf/ref/x86/linux/simple-atomic/simout |  10 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |  11 +-
 .../ref/x86/linux/simple-timing/config.ini         |  72 ++-
 .../se/70.twolf/ref/x86/linux/simple-timing/simerr |   1 +
 .../se/70.twolf/ref/x86/linux/simple-timing/simout |  10 +-
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |  12 +-
 249 files changed, 5340 insertions(+), 1650 deletions(-)

(limited to 'tests/quick/se')

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index b45f7c576..6320b231e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -59,6 +64,7 @@ decodeCycleInput=true
 decodeInputBufferSize=3
 decodeInputWidth=2
 decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -101,12 +107,17 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
 socket_id=0
 switched_out=false
 system=system
+threadPolicy=RoundRobin
 tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -142,12 +153,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -166,8 +182,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -566,12 +587,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -590,8 +616,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -616,12 +647,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -640,8 +676,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -649,10 +690,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -683,7 +729,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -715,10 +761,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -762,6 +813,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -773,7 +825,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
index 7264993fd..70f465dc7 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:56:23
-gem5 executing on phenom, pid 28115
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:27
+gem5 executing on e108600-lin, pid 39611
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 37629000 because target called exit()
+Exiting @ tick 37822000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 7fa71daaa..20c464e74 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000037                       # Number of seconds simulated
-sim_ticks                                    37494000                       # Number of ticks simulated
-final_tick                                   37494000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000038                       # Number of seconds simulated
+sim_ticks                                    37822000                       # Number of ticks simulated
+final_tick                                   37822000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200557                       # Simulator instruction rate (inst/s)
-host_op_rate                                   200498                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1171902214                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294520                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 100508                       # Simulator instruction rate (inst/s)
+host_op_rate                                   100471                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              592356577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249008                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6413                       # Number of instructions simulated
 sim_ops                                          6413                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                34048                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           23232                       # Nu
 system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   532                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            619619139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            288472822                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               908091961                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       619619139                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          619619139                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           619619139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           288472822                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              908091961                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            614245677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            285971128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               900216805                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       614245677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          614245677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           614245677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           285971128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              900216805                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           532                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         532                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        37389500                       # Total gap between requests
+system.physmem.totGap                        37718000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -188,32 +188,32 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           82                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      387.902439                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     251.688412                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.441746                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             19     23.17%     23.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     21.95%     45.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           11     13.41%     58.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           10     12.20%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            1      1.22%     71.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            6      7.32%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      4.88%     84.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            5      6.10%     90.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            8      9.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      385.560976                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     252.880176                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.081835                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             17     20.73%     20.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           21     25.61%     46.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            9     10.98%     57.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           11     13.41%     70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      4.88%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.66%     79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      3.66%     82.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            5      6.10%     89.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     10.98%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             82                       # Bytes accessed per row activation
-system.physmem.totQLat                        3129000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13104000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3215000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13190000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2660000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5881.58                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6043.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24631.58                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         908.09                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24793.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         900.22                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      908.09                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      900.22                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.09                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.09                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -221,7 +221,7 @@ system.physmem.readRowHits                        438                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.33                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70281.02                       # Average gap between requests
+system.physmem.avgGap                        70898.50                       # Average gap between requests
 system.physmem.pageHitRate                      82.33                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     234360                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     127875                       # Energy for precharge commands per rank (pJ)
@@ -232,60 +232,60 @@ system.physmem_0.actBackEnergy               21404070                       # En
 system.physmem_0.preBackEnergy                  67500                       # Energy for precharge background per rank (pJ)
 system.physmem_0.totalEnergy                 25911645                       # Total energy per rank (pJ)
 system.physmem_0.averagePower              825.080242                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          16000                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE         366250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        30362750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        30363250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     340200                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     185625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1552200                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   1521000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               20432790                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 920250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 25465305                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              810.835582                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1481500                       # Time in different power states
+system.physmem_1.actBackEnergy               20148930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                1168500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 25398495                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              808.740487                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1794750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        28986000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        28584000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2009                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1241                       # Number of conditional branches predicted
+system.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2005                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1239                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               379                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1611                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     378                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1607                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     377                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             23.463687                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     234                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             23.459863                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     235                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             338                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups             336                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 13                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              325                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses              323                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          113                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1378                       # DTB read hits
+system.cpu.dtb.read_hits                         1365                       # DTB read hits
 system.cpu.dtb.read_misses                         11                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1389                       # DTB read accesses
-system.cpu.dtb.write_hits                         885                       # DTB write hits
+system.cpu.dtb.read_accesses                     1376                       # DTB read accesses
+system.cpu.dtb.write_hits                         884                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     888                       # DTB write accesses
-system.cpu.dtb.data_hits                         2263                       # DTB hits
+system.cpu.dtb.write_accesses                     887                       # DTB write accesses
+system.cpu.dtb.data_hits                         2249                       # DTB hits
 system.cpu.dtb.data_misses                         14                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2277                       # DTB accesses
-system.cpu.itb.fetch_hits                        2687                       # ITB hits
+system.cpu.dtb.data_accesses                     2263                       # DTB accesses
+system.cpu.itb.fetch_hits                        2686                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2704                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2703                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,16 +299,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        37494000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            74988                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        37822000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            75644                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6413                       # Number of instructions committed
 system.cpu.committedOps                          6413                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1148                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1095                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              11.693123                       # CPI: cycles per instruction
-system.cpu.ipc                               0.085520                       # IPC: instructions per cycle
+system.cpu.cpi                              11.795416                       # CPI: cycles per instruction
+system.cpu.ipc                               0.084779                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                  19      0.30%      0.30% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    4331     67.53%     67.83% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      1      0.02%     67.85% # Class of committed instruction
@@ -344,87 +344,85 @@ system.cpu.op_class_0::MemWrite                   868     13.54%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     6413                       # Class of committed instruction
-system.cpu.tickCycles                           12653                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           62335                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                           12651                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           62993                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.135823                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1980                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           103.701168                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1990                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.715976                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.775148                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   104.135823                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025424                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025424                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.701168                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025318                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025318                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4583                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4583                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1240                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1240                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4591                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4591                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1250                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1250                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1980                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1980                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1980                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1980                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          1990                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1990                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1990                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1990                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           96                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            96                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          227                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          227                       # number of overall misses
-system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8280500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8280500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      9164500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      9164500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17445000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17445000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17445000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17445000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1342                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1342                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          221                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            221                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          221                       # number of overall misses
+system.cpu.dcache.overall_misses::total           221                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7590000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7590000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      9158000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      9158000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16748000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16748000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16748000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16748000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1346                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1346                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2207                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2207                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2207                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2207                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076006                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076006                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2211                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2211                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2211                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2211                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.071322                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.071322                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.102855                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.102855                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102855                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102855                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81181.372549                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 81181.372549                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73316                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        73316                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76850.220264                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76850.220264                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76850.220264                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099955                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099955                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.099955                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.099955                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73264                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        73264                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75782.805430                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75782.805430                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           58                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           52                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           52                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           52                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
@@ -433,83 +431,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          169
 system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7723000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7723000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5385500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5385500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13108500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13108500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13108500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13108500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071535                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071535                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7494000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7494000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5379500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5379500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12873500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12873500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12873500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12873500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071322                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071322                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076575                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076575                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076575                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076575                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076436                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076436                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           175.312988                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2323                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           174.485780                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2322                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               364                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.381868                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.379121                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   175.312988                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085602                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085602                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   174.485780                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085198                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085198                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.177734                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5738                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5738                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         2323                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2323                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2323                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2323                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2323                       # number of overall hits
-system.cpu.icache.overall_hits::total            2323                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5736                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5736                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         2322                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2322                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2322                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2322                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2322                       # number of overall hits
+system.cpu.icache.overall_hits::total            2322                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           364                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
 system.cpu.icache.overall_misses::total           364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     27766000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     27766000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     27766000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     27766000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     27766000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     27766000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2687                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2687                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2687                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2687                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2687                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2687                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.135467                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.135467                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.135467                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.135467                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.135467                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.135467                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76280.219780                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76280.219780                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76280.219780                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76280.219780                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76280.219780                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     28087500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     28087500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     28087500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     28087500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     28087500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     28087500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2686                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2686                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2686                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2686                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2686                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2686                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.135517                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.135517                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.135517                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.135517                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.135517                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.135517                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77163.461538                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77163.461538                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -522,43 +520,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          364
 system.cpu.icache.demand_mshr_misses::total          364                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          364                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27402000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27402000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27402000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27402000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27402000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27402000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135467                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135467                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135467                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.135467                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135467                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.135467                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27723500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     27723500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27723500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     27723500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27723500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     27723500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135517                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.135517                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.135517                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.336913                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          232.271171                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              459                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002179                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.327844                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    58.009069                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005351                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001770                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007121                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   174.500375                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.770796                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005325                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001763                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007088                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014008                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4796                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4796                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -577,18 +575,18 @@ system.cpu.l2cache.demand_misses::total           532                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          532                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     26844000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     26844000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7577500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      7577500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     26844000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12852500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     39696500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     26844000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12852500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     39696500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5270000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5270000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27166000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27166000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7348500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7348500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27166000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12618500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39784500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27166000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12618500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39784500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          364                       # number of ReadCleanReq accesses(hits+misses)
@@ -613,18 +611,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.998124                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997253                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998124                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73950.413223                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73950.413223                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78932.291667                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78932.291667                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73950.413223                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76050.295858                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74617.481203                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73950.413223                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -643,18 +641,18 @@ system.cpu.l2cache.demand_mshr_misses::total          532
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4545000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4545000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23214000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23214000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6617500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6617500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11162500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     34376500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23214000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11162500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     34376500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4540000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4540000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23536000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23536000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6388500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6388500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23536000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10928500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     34464500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23536000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10928500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     34464500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for ReadCleanReq accesses
@@ -667,25 +665,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.998124
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998124                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63950.413223                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63950.413223                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          533                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           460                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
@@ -698,6 +696,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              34112                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          533                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.001876                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.043315                       # Request fanout histogram
@@ -712,10 +711,10 @@ system.cpu.toL2Bus.snoop_fanout::total            533                       # Re
 system.cpu.toL2Bus.reqLayer0.occupancy         266500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        546000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED     37494000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     37822000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                459                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
@@ -725,6 +724,7 @@ system.membus.pkt_count::total                   1064                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34048                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   34048                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               532                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -735,9 +735,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 532                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              602500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              608000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2826750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2826500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index a3681b4ff..81c1646b5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -565,12 +595,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -589,8 +624,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -598,10 +638,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -632,7 +677,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -664,10 +709,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -711,6 +761,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -722,7 +773,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index bd3dd6b17..b4b146baf 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:57:45
-gem5 executing on phenom, pid 28188
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:27
+gem5 executing on e108600-lin, pid 39605
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 21972500 because target called exit()
+Exiting @ tick 22019000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 8d95bb8b7..0781260bf 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000022                       # Nu
 sim_ticks                                    22019000                       # Number of ticks simulated
 final_tick                                   22019000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 117755                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117735                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              405950936                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294524                       # Number of bytes of host memory used
+host_inst_rate                                 122018                       # Simulator instruction rate (inst/s)
+host_op_rate                                   121990                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              420608458                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250288                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        6385                       # Number of instructions simulated
 sim_ops                                          6385                       # Number of ops (including micro ops) simulated
@@ -948,6 +948,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11072                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              31104                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          486                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.002058                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.045361                       # Request fanout histogram
@@ -975,6 +976,7 @@ system.membus.pkt_count::total                    970                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   31040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               485                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 5f2701c66..c1171633d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index e982daec6..a049bb5ed 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:56:00
-gem5 executing on phenom, pid 28087
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:27
+gem5 executing on e108600-lin, pid 39609
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 281db070e..724287a51 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3214500                       # Number of ticks simulated
 final_tick                                    3214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 879431                       # Simulator instruction rate (inst/s)
-host_op_rate                                   878309                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              440397606                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282472                       # Number of bytes of host memory used
+host_inst_rate                                1026789                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1024872                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              513643962                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238508                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        25652
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port        15500                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   41152                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              8463                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.757769                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.428459                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 68b35910c..d2de1569b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -203,8 +238,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -212,10 +252,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -246,7 +291,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -278,10 +323,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -296,11 +346,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index 9c12b76cc..7b601dbe7 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:56:12
-gem5 executing on phenom, pid 28101
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:28
+gem5 executing on e108600-lin, pid 39614
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 0b95c7449..d4fc31bad 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000036                       # Nu
 sim_ticks                                    35682500                       # Number of ticks simulated
 final_tick                                   35682500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 516760                       # Simulator instruction rate (inst/s)
-host_op_rate                                   516348                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2875227341                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291440                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 318235                       # Simulator instruction rate (inst/s)
+host_op_rate                                   317806                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1768975757                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248500                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -468,6 +468,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              28608                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          447                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.002237                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.047298                       # Request fanout histogram
@@ -495,6 +496,7 @@ system.membus.pkt_count::total                    892                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               446                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index 654daf7a1..ccd9350bc 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -59,6 +64,7 @@ decodeCycleInput=true
 decodeInputBufferSize=3
 decodeInputWidth=2
 decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -101,12 +107,17 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
 socket_id=0
 switched_out=false
 system=system
+threadPolicy=RoundRobin
 tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -142,12 +153,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -166,8 +182,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -566,12 +587,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -590,8 +616,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -616,12 +647,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -640,8 +676,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -649,10 +690,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -683,7 +729,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -715,10 +761,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -762,6 +813,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -773,7 +825,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
index c6957696d..b68e0fd83 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
@@ -1,3 +1,4 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
index 9179fdffe..115f46689 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:13
-gem5 executing on zizzer, pid 34033
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:24
+gem5 executing on e108600-lin, pid 39579
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 20075000 because target called exit()
+Exiting @ tick 20329000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index b5156559e..ac371de2b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20320000                       # Number of ticks simulated
-final_tick                                   20320000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20329000                       # Number of ticks simulated
+final_tick                                   20329000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171591                       # Simulator instruction rate (inst/s)
-host_op_rate                                   171481                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1347191282                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293200                       # Number of bytes of host memory used
+host_inst_rate                                 113549                       # Simulator instruction rate (inst/s)
+host_op_rate                                   113428                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              891182571                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248724                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                19840                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   310                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            708661417                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            267716535                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               976377953                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       708661417                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          708661417                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           708661417                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           267716535                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              976377953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            708347681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            267598013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               975945693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       708347681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          708347681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           708347681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           267598013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              975945693                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           310                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         310                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -49,11 +49,11 @@ system.physmem.perBankRdBursts::3                  24                       # Pe
 system.physmem.perBankRdBursts::4                  21                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  27                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  47                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  48                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  68                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 15                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 16                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 15                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 18                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 52                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 15                       # Per bank write bursts
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20232000                       # Total gap between requests
+system.physmem.totGap                        20241500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       246                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -189,71 +189,71 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      429.268293                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     282.076610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.225077                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     281.421645                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.320856                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             10     24.39%     24.39% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255            6     14.63%     39.02% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383            4      9.76%     48.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      4.88%     53.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            7     17.07%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      7.32%     78.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      7.32%     85.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      7.32%     56.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6     14.63%     70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      4.88%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      9.76%     85.37% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023            3      7.32%     92.68% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            3      7.32%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
-system.physmem.totQLat                        1648500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7461000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1774250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7586750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5317.74                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5723.39                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24067.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         976.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24473.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         975.95                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      976.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      975.95                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.63                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.63                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.62                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.62                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        259                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        260                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.55                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.87                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        65264.52                       # Average gap between requests
-system.physmem.pageHitRate                      83.55                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        65295.16                       # Average gap between requests
+system.physmem.pageHitRate                      83.87                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    780000                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                    787800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10605420                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 196500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12727575                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              803.889152                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         681250                       # Time in different power states
+system.physmem_0.actBackEnergy               10557540                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 238500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12729495                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              804.010422                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         825750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15041250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        14971750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1193400                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   1185600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10488285                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy               10490850                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy                 299250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13290180                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              839.423970                       # Core power per rank (mW)
+system.physmem_1.totalEnergy                 13284945                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              838.894625                       # Core power per rank (mW)
 system.physmem_1.memoryStateTime::IDLE         457000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14869250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14872250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                     794                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               395                       # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted               394                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               170                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups                  562                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                      54                       # Number of BTB hits
@@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          510                       # DTB read hits
-system.cpu.dtb.read_misses                          8                       # DTB read misses
-system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      518                       # DTB read accesses
+system.cpu.dtb.read_hits                          506                       # DTB read hits
+system.cpu.dtb.read_misses                          6                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      512                       # DTB read accesses
 system.cpu.dtb.write_hits                         307                       # DTB write hits
 system.cpu.dtb.write_misses                         6                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     313                       # DTB write accesses
-system.cpu.dtb.data_hits                          817                       # DTB hits
-system.cpu.dtb.data_misses                         14                       # DTB misses
-system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                      831                       # DTB accesses
-system.cpu.itb.fetch_hits                         975                       # ITB hits
+system.cpu.dtb.data_hits                          813                       # DTB hits
+system.cpu.dtb.data_misses                         12                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      825                       # DTB accesses
+system.cpu.itb.fetch_hits                         979                       # ITB hits
 system.cpu.itb.fetch_misses                        13                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     988                       # ITB accesses
+system.cpu.itb.fetch_accesses                     992                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,16 +299,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        20320000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            40640                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        20329000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            40658                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2585                       # Number of instructions committed
 system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                           603                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                           573                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              15.721470                       # CPI: cycles per instruction
-system.cpu.ipc                               0.063607                       # IPC: instructions per cycle
+system.cpu.cpi                              15.728433                       # CPI: cycles per instruction
+system.cpu.ipc                               0.063579                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                 189      7.31%      7.31% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    1678     64.91%     72.22% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      1      0.04%     72.26% # Class of committed instruction
@@ -344,87 +344,87 @@ system.cpu.op_class_0::MemWrite                   298     11.53%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     2585                       # Class of committed instruction
-system.cpu.tickCycles                            5416                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           35224                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                            5421                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           35237                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.513757                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 693                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            48.302993                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.152941                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    48.513757                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011844                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011844                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    48.302993                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011793                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011793                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1679                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1679                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data          442                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             442                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1673                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1673                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data          441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          251                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           693                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              693                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          693                       # number of overall hits
-system.cpu.dcache.overall_hits::total             693                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data           692                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              692                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          692                       # number of overall hits
+system.cpu.dcache.overall_hits::total             692                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           59                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            59                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          104                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          104                       # number of overall misses
-system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4723500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4723500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      3258500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3258500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7982000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7982000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7982000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7982000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          503                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          503                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          102                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            102                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          102                       # number of overall misses
+system.cpu.dcache.overall_misses::total           102                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4783500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4783500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3258000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3258000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      8041500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      8041500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      8041500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      8041500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          500                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          500                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          797                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          797                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          797                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          797                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.121272                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.121272                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          794                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          794                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          794                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          794                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.118000                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.118000                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.146259                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.130489                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.130489                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.130489                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.130489                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77434.426230                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77434.426230                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        76750                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        76750                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        76750                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        76750                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.128463                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.128463                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.128463                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.128463                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 78838.235294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 78838.235294                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           16                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           17                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           17                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           17                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           58                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
@@ -433,83 +433,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4442500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4442500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4654000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4654000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2017500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2017500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6460000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6460000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6460000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6460000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.115308                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115308                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6671500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6671500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6671500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6671500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.116000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116000                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.106650                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.106650                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.106650                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.106650                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76594.827586                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76594.827586                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.107053                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.107053                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.107053                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.107053                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        76000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        76000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        76000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        76000                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           119.123012                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 750                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           119.197826                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 754                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               225                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.333333                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.351111                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   119.123012                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.058166                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.058166                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   119.197826                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.058202                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.058202                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          225                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.109863                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2175                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2175                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst          750                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             750                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           750                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              750                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          750                       # number of overall hits
-system.cpu.icache.overall_hits::total             750                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              2183                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2183                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst          754                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             754                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           754                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              754                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          754                       # number of overall hits
+system.cpu.icache.overall_hits::total             754                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          225                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           225                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            225                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.icache.overall_misses::total           225                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17203000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17203000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17203000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17203000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17203000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17203000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          975                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          975                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          975                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          975                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          975                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          975                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.230769                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.230769                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.230769                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.230769                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.230769                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.230769                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76457.777778                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76457.777778                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76457.777778                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76457.777778                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76457.777778                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76457.777778                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     17116000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     17116000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     17116000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     17116000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     17116000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     17116000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          979                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          979                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          979                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          979                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          979                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          979                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229826                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.229826                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.229826                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.229826                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.229826                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.229826                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76071.111111                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76071.111111                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -522,43 +522,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          225
 system.cpu.icache.demand_mshr_misses::total          225                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          225                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16978000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16978000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16978000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16978000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16978000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16978000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.230769                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.230769                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.230769                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.230769                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.230769                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.230769                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75457.777778                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75457.777778                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16891000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16891000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16891000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16891000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16891000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16891000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.229826                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.229826                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.229826                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          147.162900                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          147.090026                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              283                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   119.239277                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    27.923624                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003639                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000852                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004491                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   119.314039                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    27.775987                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003641                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000848                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004489                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          283                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008636                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2790                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2790                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          225                       # number of ReadCleanReq misses
@@ -573,16 +573,16 @@ system.cpu.l2cache.overall_misses::cpu.data           85                       #
 system.cpu.l2cache.overall_misses::total          310                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1977000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      1977000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16640500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     16640500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4354500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4354500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16640500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6331500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     22972000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16640500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6331500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     22972000                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16553500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     16553500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4566000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4566000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16553500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6543000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23096500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16553500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6543000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23096500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          225                       # number of ReadCleanReq accesses(hits+misses)
@@ -609,16 +609,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73957.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73957.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75077.586207                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75077.586207                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73957.777778                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74488.235294                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74103.225806                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73957.777778                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74488.235294                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74103.225806                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -639,16 +639,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data           85
 system.cpu.l2cache.overall_mshr_misses::total          310                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1707000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1707000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14390500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14390500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3774500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3774500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14390500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5481500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     19872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14390500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5481500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     19872000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14303500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14303500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3986000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3986000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14303500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5693000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19996500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14303500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5693000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19996500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
@@ -663,23 +663,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63957.777778                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63957.777778                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65077.586207                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65077.586207                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63957.777778                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64488.235294                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          310                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
@@ -692,6 +692,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              19840                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          310                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -709,7 +710,7 @@ system.cpu.toL2Bus.respLayer0.occupancy        337500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED     20320000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                283                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
@@ -719,6 +720,7 @@ system.membus.pkt_count::total                    620                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   19840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               310                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -729,9 +731,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 310                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              363500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              363000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            1649000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            1648250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              8.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 4281491aa..39c72e110 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -565,12 +595,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -589,8 +624,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -598,10 +638,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -632,7 +677,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -664,10 +709,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -711,6 +761,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -722,7 +773,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
index c828ff444..4e7b90c23 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,5 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 0abe9b40e..5515360ee 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:12
-gem5 executing on zizzer, pid 34021
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:24
+gem5 executing on e108600-lin, pid 39577
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 12363500 because target called exit()
+Exiting @ tick 12409500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 006581ce2..51e8f72d6 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12409500                       # Number of ticks simulated
 final_tick                                   12409500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52563                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52553                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              273157641                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293200                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  95060                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95002                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              493600045                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248984                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -941,6 +941,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              17408                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          272                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -968,6 +969,7 @@ system.membus.pkt_count::total                    544                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   17408                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               272                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 164e856da..21de058a2 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 0b3033cd9..05d0e3f61 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index ec449ee9d..4e010ba65 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:01
-gem5 executing on zizzer, pid 33991
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:25
+gem5 executing on e108600-lin, pid 39590
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index fe81a2b88..a36aefa9a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 615280                       # Simulator instruction rate (inst/s)
-host_op_rate                                   613973                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              308554926                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281160                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
+host_inst_rate                                 290379                       # Simulator instruction rate (inst/s)
+host_op_rate                                   289620                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              145475657                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238224                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        10340
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         5074                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   15414                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              3294                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.784760                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.411051                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index ea2d2a5a5..14ec42af5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -203,8 +238,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -212,10 +252,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -246,7 +291,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -278,10 +323,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -296,11 +346,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
index 0b3033cd9..05d0e3f61 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index bad9ca9c2..af6b46ed3 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:15
-gem5 executing on zizzer, pid 34051
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:23
+gem5 executing on e108600-lin, pid 39547
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index a94783b9b..c5f7031d7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18239500                       # Number of ticks simulated
 final_tick                                   18239500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 346390                       # Simulator instruction rate (inst/s)
-host_op_rate                                   345952                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2445638693                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291156                       # Number of bytes of host memory used
+host_inst_rate                                 190443                       # Simulator instruction rate (inst/s)
+host_op_rate                                   190287                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1345802218                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247188                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
@@ -462,6 +462,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5248                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              15680                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          245                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -489,6 +490,7 @@ system.membus.pkt_count::total                    490                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        15680                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   15680                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               245                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index 0858c144d..a47bafcf6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -59,6 +64,7 @@ decodeCycleInput=true
 decodeInputBufferSize=3
 decodeInputWidth=2
 decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -103,12 +109,17 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
 socket_id=0
 switched_out=false
 system=system
+threadPolicy=RoundRobin
 tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -144,12 +155,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -168,8 +184,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -192,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -208,9 +234,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -604,12 +635,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -628,8 +664,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -687,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -703,9 +749,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -716,12 +767,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -740,8 +796,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -749,10 +810,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -783,7 +849,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -815,10 +881,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -862,6 +933,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -873,7 +945,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
index b3cb615d2..21abd8071 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:59
-gem5 executing on zizzer, pid 20780
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:22
+gem5 executing on e108600-lin, pid 23083
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 29949500 because target called exit()
+Exiting @ tick 30083500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index acde8b0d6..ebafeb85e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29977500                       # Number of ticks simulated
-final_tick                                   29977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    30083500                       # Number of ticks simulated
+final_tick                                   30083500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147440                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172555                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              959274014                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309288                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  80042                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93682                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              522670316                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264608                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           19520                       # Nu
 system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            651155033                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            247652406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               898807439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       651155033                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          651155033                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           651155033                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           247652406                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              898807439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            648860671                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            246779796                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               895640467                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       648860671                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          648860671                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           648860671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           246779796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              895640467                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        29886000                       # Total gap between requests
+system.physmem.totGap                        29992500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        66                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       344                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -189,84 +189,84 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      408.774194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     287.393665                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     328.869570                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     287.809352                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.256468                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127              8     12.90%     12.90% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255           17     27.42%     40.32% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           12     19.35%     59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      8.06%     67.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      6.45%     74.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6      9.68%     69.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.84%     74.19% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::640-767            3      4.84%     79.03% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895            3      4.84%     83.87% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023            1      1.61%     85.48% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        2113500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10007250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        2221000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10114750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5020.19                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5275.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23770.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         898.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24025.53                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         895.64                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      898.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      895.64                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.00                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        350                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70988.12                       # Average gap between requests
+system.physmem.avgGap                        71241.09                       # Average gap between requests
 system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1973400                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                   1965600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16099650                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy               16103925                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  48750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20068140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              849.669860                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          12500                       # Time in different power states
+system.physmem_0.totalEnergy                 20064615                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              849.295873                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          12000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22840000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        22845750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    694200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15745680                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 359250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 18523455                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              784.269066                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1654750                       # Time in different power states
+system.physmem_1.actBackEnergy               15554160                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 527250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 18499935                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              783.273247                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        2015750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        22324250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22043250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    1949                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1165                       # Number of conditional branches predicted
+system.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    1968                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1178                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               351                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1641                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     316                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1660                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     322                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             19.256551                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     222                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             19.397590                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     220                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             133                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups             135                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                  8                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              125                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses              127                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted           62                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,16 +387,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        29977500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            59955                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        30083500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            60167                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4605                       # Number of instructions committed
 system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1202                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1193                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              13.019544                       # CPI: cycles per instruction
-system.cpu.ipc                               0.076808                       # IPC: instructions per cycle
+system.cpu.cpi                              13.065581                       # CPI: cycles per instruction
+system.cpu.ipc                               0.076537                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    3419     63.42%     63.42% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      4      0.07%     63.49% # Class of committed instruction
@@ -432,95 +432,95 @@ system.cpu.op_class_0::MemWrite                   938     17.40%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     5391                       # Class of committed instruction
-system.cpu.tickCycles                           10654                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           49301                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                           10719                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           49448                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.495507                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1916                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            86.478936                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.123288                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.136986                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.495507                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021117                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021117                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.478936                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021113                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021113                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4342                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4342                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4334                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4334                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1050                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1050                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1894                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1894                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1894                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1894                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          1896                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1896                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1896                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          109                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           109                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           67                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          182                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
-system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6977500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6977500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5011500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5011500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     11989000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11989000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     11989000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11989000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          176                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            176                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          176                       # number of overall misses
+system.cpu.dcache.overall_misses::total           176                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6690500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6690500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5002500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5002500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     11693000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11693000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     11693000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11693000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1159                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1159                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2076                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2076                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2076                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2076                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098882                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098882                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2072                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2072                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2072                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2072                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.094047                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.094047                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.073384                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.087669                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.087669                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.087669                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087669                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65873.626374                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65873.626374                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.084942                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.084942                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.084942                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.084942                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66437.500000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66437.500000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           24                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           36                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           36                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           30                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           30                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           30                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
@@ -529,83 +529,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6370500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6370500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3194000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3194000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9564500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9564500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9564500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9564500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088564                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088564                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6338000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6338000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3188000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3188000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9526000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9526000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9526000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9526000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088870                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088870                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070328                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.070328                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070328                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.070328                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070463                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.070463                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070463                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.070463                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           162.122030                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1926                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               323                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.962848                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           161.834516                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1963                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.096273                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   162.122030                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.079161                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.079161                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.834516                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079021                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079021                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          318                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4821                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4821                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1926                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1926                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1926                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1926                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1926                       # number of overall hits
-system.cpu.icache.overall_hits::total            1926                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          323                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           323                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          323                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            323                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          323                       # number of overall misses
-system.cpu.icache.overall_misses::total           323                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23530000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23530000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23530000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23530000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23530000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23530000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2249                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2249                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2249                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2249                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2249                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2249                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143619                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.143619                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.143619                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.143619                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.143619                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.143619                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72848.297214                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72848.297214                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.155273                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4892                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4892                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1963                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total           322                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     23678000                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst     23678000                       # number of overall miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst         2285                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2285                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total         2285                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2285                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2285                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.140919                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.140919                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.140919                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.140919                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.140919                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.140919                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73534.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73534.161491                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -614,61 +614,61 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks            4                       # number of writebacks
 system.cpu.icache.writebacks::total                 4                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          323                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          323                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          323                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          323                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          323                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          323                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23207000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23207000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23207000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23207000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23207000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23207000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143619                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.143619                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.143619                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          322                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_miss_latency::total     23356000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.140919                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.140919                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          195.781809                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 43                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          195.879475                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 42                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.113757                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.111111                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.633330                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    41.148479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004719                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001256                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005975                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_blocks::cpu.data    41.132665                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004722                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4197                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4197                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.tag_accesses             4189                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4189                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           18                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           18                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           17                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           17                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           22                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           22                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           18                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              40                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           18                       # number of overall hits
+system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             40                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          305                       # number of ReadCleanReq misses
@@ -681,56 +681,56 @@ system.cpu.l2cache.demand_misses::total           429                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          124                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3129500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3129500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22515500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     22515500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5956000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5956000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22515500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9085500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31601000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22515500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9085500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31601000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3123500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3123500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22677500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22677500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5924000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5924000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22677500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9047500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31725000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22677500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9047500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31725000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          323                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          323                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          322                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          322                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          103                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          103                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          323                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          322                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          469                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          323                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          468                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          322                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          469                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          468                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.944272                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.944272                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.947205                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.947205                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.786408                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.786408                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.944272                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.947205                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.849315                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.914712                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.944272                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.916667                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947205                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.914712                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,80 +755,81 @@ system.cpu.l2cache.demand_mshr_misses::total          421
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          116                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2699500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2699500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19465500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19465500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4696000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4696000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19465500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7395500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26861000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19465500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7395500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26861000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2693500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2693500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19627500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19627500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4648000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4648000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19627500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7341500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26969000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19627500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7341500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26969000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.944272                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.947205                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.708738                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.708738                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.897655                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.899573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.897655                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          473                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests           51                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests          472                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests           50                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           426                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          103                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          650                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          648                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               942                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               940                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20864                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30208                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          469                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.102345                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.303426                       # Request fanout histogram
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples          468                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.100427                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.300891                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                421     89.77%     89.77% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                 48     10.23%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                421     89.96%     89.96% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                 47     10.04%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            469                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         240500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            468                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         240000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        484500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        483000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        222992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     30083500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                378                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
@@ -838,6 +839,7 @@ system.membus.pkt_count::total                    842                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26944                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   26944                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               421                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -848,9 +850,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 421                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              489000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              490000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2236750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2237750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              7.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index db680b227..78e5f6bf3 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -110,6 +116,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -168,6 +178,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -186,6 +197,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -216,9 +231,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
 [system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.dtb]
@@ -232,9 +252,14 @@ walker=system.cpu.checker.dtb.walker
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[5]
 
@@ -288,9 +313,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
 [system.cpu.checker.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.itb]
@@ -304,9 +334,14 @@ walker=system.cpu.checker.itb.walker
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[4]
 
@@ -321,12 +356,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -345,8 +385,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -369,9 +414,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -385,9 +435,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -705,12 +760,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -729,8 +789,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -788,9 +853,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -804,9 +874,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -817,12 +892,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -841,8 +921,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -850,10 +935,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -884,7 +974,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -916,10 +1006,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -963,6 +1058,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -974,7 +1070,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
index 341b479f7..57447a9b7 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
@@ -1,2 +1,4 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 97296d3da..8c38643eb 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:35:59
-gem5 started Mar 13 2016 22:47:14
-gem5 executing on phenom, pid 19877
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:41:21
+gem5 executing on e108600-lin, pid 23122
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index e232e499c..f9ef4c918 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17232500                       # Number of ticks simulated
 final_tick                                   17232500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  78702                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92158                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              295258113                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310332                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  43349                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50759                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              162616088                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265888                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1198,6 +1198,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              28352                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.099773                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.300038                       # Request fanout histogram
@@ -1225,6 +1226,7 @@ system.membus.pkt_count::total                    794                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25408                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   25408                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               397                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 4403ba687..fc0ffed98 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=2
 decodeWidth=3
+default_p_state=UNDEFINED
 dispatchWidth=6
 do_checkpoint_insts=true
 do_quiesce=true
@@ -110,6 +116,10 @@ numPhysIntRegs=128
 numROBEntries=40
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -190,8 +205,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=1
 is_read_only=true
 max_miss_count=0
 mshrs=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=1
@@ -532,8 +567,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -607,9 +652,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=12
 is_read_only=false
 max_miss_count=0
 mshrs=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=true
 prefetcher=system.cpu.l2cache.prefetcher
 response_latency=12
@@ -643,6 +698,7 @@ mem_side=system.membus.slave[1]
 type=StridePrefetcher
 cache_snoop=false
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 degree=8
 eventq_index=0
 latency=1
@@ -653,6 +709,10 @@ on_inst=true
 on_miss=false
 on_read=true
 on_write=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 queue_filter=true
 queue_size=32
 queue_squash=true
@@ -669,8 +729,13 @@ type=RandomRepl
 assoc=16
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=12
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=1048576
 
@@ -678,10 +743,15 @@ size=1048576
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -712,7 +782,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -744,10 +814,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -791,6 +866,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -802,7 +878,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index e4ae04024..10d18de27 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:35:59
-gem5 started Mar 13 2016 22:47:14
-gem5 executing on phenom, pid 19874
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:07:36
+gem5 executing on e108600-lin, pid 24410
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index e81d385ba..1e33086fd 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18821000                       # Number of ticks simulated
 final_tick                                   18821000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84019                       # Simulator instruction rate (inst/s)
-host_op_rate                                    98384                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              344256847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306884                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  60061                       # Simulator instruction rate (inst/s)
+host_op_rate                                    70319                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              246027411                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262688                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1107,6 +1107,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9216                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              31168                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                         454                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          897                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.549610                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.582523                       # Request fanout histogram
@@ -1134,6 +1135,7 @@ system.membus.pkt_count::total                    885                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28288                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   28288                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               443                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 60fb7fd34..be532b0c0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=system.cpu.checker
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -93,6 +103,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -111,6 +122,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -141,9 +156,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
 [system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.dtb]
@@ -157,9 +177,14 @@ walker=system.cpu.checker.dtb.walker
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.isa]
@@ -212,9 +237,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
 [system.cpu.checker.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.itb]
@@ -228,9 +258,14 @@ walker=system.cpu.checker.itb.walker
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.checker.tracer]
@@ -256,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -272,9 +312,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[4]
 
@@ -332,9 +377,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -348,9 +398,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[3]
 
@@ -368,7 +423,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -400,10 +455,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -418,11 +478,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
index 1a4f96712..2b0e974b5 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
@@ -1 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index dca8243ae..a4f08df89 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:47:11
-gem5 executing on zizzer, pid 20787
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:49:47
+gem5 executing on e108600-lin, pid 23301
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index c4cb1f552..55d542711 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 569364                       # Simulator instruction rate (inst/s)
-host_op_rate                                   666035                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              333433301                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299296                       # Number of bytes of host memory used
+host_inst_rate                                 427598                       # Simulator instruction rate (inst/s)
+host_op_rate                                   499586                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              249859240                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254616                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
@@ -359,6 +359,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18420
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   26559                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              6532                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.704991                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.456082                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index 40d4f88c7..8f8064fa0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[4]
 
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[3]
 
@@ -218,7 +248,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -250,10 +280,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 98eb95060..813c1fdca 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:25
-gem5 executing on zizzer, pid 20745
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:23
+gem5 executing on e108600-lin, pid 23087
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index a84dba320..43260b12f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 625339                       # Simulator instruction rate (inst/s)
-host_op_rate                                   731490                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              366164896                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298280                       # Number of bytes of host memory used
+host_inst_rate                                 433184                       # Simulator instruction rate (inst/s)
+host_op_rate                                   506134                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              253162440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254364                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
@@ -235,6 +235,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18420
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   26559                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              6532                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.704991                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.456082                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 3fd071b25..b1081da03 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -114,8 +129,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +226,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -303,8 +358,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -312,10 +372,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -346,7 +411,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -378,10 +443,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index daa769407..4f7f76cdc 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:20
-gem5 executing on zizzer, pid 20726
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:23
+gem5 executing on e108600-lin, pid 23085
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 92414aab2..40170ff2c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 377704                       # Simulator instruction rate (inst/s)
-host_op_rate                                   440559                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2337429945                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308268                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 246555                       # Simulator instruction rate (inst/s)
+host_op_rate                                   287459                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1524533550                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264352                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -573,6 +573,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              24512                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          382                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.083770                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.277405                       # Request fanout histogram
@@ -600,6 +601,7 @@ system.membus.pkt_count::total                    700                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        22400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   22400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               350                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 900efeb02..fb58e2bf8 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -567,12 +597,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -591,8 +626,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -600,10 +640,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -634,7 +679,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -666,10 +711,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -713,6 +763,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -724,7 +775,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index fea443199..8c26880d3 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29859
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled Jul 21 2016 14:23:13
+gem5 started Jul 21 2016 14:23:47
+gem5 executing on e108600-lin, pid 13281
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 22454000 because target called exit()
+Exiting @ tick 22532000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 1d63b6535..ba0daa415 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000023                       # Nu
 sim_ticks                                    22532000                       # Number of ticks simulated
 final_tick                                   22532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107418                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107396                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              483974405                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292720                       # Number of bytes of host memory used
+host_inst_rate                                  94024                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93989                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              423490323                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248172                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4999                       # Number of instructions simulated
 sim_ops                                          4999                       # Number of ops (including micro ops) simulated
@@ -939,6 +939,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8960                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              31296                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          472                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -966,6 +967,7 @@ system.membus.pkt_count::total                    938                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   30016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               469                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 45a38b492..9bfe34f71 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -120,7 +130,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -152,10 +162,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -170,11 +185,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 3810aff86..8185b0f75 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-a
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29858
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:23:13
+gem5 started Jul 21 2016 14:23:47
+gem5 executing on e108600-lin, pid 13283
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 873eb6862..619b5f6ac 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2820500                       # Number of ticks simulated
 final_tick                                    2820500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 743339                       # Simulator instruction rate (inst/s)
-host_op_rate                                   742439                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              370817863                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279644                       # Number of bytes of host memory used
+host_inst_rate                                 890532                       # Simulator instruction rate (inst/s)
+host_op_rate                                   888973                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              443763917                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236392                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
@@ -128,6 +128,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        22568
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         7902                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   30470                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              7678                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.734827                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.441454                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 86ced7654..2eeeec54d 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -181,12 +211,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -205,8 +240,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -214,10 +254,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -248,7 +293,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -280,10 +325,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -298,11 +348,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index c38df8b63..9b7b607dc 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29861
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+gem5 compiled Jul 21 2016 14:23:13
+gem5 started Jul 21 2016 14:23:47
+gem5 executing on e108600-lin, pid 13258
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 5a06a8f5e..29abc2b26 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000034                       # Nu
 sim_ticks                                    33932500                       # Number of ticks simulated
 final_tick                                   33932500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 497160                       # Simulator instruction rate (inst/s)
-host_op_rate                                   496749                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2985875640                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289632                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  18620                       # Simulator instruction rate (inst/s)
+host_op_rate                                    18619                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              111991731                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246380                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -461,6 +461,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              28480                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          432                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -488,6 +489,7 @@ system.membus.pkt_count::total                    860                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        27520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   27520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               430                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 0500fc3ab..11c8c38c9 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -73,6 +78,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -109,6 +115,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -168,12 +178,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -192,8 +207,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -516,12 +536,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -540,8 +565,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -565,12 +595,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -589,8 +624,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -598,10 +638,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -632,7 +677,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -664,10 +709,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -711,6 +761,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -722,7 +773,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 4c7495180..bd0101e05 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:44:19
-gem5 started Mar 13 2016 22:49:48
-gem5 executing on phenom, pid 19921
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
+gem5 compiled Jul 21 2016 14:27:08
+gem5 started Jul 21 2016 14:27:33
+gem5 executing on e108600-lin, pid 27995
+command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 19923000 because target called exit()
+Exiting @ tick 19908000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index c26ae805a..a1b1af10d 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19908000                       # Number of ticks simulated
 final_tick                                   19908000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67828                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67820                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              233087583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290888                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  79311                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              272523705                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246096                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -937,6 +937,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         6528                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              28864                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          454                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.017621                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.131715                       # Request fanout histogram
@@ -964,6 +965,7 @@ system.membus.pkt_count::total                    888                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28352                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   28352                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               445                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index ae31c4fe2..b654cdd15 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -56,6 +61,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 0c347fd1b..cbf63eeba 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:25:19
-gem5 started Jan 21 2016 14:25:54
-gem5 executing on zizzer, pid 3347
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:27:08
+gem5 started Jul 21 2016 14:27:33
+gem5 executing on e108600-lin, pid 28000
+command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 7771c9798..c2dda4058 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2896000                       # Number of ticks simulated
 final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 806520                       # Simulator instruction rate (inst/s)
-host_op_rate                                   805428                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              402167874                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277804                       # Number of bytes of host memory used
+host_inst_rate                                 667625                       # Simulator instruction rate (inst/s)
+host_op_rate                                   666766                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              332924076                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235336                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5793                       # Number of instructions simulated
 sim_ops                                          5793                       # Number of ops (including micro ops) simulated
@@ -128,6 +128,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        23172
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         7929                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   31101                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              7800                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.742692                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.437178                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index bf044682b..c79232133 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -117,7 +127,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -149,10 +159,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 4be93416d..0783a6d90 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:25
-gem5 executing on zizzer, pid 8711
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38676
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 5963e613d..c6c8dc595 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 770174                       # Simulator instruction rate (inst/s)
-host_op_rate                                   769174                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              388618840                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281084                       # Number of bytes of host memory used
+host_inst_rate                                 588885                       # Simulator instruction rate (inst/s)
+host_op_rate                                   587162                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              296343205                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237088                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
@@ -110,6 +110,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        21480
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         9667                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   31147                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              6758                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.794614                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.404013                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 75416425d..467bc0996 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -178,12 +208,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -202,8 +237,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -211,10 +251,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -245,7 +290,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -277,10 +322,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -295,11 +345,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 0694c2e26..a65457027 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:24
-gem5 executing on zizzer, pid 8705
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38670
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 77136ce08..61bfb723b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30526500                       # Number of ticks simulated
 final_tick                                   30526500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 412582                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412293                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2361216779                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290052                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 232577                       # Simulator instruction rate (inst/s)
+host_op_rate                                   232336                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1330299281                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247080                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -440,6 +440,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              25088                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          392                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.007653                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.087258                       # Request fanout histogram
@@ -467,6 +468,7 @@ system.membus.pkt_count::total                    778                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        24896                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   24896                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               389                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 81a7b3677..8fda1a50c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -173,12 +183,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -197,8 +212,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -212,8 +232,13 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -531,12 +556,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -555,18 +585,28 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[2]
 int_slave=system.membus.master[2]
@@ -586,8 +626,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -598,12 +643,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -622,8 +672,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -631,10 +686,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -665,7 +725,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -697,10 +757,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -744,6 +809,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -755,7 +821,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 2ebb8dfe8..8cf3e8140 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:47:14
-gem5 started Mar 13 2016 22:50:36
-gem5 executing on phenom, pid 19928
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:18
+gem5 executing on e108600-lin, pid 18560
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 20818000 because target called exit()
+Exiting @ tick 21273500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 5bbab77d0..07049f339 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21273500                       # Number of ticks simulated
 final_tick                                   21273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60676                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109916                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              239878032                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 312536                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  32077                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58109                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              126812951                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266996                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -918,6 +918,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              26688                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          417                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.002398                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.048970                       # Request fanout histogram
@@ -947,6 +948,7 @@ system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        2
 system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               416                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 4a2074e15..62043a3c5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -101,18 +111,28 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[5]
 int_slave=system.membus.master[2]
@@ -132,8 +152,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[3]
 
@@ -151,7 +176,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -183,10 +208,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -201,11 +231,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 87f2a402c..bd2d6df6a 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:54
-gem5 executing on zizzer, pid 17917
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:19
+gem5 executing on e108600-lin, pid 18561
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index da4043b17..563e9e0f5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5615000                       # Number of ticks simulated
 final_tick                                    5615000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 383826                       # Simulator instruction rate (inst/s)
-host_op_rate                                   694898                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              400042776                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299464                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 290053                       # Simulator instruction rate (inst/s)
+host_op_rate                                   524918                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              302085986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255208                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -120,6 +120,7 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port        14178
 system.membus.pkt_size_system.cpu.dcache_port::total        14178                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   69090                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              8852                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.775418                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.417330                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index ca3cb5481..bc04df7fd 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -118,8 +133,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -133,8 +153,13 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -145,12 +170,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -169,18 +199,28 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[2]
 int_slave=system.membus.master[2]
@@ -200,8 +240,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -212,12 +257,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -236,8 +286,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -245,10 +300,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -279,7 +339,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -311,10 +371,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -329,11 +394,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index b229084a6..17523a325 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:52
-gem5 executing on zizzer, pid 17886
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:20
+gem5 executing on e108600-lin, pid 18567
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index be586bcab..9047321d1 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30886500                       # Number of ticks simulated
 final_tick                                   30886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 223066                       # Simulator instruction rate (inst/s)
-host_op_rate                                   403939                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1279464733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309460                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 211795                       # Simulator instruction rate (inst/s)
+host_op_rate                                   383429                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1214135841                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263924                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -442,6 +442,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8576                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              23168                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          362                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.002762                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.052559                       # Request fanout histogram
@@ -471,6 +472,7 @@ system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        2
 system.membus.pkt_size_system.cpu.l2cache.mem_side::total        23104                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   23104                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               361                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
index 99297fbad..83c5a15fe 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=true
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -574,12 +604,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -598,8 +633,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -607,10 +647,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -641,7 +686,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -664,7 +709,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -696,10 +741,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -743,6 +793,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -754,7 +805,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
index 341b479f7..b4f78c475 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
@@ -1,2 +1,4 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: Already in the requested power state, request ignored
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
index a1fd37503..b07f24804 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:58:29
-gem5 executing on phenom, pid 28223
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:26
+gem5 executing on e108600-lin, pid 39592
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 24794500 because target called exit()
+Exiting @ tick 25580500 because target called exit()
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index 6380191ed..561952189 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25580500                       # Number of ticks simulated
 final_tick                                   25580500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131467                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131454                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              263302304                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296128                       # Number of bytes of host memory used
+host_inst_rate                                 123264                       # Simulator instruction rate (inst/s)
+host_op_rate                                   123250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              246864911                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250880                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                       12770                       # Number of instructions simulated
 sim_ops                                         12770                       # Number of ops (including micro ops) simulated
@@ -1102,6 +1102,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        21824                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              62144                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          965                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.002073                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.045502                       # Request fanout histogram
@@ -1129,6 +1130,7 @@ system.membus.pkt_count::total                   1923                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        61504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   61504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               962                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index d8bc200f7..50d6b0572 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -564,12 +594,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -588,8 +623,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -597,10 +637,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -631,7 +676,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 kvmInSE=false
@@ -663,10 +708,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -710,6 +760,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -721,7 +772,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
index 341b479f7..bbcd9d751 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index b244d8ce1..a008eb955 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:35:56
-gem5 started Mar 13 2016 22:47:13
-gem5 executing on phenom, pid 19871
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38673
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -19,4 +21,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 26944000 because target called exit()
+Exiting @ tick 28845500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 4d702e129..a74466584 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28845500                       # Number of ticks simulated
 final_tick                                   28845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97927                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97921                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              195651101                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293060                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  66025                       # Simulator instruction rate (inst/s)
+host_op_rate                                    66018                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              131902943                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248796                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -913,6 +913,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              32704                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          513                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.003899                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.062378                       # Request fanout histogram
@@ -940,6 +941,7 @@ system.membus.pkt_count::total                   1020                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        32576                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   32576                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               511                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 4869afcc8..28ad26872 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -117,7 +127,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 kvmInSE=false
@@ -149,10 +159,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index 4cc5ce56f..da1b76716 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:26
-gem5 executing on zizzer, pid 8728
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38677
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index f85a288f2..f98d4e626 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000008                       # Nu
 sim_ticks                                     7612000                       # Number of ticks simulated
 final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 696198                       # Simulator instruction rate (inst/s)
-host_op_rate                                   695914                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              349255842                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279976                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 348414                       # Simulator instruction rate (inst/s)
+host_op_rate                                   348210                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              174731638                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237012                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -114,6 +114,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        60828
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port        20442                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   81270                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples             18880                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.805456                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.395860                       # Request fanout histogram
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 0632f29e9..76eaa1c9f 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -178,12 +208,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -202,8 +237,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -211,10 +251,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -245,7 +290,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 kvmInSE=false
@@ -277,10 +322,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -295,11 +345,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index e9bf8b42d..aa11b3776 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:27
-gem5 executing on zizzer, pid 8737
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:38
+gem5 executing on e108600-lin, pid 38722
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 718aa1232..28b8d6695 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000044                       # Nu
 sim_ticks                                    44282500                       # Number of ticks simulated
 final_tick                                   44282500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 533053                       # Simulator instruction rate (inst/s)
-host_op_rate                                   532883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1555927955                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289976                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 322672                       # Simulator instruction rate (inst/s)
+host_op_rate                                   322568                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              941828647                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247000                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -440,6 +440,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total              26752                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples          418                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.004785                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.069088                       # Request fanout histogram
@@ -467,6 +468,7 @@ system.membus.pkt_count::total                    832                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               416                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
index bc179e2e1..407eb5e1e 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -175,6 +185,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -186,7 +197,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -221,10 +236,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
index fa59b7ebb..7b44dd5a2 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:58:08
-gem5 executing on phenom, pid 28209
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:26
+gem5 executing on e108600-lin, pid 39594
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
index 540013051..9f33ca572 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000405                       # Nu
 sim_ticks                                   405365000                       # Number of ticks simulated
 final_tick                                  405365000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 281711                       # Simulator instruction rate (inst/s)
-host_op_rate                                   281601                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17683002929                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675684                       # Number of bytes of host memory used
+host_inst_rate                                 357720                       # Simulator instruction rate (inst/s)
+host_op_rate                                   357500                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22445039511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631720                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
@@ -377,6 +377,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        25852
 system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port        15540                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   41392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              8519                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.758775                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.427852                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
index d03b53466..f8108d4cd 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -118,8 +133,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -135,12 +155,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -159,8 +184,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=16384
 
@@ -217,10 +247,15 @@ transition_latency=100000000
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.l2bus.snoop_filter
 snoop_response_latency=1
@@ -244,12 +279,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -268,8 +308,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -307,6 +352,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -318,7 +364,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -353,10 +403,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
index 33f584256..7505aca67 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:56:34
-gem5 executing on phenom, pid 28126
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 19 2016 12:24:26
+gem5 executing on e108600-lin, pid 39597
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
index 965f59d57..674c577ef 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000061                       # Nu
 sim_ticks                                    61470000                       # Number of ticks simulated
 final_tick                                   61470000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 534192                       # Simulator instruction rate (inst/s)
-host_op_rate                                   533574                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5078648410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 679784                       # Number of bytes of host memory used
+host_inst_rate                                 601148                       # Simulator instruction rate (inst/s)
+host_op_rate                                   600523                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5715150644                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 635816                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
@@ -548,6 +548,7 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    28736                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.snoops                                 0                       # Total snoops (count)
+system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
 system.l2bus.snoop_fanout::samples                449                       # Request fanout histogram
 system.l2bus.snoop_fanout::mean              0.002227                       # Request fanout histogram
 system.l2bus.snoop_fanout::stdev             0.047193                       # Request fanout histogram
@@ -705,6 +706,7 @@ system.membus.pkt_count::total                    892                       # Pa
 system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               446                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
index efaf99014..6eea99b33 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -78,6 +84,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -108,9 +118,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -124,9 +139,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.interrupts]
@@ -183,9 +203,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -199,9 +224,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.tracer]
@@ -273,6 +303,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -284,7 +315,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -319,10 +354,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
index 48bc9cc41..eb0348157 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:47:24
-gem5 executing on zizzer, pid 20809
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:05:26
+gem5 executing on e108600-lin, pid 24207
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
index 1d743770e..b0e38a814 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000326                       # Nu
 sim_ticks                                   325849000                       # Number of ticks simulated
 final_tick                                  325849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 301831                       # Simulator instruction rate (inst/s)
-host_op_rate                                   348968                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            19697741357                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 691496                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 174378                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201529                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            11371603109                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647324                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -468,6 +468,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        20108
 system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port         8368                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   28476                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              7025                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.715730                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.451098                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
index c95223039..ad9e5a13b 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -78,6 +84,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -96,12 +106,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -120,8 +135,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -144,9 +164,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -160,9 +185,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.icache]
@@ -172,12 +202,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -196,8 +231,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=16384
 
@@ -255,9 +295,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -271,9 +316,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.tracer]
@@ -315,10 +365,15 @@ transition_latency=100000000
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.l2bus.snoop_filter
 snoop_response_latency=1
@@ -342,12 +397,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -366,8 +426,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -405,6 +470,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -416,7 +482,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -451,10 +521,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
index 27e9cb793..a3411dc5e 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:47:23
-gem5 executing on zizzer, pid 20801
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:03:01
+gem5 executing on e108600-lin, pid 24156
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index bff9edae7..b14eb2f25 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 407452                       # Simulator instruction rate (inst/s)
-host_op_rate                                   470980                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4066768251                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 695596                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 256506                       # Simulator instruction rate (inst/s)
+host_op_rate                                   296356                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2557788683                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 651420                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -646,6 +646,7 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    25024                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.snoops                                 0                       # Total snoops (count)
+system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
 system.l2bus.snoop_fanout::samples                391                       # Request fanout histogram
 system.l2bus.snoop_fanout::mean              0.086957                       # Request fanout histogram
 system.l2bus.snoop_fanout::stdev             0.282132                       # Request fanout histogram
@@ -806,6 +807,7 @@ system.membus.pkt_count::total                    702                       # Pa
 system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        22464                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   22464                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               351                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
index 6a950e658..de0268a39 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -188,7 +199,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -223,10 +238,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
index f1e009cf1..194a454d5 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29862
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
+gem5 compiled Jul 21 2016 14:23:13
+gem5 started Jul 21 2016 14:23:48
+gem5 executing on e108600-lin, pid 13288
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
index e9f25f2b3..54ae8e9b7 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000369                       # Nu
 sim_ticks                                   368887000                       # Number of ticks simulated
 final_tick                                  368887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 323597                       # Simulator instruction rate (inst/s)
-host_op_rate                                   323434                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            21140902807                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 672844                       # Number of bytes of host memory used
+host_inst_rate                                 354647                       # Simulator instruction rate (inst/s)
+host_op_rate                                   354403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23159010384                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 629604                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
@@ -362,6 +362,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        22568
 system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port         7902                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   30470                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              7679                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.734861                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.441436                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
index 624933f37..cf4a132b7 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -118,8 +133,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -135,12 +155,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -159,8 +184,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=16384
 
@@ -219,10 +249,15 @@ transition_latency=100000000
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.l2bus.snoop_filter
 snoop_response_latency=1
@@ -246,12 +281,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -270,8 +310,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -309,6 +354,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -320,7 +366,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -355,10 +405,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
index cda55876d..760ae9b2e 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29863
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
+gem5 compiled Jul 21 2016 14:23:13
+gem5 started Jul 21 2016 14:23:48
+gem5 executing on e108600-lin, pid 13287
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
index 41fba603d..c2c263451 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000059                       # Nu
 sim_ticks                                    58892000                       # Number of ticks simulated
 final_tick                                   58892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 486513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   486102                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5071440381                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 676956                       # Number of bytes of host memory used
+host_inst_rate                                 557970                       # Simulator instruction rate (inst/s)
+host_op_rate                                   557350                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5812791438                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 633704                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
@@ -534,6 +534,7 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    27776                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.snoops                                 0                       # Total snoops (count)
+system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
 system.l2bus.snoop_fanout::samples                434                       # Request fanout histogram
 system.l2bus.snoop_fanout::mean                     0                       # Request fanout histogram
 system.l2bus.snoop_fanout::stdev                    0                       # Request fanout histogram
@@ -691,6 +692,7 @@ system.membus.pkt_count::total                    860                       # Pa
 system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        27520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   27520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               430                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
index ad7fd8fe2..a434b8376 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -174,6 +184,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -185,7 +196,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -220,10 +235,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
index 17e9b6a4f..9b1207098 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:25
-gem5 executing on zizzer, pid 8716
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:37
+gem5 executing on e108600-lin, pid 38687
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
index 1263f399d..81f7b029f 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000333                       # Nu
 sim_ticks                                   333033000                       # Number of ticks simulated
 final_tick                                  333033000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 352196                       # Simulator instruction rate (inst/s)
-host_op_rate                                   351993                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            21118670028                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 673252                       # Number of bytes of host memory used
+host_inst_rate                                 341593                       # Simulator instruction rate (inst/s)
+host_op_rate                                   341350                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            20477364302                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 630048                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
@@ -345,6 +345,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        22364
 system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port         9705                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   32069                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              6983                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.800802                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.399426                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
index b339bd7f3..24d190659 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -118,8 +133,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -135,12 +155,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -159,8 +184,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=16384
 
@@ -216,10 +246,15 @@ transition_latency=100000000
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.l2bus.snoop_filter
 snoop_response_latency=1
@@ -243,12 +278,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -267,8 +307,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -306,6 +351,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -317,7 +363,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -352,10 +402,15 @@ port=system.membus.master[0]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
index ad0a8825b..362a2e4dd 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:26
-gem5 executing on zizzer, pid 8726
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38678
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
index 8682445d5..6107833ad 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                    53334000                       # Number of ticks simulated
 final_tick                                   53334000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 483647                       # Simulator instruction rate (inst/s)
-host_op_rate                                   483274                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4642649843                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677372                       # Number of bytes of host memory used
+host_inst_rate                                 532040                       # Simulator instruction rate (inst/s)
+host_op_rate                                   531414                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5103257870                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 634140                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
@@ -521,6 +521,7 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    25408                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.snoops                                 0                       # Total snoops (count)
+system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
 system.l2bus.snoop_fanout::samples                397                       # Request fanout histogram
 system.l2bus.snoop_fanout::mean              0.007557                       # Request fanout histogram
 system.l2bus.snoop_fanout::stdev             0.086709                       # Request fanout histogram
@@ -681,6 +682,7 @@ system.membus.pkt_count::total                    788                       # Pa
 system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        25216                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   25216                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               394                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
index 8ec6092a8..f9a7ceaa3 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -103,17 +113,27 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[2]
 int_slave=system.membus.master[1]
@@ -133,8 +153,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 
 [system.cpu.tracer]
@@ -206,6 +231,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -217,7 +243,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -252,10 +282,15 @@ port=system.membus.master[2]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
index 465ea0a99..c68473235 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:52
-gem5 executing on zizzer, pid 17890
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:19
+gem5 executing on e108600-lin, pid 18562
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
index 9c22d46ab..f9a903a5e 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000445                       # Nu
 sim_ticks                                   445082000                       # Number of ticks simulated
 final_tick                                  445082000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 219197                       # Simulator instruction rate (inst/s)
-host_op_rate                                   395662                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17068456983                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 691636                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 125099                       # Simulator instruction rate (inst/s)
+host_op_rate                                   225788                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9739384878                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 648172                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -357,6 +357,7 @@ system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port        14327
 system.membus.pkt_size_system.cpu.dcache_port::total        14327                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   72591                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              9308                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.782445                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.412605                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
index 84612ddd1..1ce461f16 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -61,6 +66,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.clk_domain
 cpu_id=-1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -76,6 +82,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -100,12 +110,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -124,8 +139,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -139,8 +159,13 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 
 [system.cpu.icache]
@@ -150,12 +175,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -174,18 +204,28 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=16384
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[1]
 int_slave=system.membus.master[1]
@@ -205,8 +245,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 
 [system.cpu.tracer]
@@ -248,10 +293,15 @@ transition_latency=100000000
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.l2bus.snoop_filter
 snoop_response_latency=1
@@ -275,12 +325,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -299,8 +354,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -338,6 +398,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -349,7 +410,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:536870911
 ranks_per_channel=2
 read_buffer_size=32
@@ -384,10 +449,15 @@ port=system.membus.master[2]
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr
index 8e03cc523..2f9507495 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
index 184ec1b39..cdf63e901 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:53
-gem5 executing on zizzer, pid 17895
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:17
+gem5 executing on e108600-lin, pid 18545
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
index 41d5837a9..7d909cf8e 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000056                       # Nu
 sim_ticks                                    55844000                       # Number of ticks simulated
 final_tick                                   55844000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304150                       # Simulator instruction rate (inst/s)
-host_op_rate                                   548931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2970813002                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 696756                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 197644                       # Simulator instruction rate (inst/s)
+host_op_rate                                   356622                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1929610808                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 652268                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -523,6 +523,7 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8640                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    23680                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.snoops                                 0                       # Total snoops (count)
+system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
 system.l2bus.snoop_fanout::samples                370                       # Request fanout histogram
 system.l2bus.snoop_fanout::mean              0.002703                       # Request fanout histogram
 system.l2bus.snoop_fanout::stdev             0.051988                       # Request fanout histogram
@@ -682,6 +683,7 @@ system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        2329
 system.membus.pkt_size_system.l2cache.mem_side::total        23296                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   23296                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               364                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 1c0f40c55..01ff6a1ab 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[4]
 
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[3]
 
@@ -218,9 +248,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
@@ -250,10 +280,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:268435455
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 0868020ea..fcb337fda 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:19
-gem5 executing on zizzer, pid 20715
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:23
+gem5 executing on e108600-lin, pid 23089
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 2b946b0e1..5d52b3854 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.054141                       # Nu
 sim_ticks                                 54141000500                       # Number of ticks simulated
 final_tick                                54141000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2060319                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2070580                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1231177946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436424                       # Number of bytes of host memory used
-host_seconds                                    43.98                       # Real time elapsed on the host
+host_inst_rate                                1047421                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1052637                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              625903844                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 389680                       # Number of bytes of host memory used
+host_seconds                                    86.50                       # Real time elapsed on the host
 sim_insts                                    90602408                       # Number of instructions simulated
 sim_ops                                      91053639                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323084
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               540247820                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         135031171                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.798562                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 144fe8415..8e2469e68 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -114,8 +129,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +226,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -303,8 +358,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -312,10 +372,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -346,9 +411,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
@@ -378,10 +443,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:268435455
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
index 6c1776dde..70c7c951b 100755
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:47
-gem5 executing on zizzer, pid 20773
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:58:41
+gem5 executing on e108600-lin, pid 24094
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 1c05d7789..6dcb559f6 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147149                       # Nu
 sim_ticks                                147148719500                       # Number of ticks simulated
 final_tick                               147148719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1337875                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1344524                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2173475460                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 445404                       # Number of bytes of host memory used
-host_seconds                                    67.70                       # Real time elapsed on the host
+host_inst_rate                                 664401                       # Simulator instruction rate (inst/s)
+host_op_rate                                   667702                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1079367051                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 398392                       # Number of bytes of host memory used
+host_seconds                                   136.33                       # Real time elapsed on the host
 sim_insts                                    90576862                       # Number of instructions simulated
 sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -618,6 +618,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          120942912                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples       947397                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000132                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.011486                       # Request fanout histogram
@@ -645,6 +646,7 @@ system.membus.pkt_count::total                  30680                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  981760                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples             15340                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index c428f015f..c9c77a327 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -117,9 +127,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
@@ -149,10 +159,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:268435455
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index db6d1fe13..99db763e0 100755
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:24
-gem5 executing on zizzer, pid 8701
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:35
+gem5 executing on e108600-lin, pid 38668
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 329845e75..7bb62e016 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.122216                       # Nu
 sim_ticks                                122215823500                       # Number of ticks simulated
 final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2850562                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2850680                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1428826010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 416224                       # Number of bytes of host memory used
-host_seconds                                    85.54                       # Real time elapsed on the host
+host_inst_rate                                2052281                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2052366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1028692544                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371448                       # Number of bytes of host memory used
+host_seconds                                   118.81                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -114,6 +114,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    977685992
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    420311185                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total              1397997177                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         349547768                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.699251                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.458584                       # Request fanout histogram
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index a935118c3..b442fbc66 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -101,18 +111,28 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[5]
 int_slave=system.membus.master[2]
@@ -132,8 +152,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[3]
 
@@ -151,9 +176,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
@@ -183,10 +208,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -201,11 +231,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:268435455
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 593cf5faf..42e1355e1 100755
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:53
-gem5 executing on zizzer, pid 17901
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:17
+gem5 executing on e108600-lin, pid 18547
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index cac921e45..20d186f41 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950040000                       # Number of ticks simulated
 final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1541579                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2714473                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1648535817                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 443832                       # Number of bytes of host memory used
-host_seconds                                   102.49                       # Real time elapsed on the host
+host_inst_rate                                 780506                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1374345                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              834658386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 397512                       # Number of bytes of host memory used
+host_seconds                                   202.42                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -120,6 +120,7 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    960419130
 system.membus.pkt_size_system.cpu.dcache_port::total    960419130                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total              2701988442                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         339915363                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.640442                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.479871                       # Request fanout histogram
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index f3b0d748d..5f021cba5 100644
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
index 664365742..870cfd899 100755
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index 44c2c4d4d..4aef5499e 100755
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:14
-gem5 executing on zizzer, pid 34044
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:27
+gem5 executing on e108600-lin, pid 4289
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/30.eon/alpha/tru64/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index f279a3d46..5fb1fafd0 100644
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3079687                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3079687                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1539844146                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290224                       # Number of bytes of host memory used
-host_seconds                                   129.45                       # Real time elapsed on the host
+host_inst_rate                                1645472                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1645472                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              822736272                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245476                       # Number of bytes of host memory used
+host_seconds                                   242.28                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1594658604
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1154806069                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total              2749464673                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         566939869                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.703187                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.456853                       # Request fanout histogram
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 485cbfda8..0109ebfd6 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -108,6 +114,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -167,12 +177,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +206,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -515,12 +535,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -539,8 +564,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -571,7 +601,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 kvmInSE=false
@@ -608,6 +638,7 @@ cpu_id=1
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -644,6 +675,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -703,12 +738,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -727,8 +767,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -1051,12 +1096,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -1075,8 +1125,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -1121,6 +1176,7 @@ cpu_id=2
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -1157,6 +1213,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -1216,12 +1276,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -1240,8 +1305,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -1564,12 +1634,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -1588,8 +1663,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -1634,6 +1714,7 @@ cpu_id=3
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
+default_p_state=UNDEFINED
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -1670,6 +1751,10 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -1729,12 +1814,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -1753,8 +1843,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -2077,12 +2172,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -2101,8 +2201,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -2146,12 +2251,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -2170,20 +2280,31 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=4194304
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -2191,6 +2312,13 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -2225,6 +2353,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -2236,7 +2365,11 @@ max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
+power_model=Null
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
@@ -2272,10 +2405,15 @@ port=system.membus.master[0]
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
index 341b479f7..952fc386a 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
@@ -1,2 +1,7 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: Already in the requested power state, request ignored
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 1f6d76948..64591e1c0 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,20 +1,22 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 13 2016 22:35:56
-gem5 started Mar 13 2016 22:44:20
-gem5 executing on phenom, pid 19840
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:37
+gem5 executing on e108600-lin, pid 38681
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 1] Got lock
 [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 1 completed
 [Iteration 2, Thread 1] Got lock
 [Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
@@ -30,54 +32,54 @@ Iteration 2 completed
 [Iteration 3, Thread 1] Got lock
 [Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 3 completed
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 4, Thread 3] Got lock
 [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 4 completed
 [Iteration 5, Thread 1] Got lock
 [Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 5 completed
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 6 completed
 [Iteration 7, Thread 3] Got lock
 [Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 107700000 because target called exit()
+Exiting @ tick 124523000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index b9708b9b9..8c3fa74c7 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000125                       # Nu
 sim_ticks                                   124523000                       # Number of ticks simulated
 final_tick                                  124523000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 259079                       # Simulator instruction rate (inst/s)
-host_op_rate                                   259078                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27957290                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308636                       # Number of bytes of host memory used
-host_seconds                                     4.45                       # Real time elapsed on the host
+host_inst_rate                                 143029                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143029                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               15434351                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263456                       # Number of bytes of host memory used
+host_seconds                                     8.07                       # Real time elapsed on the host
 sim_insts                                     1153943                       # Number of instructions simulated
 sim_ops                                       1153943                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -2838,6 +2838,7 @@ system.membus.pkt_count::total                   1755                       # Pa
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45632                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   45632                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              244                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              1042                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -2889,6 +2890,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 334720                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                            1023                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                     53376                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             4207                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.289042                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           1.099056                       # Request fanout histogram
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 8aa92b057..d84a9f055 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -92,12 +102,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -116,8 +131,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -133,12 +153,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -157,8 +182,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -189,7 +219,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 kvmInSE=false
@@ -209,6 +239,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -225,6 +256,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -246,12 +281,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -270,8 +310,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -287,12 +332,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -311,8 +361,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -340,6 +395,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=2
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -356,6 +412,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -377,12 +437,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -401,8 +466,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -418,12 +488,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -442,8 +517,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -471,6 +551,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=3
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -487,6 +568,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -508,12 +593,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -532,8 +622,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -549,12 +644,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -573,8 +673,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -618,12 +723,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -642,20 +752,31 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=4194304
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -663,16 +784,28 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
@@ -680,10 +813,15 @@ port=system.membus.master[0]
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
index 1a4f96712..a5c275fc8 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
@@ -1 +1,6 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: Already in the requested power state, request ignored
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 05f972a06..f5b06fc1f 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:25
-gem5 executing on zizzer, pid 8720
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:37
+gem5 executing on e108600-lin, pid 38680
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 42d05c9b0..5019ecb02 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1934217                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1934165                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              250446535                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303372                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
+host_inst_rate                                 807732                       # Simulator instruction rate (inst/s)
+host_op_rate                                   807715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              104588000                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259108                       # Number of bytes of host memory used
+host_seconds                                     0.84                       # Real time elapsed on the host
 sim_insts                                      677333                       # Number of instructions simulated
 sim_ops                                        677333                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -956,6 +956,7 @@ system.membus.pkt_count::total                   1518                       # Pa
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        35776                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   35776                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               879                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -1002,6 +1003,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 233088                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                               0                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                         0                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             3918                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.246554                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           1.199505                       # Request fanout histogram
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index b3a457f47..524dea641 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -185,7 +215,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 kvmInSE=false
@@ -205,6 +235,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=1
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -220,6 +251,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -238,12 +273,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -262,8 +302,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -279,12 +324,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -303,8 +353,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -332,6 +387,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=2
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -347,6 +403,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -365,12 +425,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -389,8 +454,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -406,12 +476,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -430,8 +505,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -459,6 +539,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=3
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -474,6 +555,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -492,12 +577,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -516,8 +606,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -533,12 +628,17 @@ addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -557,8 +657,13 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -602,12 +707,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -626,20 +736,31 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=4194304
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -647,16 +768,28 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
@@ -664,10 +797,15 @@ port=system.membus.master[0]
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
index 1a4f96712..a5c275fc8 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
@@ -1 +1,6 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: Already in the requested power state, request ignored
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 0436b2616..dc5d474a6 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:26
-gem5 executing on zizzer, pid 8732
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38675
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,47 +25,47 @@ Iteration 1 completed
 [Iteration 2, Thread 2] Got lock
 [Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 2 completed
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 5, Thread 2] Got lock
 [Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 5 completed
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 6, Thread 2] Got lock
 [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 6 completed
 [Iteration 7, Thread 2] Got lock
 [Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 7 completed
 [Iteration 8, Thread 3] Got lock
 [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 8 completed
 [Iteration 9, Thread 1] Got lock
 [Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
@@ -72,12 +74,12 @@ Iteration 8 completed
 [Iteration 9, Thread 3] Got lock
 [Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 264840500 because target called exit()
+Exiting @ tick 264174500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index be0efa0c8..78f5a0ee7 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000264                       # Nu
 sim_ticks                                   264174500                       # Number of ticks simulated
 final_tick                                  264174500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1178179                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1178160                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              469155398                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303372                       # Number of bytes of host memory used
-host_seconds                                     0.56                       # Real time elapsed on the host
+host_inst_rate                                 538178                       # Simulator instruction rate (inst/s)
+host_op_rate                                   538161                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              214299964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259104                       # Number of bytes of host memory used
+host_seconds                                     1.23                       # Real time elapsed on the host
 sim_insts                                      663394                       # Number of instructions simulated
 sim_ops                                        663394                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1581,6 +1581,7 @@ system.membus.pkt_count::total                   1482                       # Pa
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              261                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples               916                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -1631,6 +1632,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 183616                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                            1028                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                     53312                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             2919                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.272011                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           1.157273                       # Request fanout histogram
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index 8d136d962..a2f7231b1 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -52,12 +57,17 @@ voltage_domain=system.voltage_domain
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -72,12 +82,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -96,8 +111,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -105,12 +125,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -125,12 +150,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -149,8 +179,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -158,12 +193,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -178,12 +218,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -202,8 +247,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -211,12 +261,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -231,12 +286,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -255,8 +315,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -264,12 +329,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -284,12 +354,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -308,8 +383,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -317,12 +397,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -337,12 +422,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -361,8 +451,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -370,12 +465,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -390,12 +490,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -414,8 +519,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -423,12 +533,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -443,12 +558,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -467,8 +587,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -495,12 +620,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -519,8 +649,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
@@ -528,10 +663,15 @@ size=65536
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
@@ -553,11 +693,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
@@ -565,10 +710,15 @@ port=system.membus.master[0]
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
index 4771f3483..01d1cac03 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
@@ -1,73 +1,73 @@
-system.cpu5: completed 10000 read, 5633 write accesses @60486000
-system.cpu4: completed 10000 read, 5582 write accesses @61180000
-system.cpu6: completed 10000 read, 5560 write accesses @61307500
-system.cpu7: completed 10000 read, 5599 write accesses @61402000
-system.cpu2: completed 10000 read, 5643 write accesses @61472000
-system.cpu1: completed 10000 read, 5506 write accesses @61551000
-system.cpu3: completed 10000 read, 5658 write accesses @61700000
-system.cpu0: completed 10000 read, 5706 write accesses @62631500
-system.cpu5: completed 20000 read, 11103 write accesses @113616000
-system.cpu6: completed 20000 read, 10976 write accesses @113920500
-system.cpu2: completed 20000 read, 11039 write accesses @113933500
-system.cpu3: completed 20000 read, 11207 write accesses @114624500
-system.cpu4: completed 20000 read, 11084 write accesses @114955000
-system.cpu0: completed 20000 read, 11085 write accesses @115057000
-system.cpu7: completed 20000 read, 11095 write accesses @115187000
-system.cpu1: completed 20000 read, 11193 write accesses @116687500
-system.cpu5: completed 30000 read, 16705 write accesses @166840500
-system.cpu2: completed 30000 read, 16691 write accesses @167354000
-system.cpu6: completed 30000 read, 16468 write accesses @167416000
-system.cpu4: completed 30000 read, 16533 write accesses @168175000
-system.cpu3: completed 30000 read, 16715 write accesses @168594500
-system.cpu7: completed 30000 read, 16620 write accesses @168682000
-system.cpu0: completed 30000 read, 16560 write accesses @168778500
-system.cpu1: completed 30000 read, 16873 write accesses @170313500
-system.cpu2: completed 40000 read, 22285 write accesses @220155500
-system.cpu3: completed 40000 read, 22038 write accesses @220636000
-system.cpu5: completed 40000 read, 22211 write accesses @221161500
-system.cpu6: completed 40000 read, 22097 write accesses @221217500
-system.cpu7: completed 40000 read, 22095 write accesses @221239000
-system.cpu0: completed 40000 read, 22196 write accesses @221351000
-system.cpu4: completed 40000 read, 21983 write accesses @222184000
-system.cpu1: completed 40000 read, 22367 write accesses @223407000
-system.cpu2: completed 50000 read, 27562 write accesses @273475000
-system.cpu6: completed 50000 read, 27553 write accesses @273666500
-system.cpu0: completed 50000 read, 27658 write accesses @274179000
-system.cpu4: completed 50000 read, 27584 write accesses @274332000
-system.cpu3: completed 50000 read, 27495 write accesses @274461500
-system.cpu7: completed 50000 read, 27568 write accesses @274681000
-system.cpu5: completed 50000 read, 27850 write accesses @275614000
-system.cpu1: completed 50000 read, 28070 write accesses @277107000
-system.cpu2: completed 60000 read, 33123 write accesses @327185500
-system.cpu6: completed 60000 read, 33149 write accesses @327223000
-system.cpu3: completed 60000 read, 32991 write accesses @327854000
-system.cpu7: completed 60000 read, 32997 write accesses @328407000
-system.cpu0: completed 60000 read, 33282 write accesses @328452500
-system.cpu4: completed 60000 read, 33164 write accesses @329017000
-system.cpu5: completed 60000 read, 33383 write accesses @329401500
-system.cpu1: completed 60000 read, 33681 write accesses @330675000
-system.cpu2: completed 70000 read, 38702 write accesses @380801000
-system.cpu3: completed 70000 read, 38442 write accesses @381181000
-system.cpu6: completed 70000 read, 38695 write accesses @381583500
-system.cpu7: completed 70000 read, 38573 write accesses @382302000
-system.cpu0: completed 70000 read, 38773 write accesses @382499000
-system.cpu4: completed 70000 read, 38793 write accesses @383094500
-system.cpu5: completed 70000 read, 38945 write accesses @383290000
-system.cpu1: completed 70000 read, 39200 write accesses @385376000
-system.cpu2: completed 80000 read, 44175 write accesses @434108000
-system.cpu6: completed 80000 read, 44138 write accesses @434454000
-system.cpu3: completed 80000 read, 43905 write accesses @434859000
-system.cpu7: completed 80000 read, 43929 write accesses @435594500
-system.cpu0: completed 80000 read, 44322 write accesses @435767000
-system.cpu4: completed 80000 read, 44313 write accesses @436517500
-system.cpu5: completed 80000 read, 44613 write accesses @436622000
-system.cpu1: completed 80000 read, 44739 write accesses @439209000
-system.cpu6: completed 90000 read, 49689 write accesses @488185000
-system.cpu3: completed 90000 read, 49429 write accesses @488562500
-system.cpu7: completed 90000 read, 49434 write accesses @488577000
-system.cpu2: completed 90000 read, 49778 write accesses @488987500
-system.cpu0: completed 90000 read, 49893 write accesses @489736000
-system.cpu5: completed 90000 read, 50116 write accesses @489869500
-system.cpu4: completed 90000 read, 49769 write accesses @490914000
-system.cpu1: completed 90000 read, 50142 write accesses @491765500
-system.cpu6: completed 100000 read, 55059 write accesses @540820000
+system.cpu3: completed 10000 read, 5503 write accesses @55915500
+system.cpu4: completed 10000 read, 5302 write accesses @55980000
+system.cpu7: completed 10000 read, 5500 write accesses @56129000
+system.cpu2: completed 10000 read, 5342 write accesses @56146500
+system.cpu6: completed 10000 read, 5358 write accesses @56494500
+system.cpu0: completed 10000 read, 5493 write accesses @56861500
+system.cpu1: completed 10000 read, 5676 write accesses @57033500
+system.cpu5: completed 10000 read, 5528 write accesses @57497500
+system.cpu4: completed 20000 read, 10871 write accesses @105086000
+system.cpu7: completed 20000 read, 11018 write accesses @105227000
+system.cpu6: completed 20000 read, 10904 write accesses @105245500
+system.cpu0: completed 20000 read, 10841 write accesses @105416500
+system.cpu3: completed 20000 read, 11147 write accesses @105878500
+system.cpu2: completed 20000 read, 10930 write accesses @106485500
+system.cpu5: completed 20000 read, 10954 write accesses @106687000
+system.cpu1: completed 20000 read, 11324 write accesses @107095000
+system.cpu4: completed 30000 read, 16387 write accesses @154433500
+system.cpu6: completed 30000 read, 16529 write accesses @154891500
+system.cpu2: completed 30000 read, 16387 write accesses @154906000
+system.cpu3: completed 30000 read, 16756 write accesses @155604500
+system.cpu7: completed 30000 read, 16642 write accesses @155734000
+system.cpu5: completed 30000 read, 16445 write accesses @156039500
+system.cpu0: completed 30000 read, 16469 write accesses @156104500
+system.cpu1: completed 30000 read, 16825 write accesses @156708500
+system.cpu6: completed 40000 read, 21980 write accesses @203895500
+system.cpu4: completed 40000 read, 22029 write accesses @204285000
+system.cpu3: completed 40000 read, 22257 write accesses @204704000
+system.cpu7: completed 40000 read, 22193 write accesses @205001500
+system.cpu2: completed 40000 read, 22047 write accesses @205470000
+system.cpu5: completed 40000 read, 22004 write accesses @206055000
+system.cpu0: completed 40000 read, 21987 write accesses @206174000
+system.cpu1: completed 40000 read, 22532 write accesses @206732500
+system.cpu4: completed 50000 read, 27591 write accesses @253615500
+system.cpu6: completed 50000 read, 27369 write accesses @253616500
+system.cpu2: completed 50000 read, 27561 write accesses @254261500
+system.cpu7: completed 50000 read, 27945 write accesses @254398000
+system.cpu5: completed 50000 read, 27346 write accesses @254644500
+system.cpu3: completed 50000 read, 27794 write accesses @254687000
+system.cpu0: completed 50000 read, 27491 write accesses @255540000
+system.cpu1: completed 50000 read, 28147 write accesses @256393500
+system.cpu4: completed 60000 read, 33155 write accesses @302912000
+system.cpu6: completed 60000 read, 33024 write accesses @303044500
+system.cpu5: completed 60000 read, 32819 write accesses @303948500
+system.cpu7: completed 60000 read, 33412 write accesses @304003500
+system.cpu2: completed 60000 read, 33183 write accesses @305097000
+system.cpu3: completed 60000 read, 33603 write accesses @305311500
+system.cpu1: completed 60000 read, 33393 write accesses @305569000
+system.cpu0: completed 60000 read, 33038 write accesses @305621500
+system.cpu4: completed 70000 read, 38636 write accesses @352443000
+system.cpu5: completed 70000 read, 38516 write accesses @353701000
+system.cpu6: completed 70000 read, 38725 write accesses @353942000
+system.cpu7: completed 70000 read, 39072 write accesses @354424000
+system.cpu2: completed 70000 read, 38818 write accesses @354701000
+system.cpu1: completed 70000 read, 38717 write accesses @354858500
+system.cpu3: completed 70000 read, 39274 write accesses @355379500
+system.cpu0: completed 70000 read, 38744 write accesses @355617500
+system.cpu4: completed 80000 read, 44404 write accesses @402767500
+system.cpu2: completed 80000 read, 44188 write accesses @403291500
+system.cpu5: completed 80000 read, 44099 write accesses @403371500
+system.cpu7: completed 80000 read, 44629 write accesses @403854500
+system.cpu6: completed 80000 read, 44307 write accesses @404062000
+system.cpu0: completed 80000 read, 44206 write accesses @404147000
+system.cpu1: completed 80000 read, 44256 write accesses @404649000
+system.cpu3: completed 80000 read, 44966 write accesses @406154000
+system.cpu4: completed 90000 read, 49951 write accesses @452283500
+system.cpu5: completed 90000 read, 49582 write accesses @452363500
+system.cpu2: completed 90000 read, 49727 write accesses @452365500
+system.cpu6: completed 90000 read, 49789 write accesses @453642000
+system.cpu0: completed 90000 read, 49883 write accesses @453665500
+system.cpu7: completed 90000 read, 50370 write accesses @454276500
+system.cpu1: completed 90000 read, 49817 write accesses @454621500
+system.cpu3: completed 90000 read, 50461 write accesses @455559000
+system.cpu5: completed 100000 read, 55110 write accesses @501584000
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
index 78aee4704..ee02aa361 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:20:17
-gem5 started Jan 21 2016 14:20:32
-gem5 executing on zizzer, pid 63114
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter
+gem5 compiled Jul 21 2016 14:24:31
+gem5 started Jul 21 2016 14:24:50
+gem5 executing on e108600-lin, pid 18184
+command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest-filter
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 540820000 because maximum number of loads reached
+Exiting @ tick 501584000 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 863fa9c63..a994433c5 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000502                       # Nu
 sim_ticks                                   501584000                       # Number of ticks simulated
 final_tick                                  501584000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              130273139                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277304                       # Number of bytes of host memory used
-host_seconds                                     3.85                       # Real time elapsed on the host
+host_tick_rate                               67567713                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232512                       # Number of bytes of host memory used
+host_seconds                                     7.42                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.pwrStateResidencyTicks::UNDEFINED    501584000                       # Cumulative time (in ticks) in various power states
@@ -1679,6 +1679,7 @@ system.membus.pkt_count::total                 377217                       # Pa
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1076434                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                 1076434                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                            56879                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples            245548                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -1730,6 +1731,7 @@ system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      17923
 system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1782917                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total               14289488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                          336712                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  20380288                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples           624467                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.150434                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           0.985907                       # Request fanout histogram
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 10563829b..cdf2da963 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -52,12 +57,17 @@ voltage_domain=system.voltage_domain
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -72,12 +82,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -96,8 +111,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -105,12 +125,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -125,12 +150,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -149,8 +179,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -158,12 +193,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -178,12 +218,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -202,8 +247,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -211,12 +261,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -231,12 +286,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -255,8 +315,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -264,12 +329,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -284,12 +354,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -308,8 +383,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -317,12 +397,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -337,12 +422,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -361,8 +451,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -370,12 +465,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -390,12 +490,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -414,8 +519,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -423,12 +533,17 @@ size=32768
 type=MemTest
 children=l1c
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 interval=1
 max_loads=100000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 percent_functional=50
 percent_reads=65
 percent_uncacheable=10
+power_model=Null
 progress_check=5000000
 progress_interval=10000
 size=65536
@@ -443,12 +558,17 @@ addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -467,8 +587,13 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
 
@@ -495,12 +620,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -519,18 +649,28 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=65536
 
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -545,11 +685,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
@@ -557,10 +702,15 @@ port=system.membus.master[0]
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 6df4b75be..2b36322d9 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,73 +1,73 @@
-system.cpu6: completed 10000 read, 5487 write accesses @59571500
-system.cpu3: completed 10000 read, 5414 write accesses @59651500
-system.cpu7: completed 10000 read, 5388 write accesses @60317500
-system.cpu5: completed 10000 read, 5633 write accesses @60565500
-system.cpu0: completed 10000 read, 5554 write accesses @60812000
-system.cpu2: completed 10000 read, 5506 write accesses @60906000
-system.cpu4: completed 10000 read, 5667 write accesses @61020000
-system.cpu1: completed 10000 read, 5729 write accesses @61134500
-system.cpu6: completed 20000 read, 10937 write accesses @112006500
-system.cpu3: completed 20000 read, 10780 write accesses @112135000
-system.cpu7: completed 20000 read, 10967 write accesses @112826000
-system.cpu4: completed 20000 read, 11065 write accesses @113623000
-system.cpu5: completed 20000 read, 11211 write accesses @113744000
-system.cpu2: completed 20000 read, 11030 write accesses @114035000
-system.cpu0: completed 20000 read, 10992 write accesses @114045500
-system.cpu1: completed 20000 read, 11316 write accesses @114786000
-system.cpu7: completed 30000 read, 16437 write accesses @164923000
-system.cpu3: completed 30000 read, 16370 write accesses @165110500
-system.cpu6: completed 30000 read, 16452 write accesses @165210000
-system.cpu5: completed 30000 read, 16648 write accesses @166336000
-system.cpu2: completed 30000 read, 16509 write accesses @166732000
-system.cpu0: completed 30000 read, 16577 write accesses @167160500
-system.cpu4: completed 30000 read, 16715 write accesses @167466500
-system.cpu1: completed 30000 read, 16830 write accesses @168055000
-system.cpu6: completed 40000 read, 21969 write accesses @217981000
-system.cpu3: completed 40000 read, 21918 write accesses @218202000
-system.cpu7: completed 40000 read, 21990 write accesses @218219000
-system.cpu2: completed 40000 read, 21957 write accesses @218925500
-system.cpu5: completed 40000 read, 22088 write accesses @218962000
-system.cpu0: completed 40000 read, 22019 write accesses @220261500
-system.cpu4: completed 40000 read, 22141 write accesses @220429500
-system.cpu1: completed 40000 read, 22465 write accesses @221673500
-system.cpu6: completed 50000 read, 27340 write accesses @269928500
-system.cpu3: completed 50000 read, 27331 write accesses @269971000
-system.cpu7: completed 50000 read, 27530 write accesses @270791500
-system.cpu5: completed 50000 read, 27634 write accesses @271727500
-system.cpu2: completed 50000 read, 27623 write accesses @272554500
-system.cpu0: completed 50000 read, 27533 write accesses @273321500
-system.cpu4: completed 50000 read, 27756 write accesses @273793500
-system.cpu1: completed 50000 read, 28047 write accesses @275360000
-system.cpu6: completed 60000 read, 32844 write accesses @323017000
-system.cpu3: completed 60000 read, 32841 write accesses @324483500
-system.cpu5: completed 60000 read, 33251 write accesses @324526000
-system.cpu7: completed 60000 read, 33152 write accesses @324853000
-system.cpu0: completed 60000 read, 33006 write accesses @325804000
-system.cpu2: completed 60000 read, 33348 write accesses @325916500
-system.cpu4: completed 60000 read, 33317 write accesses @326721500
-system.cpu1: completed 60000 read, 33656 write accesses @328729000
-system.cpu6: completed 70000 read, 38487 write accesses @376493000
-system.cpu7: completed 70000 read, 38761 write accesses @377715000
-system.cpu3: completed 70000 read, 38353 write accesses @377922000
-system.cpu5: completed 70000 read, 38776 write accesses @378190500
-system.cpu2: completed 70000 read, 38794 write accesses @378444500
-system.cpu0: completed 70000 read, 38678 write accesses @379664500
-system.cpu4: completed 70000 read, 38900 write accesses @380595000
-system.cpu1: completed 70000 read, 39220 write accesses @382567000
-system.cpu6: completed 80000 read, 43956 write accesses @429072500
-system.cpu7: completed 80000 read, 44286 write accesses @430036500
-system.cpu5: completed 80000 read, 44299 write accesses @430673000
-system.cpu3: completed 80000 read, 43950 write accesses @431481500
-system.cpu2: completed 80000 read, 44367 write accesses @431856000
-system.cpu0: completed 80000 read, 44165 write accesses @433508500
-system.cpu4: completed 80000 read, 44456 write accesses @435070500
-system.cpu1: completed 80000 read, 44736 write accesses @436017000
-system.cpu6: completed 90000 read, 49535 write accesses @481570000
-system.cpu7: completed 90000 read, 49822 write accesses @483210500
-system.cpu5: completed 90000 read, 49824 write accesses @483444500
-system.cpu3: completed 90000 read, 49649 write accesses @484870500
-system.cpu2: completed 90000 read, 50045 write accesses @485829000
-system.cpu0: completed 90000 read, 49706 write accesses @486425000
-system.cpu4: completed 90000 read, 49831 write accesses @488248500
-system.cpu1: completed 90000 read, 50268 write accesses @489877001
-system.cpu6: completed 100000 read, 54955 write accesses @534039500
+system.cpu2: completed 10000 read, 5501 write accesses @55798000
+system.cpu1: completed 10000 read, 5520 write accesses @55942500
+system.cpu4: completed 10000 read, 5672 write accesses @55948000
+system.cpu0: completed 10000 read, 5544 write accesses @56022500
+system.cpu6: completed 10000 read, 5523 write accesses @56194500
+system.cpu5: completed 10000 read, 5576 write accesses @56196500
+system.cpu3: completed 10000 read, 5638 write accesses @56648500
+system.cpu7: completed 10000 read, 5609 write accesses @56820000
+system.cpu6: completed 20000 read, 11092 write accesses @104740000
+system.cpu4: completed 20000 read, 11217 write accesses @105227500
+system.cpu0: completed 20000 read, 11130 write accesses @105598500
+system.cpu5: completed 20000 read, 11119 write accesses @105604000
+system.cpu2: completed 20000 read, 11021 write accesses @105822000
+system.cpu7: completed 20000 read, 11085 write accesses @105988500
+system.cpu3: completed 20000 read, 11232 write accesses @106234000
+system.cpu1: completed 20000 read, 11093 write accesses @106248000
+system.cpu6: completed 30000 read, 16618 write accesses @154364000
+system.cpu4: completed 30000 read, 16727 write accesses @154528000
+system.cpu5: completed 30000 read, 16661 write accesses @154991500
+system.cpu0: completed 30000 read, 16578 write accesses @155150000
+system.cpu7: completed 30000 read, 16597 write accesses @155572000
+system.cpu3: completed 30000 read, 16777 write accesses @155692000
+system.cpu2: completed 30000 read, 16783 write accesses @155741500
+system.cpu1: completed 30000 read, 16605 write accesses @155757500
+system.cpu4: completed 40000 read, 22227 write accesses @203532500
+system.cpu0: completed 40000 read, 22094 write accesses @203735500
+system.cpu2: completed 40000 read, 22329 write accesses @204034500
+system.cpu6: completed 40000 read, 22323 write accesses @204341500
+system.cpu5: completed 40000 read, 22093 write accesses @204530500
+system.cpu3: completed 40000 read, 22449 write accesses @204979500
+system.cpu7: completed 40000 read, 22085 write accesses @205200000
+system.cpu1: completed 40000 read, 22157 write accesses @205324500
+system.cpu2: completed 50000 read, 27810 write accesses @252814500
+system.cpu0: completed 50000 read, 27524 write accesses @252975000
+system.cpu4: completed 50000 read, 27619 write accesses @253195000
+system.cpu6: completed 50000 read, 27815 write accesses @253668000
+system.cpu5: completed 50000 read, 27749 write accesses @254286500
+system.cpu3: completed 50000 read, 28015 write accesses @254662000
+system.cpu1: completed 50000 read, 27700 write accesses @255277000
+system.cpu7: completed 50000 read, 27537 write accesses @255788500
+system.cpu2: completed 60000 read, 33479 write accesses @302616500
+system.cpu4: completed 60000 read, 33151 write accesses @302639500
+system.cpu0: completed 60000 read, 33158 write accesses @302949000
+system.cpu5: completed 60000 read, 33293 write accesses @303327000
+system.cpu6: completed 60000 read, 33367 write accesses @303498500
+system.cpu3: completed 60000 read, 33551 write accesses @304167000
+system.cpu1: completed 60000 read, 33190 write accesses @304842500
+system.cpu7: completed 60000 read, 33105 write accesses @305455501
+system.cpu4: completed 70000 read, 38677 write accesses @351659000
+system.cpu0: completed 70000 read, 38797 write accesses @352214500
+system.cpu2: completed 70000 read, 39135 write accesses @352355500
+system.cpu6: completed 70000 read, 38839 write accesses @353200500
+system.cpu5: completed 70000 read, 38774 write accesses @353284000
+system.cpu3: completed 70000 read, 38980 write accesses @353497000
+system.cpu1: completed 70000 read, 38895 write accesses @355264000
+system.cpu7: completed 70000 read, 38703 write accesses @355598500
+system.cpu2: completed 80000 read, 44512 write accesses @400360000
+system.cpu4: completed 80000 read, 44241 write accesses @401405500
+system.cpu0: completed 80000 read, 44424 write accesses @401492500
+system.cpu6: completed 80000 read, 44426 write accesses @402695000
+system.cpu5: completed 80000 read, 44250 write accesses @402938000
+system.cpu3: completed 80000 read, 44495 write accesses @403103500
+system.cpu1: completed 80000 read, 44343 write accesses @403920500
+system.cpu7: completed 80000 read, 44194 write accesses @404626000
+system.cpu0: completed 90000 read, 49874 write accesses @450153000
+system.cpu2: completed 90000 read, 50018 write accesses @450453000
+system.cpu4: completed 90000 read, 49959 write accesses @452038500
+system.cpu3: completed 90000 read, 50050 write accesses @452249000
+system.cpu5: completed 90000 read, 49902 write accesses @452294500
+system.cpu6: completed 90000 read, 50125 write accesses @453074500
+system.cpu1: completed 90000 read, 49995 write accesses @453105500
+system.cpu7: completed 90000 read, 49805 write accesses @454516500
+system.cpu2: completed 100000 read, 55556 write accesses @500337000
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
index b41d812d8..b287697fe 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:20:17
-gem5 started Jan 21 2016 14:20:31
-gem5 executing on zizzer, pid 63111
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
+gem5 compiled Jul 21 2016 14:24:31
+gem5 started Jul 21 2016 14:24:50
+gem5 executing on e108600-lin, pid 18186
+command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 534039500 because maximum number of loads reached
+Exiting @ tick 500337000 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index e55bb9c63..bfbf99e79 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000500                       # Nu
 sim_ticks                                   500337000                       # Number of ticks simulated
 final_tick                                  500337000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              117513072                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278328                       # Number of bytes of host memory used
-host_seconds                                     4.26                       # Real time elapsed on the host
+host_tick_rate                               71022114                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232508                       # Number of bytes of host memory used
+host_seconds                                     7.04                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.pwrStateResidencyTicks::UNDEFINED    500337000                       # Cumulative time (in ticks) in various power states
@@ -1672,6 +1672,7 @@ system.membus.pkt_count::total                 377440                       # Pa
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1081783                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                 1081783                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                            56900                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples            253448                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -1724,6 +1725,7 @@ system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      17966
 system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1788086                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total               14339895                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                          335681                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  20309376                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples           623777                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.148975                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           0.984758                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index c720d6208..2d4d209f1 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 222f46a4b..0d37b2b08 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:01
-gem5 executing on zizzer, pid 33985
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:27
+gem5 executing on e108600-lin, pid 4293
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index f25ed6812..a2e00980d 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3085186                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3085185                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1544361453                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293364                       # Number of bytes of host memory used
-host_seconds                                    28.63                       # Real time elapsed on the host
+host_inst_rate                                1536521                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1536520                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              769141125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247596                       # Number of bytes of host memory used
+host_seconds                                    57.49                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    353752292
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    218355543                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               572107835                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         123328088                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.717096                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.450410                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 5de9bc371..d07d610d6 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -203,8 +238,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -212,10 +252,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -246,7 +291,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -278,10 +323,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -296,11 +346,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index d1b551788..d72d31595 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:00
-gem5 executing on zizzer, pid 33970
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:27
+gem5 executing on e108600-lin, pid 4294
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index b00dd906e..51d70d56c 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.134742                       # Nu
 sim_ticks                                134741611500                       # Number of ticks simulated
 final_tick                               134741611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1731648                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1731647                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2641194476                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302344                       # Number of bytes of host memory used
-host_seconds                                    51.02                       # Real time elapsed on the host
+host_inst_rate                                 968280                       # Simulator instruction rate (inst/s)
+host_op_rate                                   968280                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1476869211                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256564                       # Number of bytes of host memory used
+host_seconds                                    91.23                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -510,6 +510,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23847808                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total           33500736                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      131998                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               7320448                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples       412778                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.009388                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.096434                       # Request fanout histogram
@@ -539,6 +540,7 @@ system.membus.pkt_count::total                 456523                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17825920                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                17825920                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples            292375                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 7e0b9adf7..f1a56a700 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[4]
 
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[3]
 
@@ -218,7 +248,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -250,10 +280,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
index 315146752..99c3eacd0 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-at
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 17:50:51
-gem5 started Mar 14 2016 18:07:36
-gem5 executing on phenom, pid 27152
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:01:37
+gem5 executing on e108600-lin, pid 24147
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 00bb71a79..4508adaf3 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.048960                       # Nu
 sim_ticks                                 48960022500                       # Number of ticks simulated
 final_tick                                48960022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1718625                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2197882                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1186575552                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310104                       # Number of bytes of host memory used
-host_seconds                                    41.26                       # Real time elapsed on the host
+host_inst_rate                                 832939                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1065213                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              575079073                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264380                       # Number of bytes of host memory used
+host_seconds                                    85.14                       # Real time elapsed on the host
 sim_insts                                    70913204                       # Number of instructions simulated
 sim_ops                                      90688159                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    312580364
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    185233556                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               497813920                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         120930641                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.646198                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.478149                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index c84baeb43..e7e819a35 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -114,8 +129,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +226,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -303,8 +358,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -312,10 +372,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -346,7 +411,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -378,10 +443,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
index 6b39172d0..34991f400 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 17:50:51
-gem5 started Mar 14 2016 18:03:19
-gem5 executing on phenom, pid 27037
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:22
+gem5 executing on e108600-lin, pid 23076
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b2023c05c..60128a0c8 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.128077                       # Nu
 sim_ticks                                128076834500                       # Number of ticks simulated
 final_tick                               128076834500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1093594                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1396212                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1990290276                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320240                       # Number of bytes of host memory used
-host_seconds                                    64.35                       # Real time elapsed on the host
+host_inst_rate                                 523174                       # Simulator instruction rate (inst/s)
+host_op_rate                                   667947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              952153159                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273092                       # Number of bytes of host memory used
+host_seconds                                   134.51                       # Real time elapsed on the host
 sim_insts                                    70373651                       # Number of instructions simulated
 sim_ops                                      89847385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -630,6 +630,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18443072                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total           20734144                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       95333                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5513600                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples       274239                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.025051                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.156979                       # Request fanout histogram
@@ -659,6 +660,7 @@ system.membus.pkt_count::total                 347268                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13672000                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                13672000                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples            219817                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 61556605d..3a4f61f9d 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -117,7 +127,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -149,10 +159,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
index 7405f50a8..e38712610 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: ignoring syscall time(4026527848, ...)
 warn: ignoring syscall time(4026527400, ...)
 warn: ignoring syscall time(4026527312, ...)
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 98ece2f0d..09707d695 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 17:46:51
-gem5 started Mar 14 2016 17:54:20
-gem5 executing on phenom, pid 26843
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:35
+gem5 executing on e108600-lin, pid 38667
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index ff66806fe..5541d62f0 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148677000                       # Number of ticks simulated
 final_tick                                68148677000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2845356                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2882198                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1442772972                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292276                       # Number of bytes of host memory used
-host_seconds                                    47.23                       # Real time elapsed on the host
+host_inst_rate                                1812136                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1835600                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              918865875                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247504                       # Number of bytes of host memory used
+host_seconds                                    74.17                       # Real time elapsed on the host
 sim_insts                                   134398959                       # Number of instructions simulated
 sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -114,6 +114,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    538214320
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    237569638                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               775783958                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         192665100                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.698381                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.458961                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index f020fab37..14d66f92a 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -178,12 +208,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -202,8 +237,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -211,10 +251,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -245,7 +290,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
@@ -277,10 +322,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -295,11 +345,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
index 7405f50a8..e38712610 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: ignoring syscall time(4026527848, ...)
 warn: ignoring syscall time(4026527400, ...)
 warn: ignoring syscall time(4026527312, ...)
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
index d24399f8c..8920b4c6b 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 17:46:51
-gem5 started Mar 14 2016 17:55:53
-gem5 executing on phenom, pid 26906
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:38
+gem5 executing on e108600-lin, pid 38688
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index be1596583..e21e8eadd 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.203116                       # Nu
 sim_ticks                                203115946500                       # Number of ticks simulated
 final_tick                               203115946500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1546845                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1566874                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2337732587                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302284                       # Number of bytes of host memory used
-host_seconds                                    86.89                       # Real time elapsed on the host
+host_inst_rate                                1206960                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1222588                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1824068108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256216                       # Number of bytes of host memory used
+host_seconds                                   111.35                       # Real time elapsed on the host
 sim_insts                                   134398959                       # Number of instructions simulated
 sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -499,6 +499,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     17570816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total           41378816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       99022                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5457280                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples       436725                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.008273                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.090579                       # Request fanout histogram
@@ -528,6 +529,7 @@ system.membus.pkt_count::total                 356615                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13810688                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                13810688                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples            226093                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
index fdc10b410..50754e5cd 100644
--- a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
+++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.010000                       # Nu
 sim_ticks                                 10000000000                       # Number of ticks simulated
 final_tick                                10000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              757790256                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1498684                       # Number of bytes of host memory used
-host_seconds                                    13.20                       # Real time elapsed on the host
+host_tick_rate                              494870114                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1444260                       # Number of bytes of host memory used
+host_seconds                                    20.21                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.pwrStateResidencyTicks::UNDEFINED  10000000000                       # Cumulative time (in ticks) in various power states
@@ -343,6 +343,7 @@ system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsy
 system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side       539600                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys0.xbar.pkt_size::total         1078992                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys0.xbar.snoops                   144671                       # Total snoops (count)
+system.l0subsys0.xbar.snoopTraffic            1556096                       # Total snoop traffic (bytes)
 system.l0subsys0.xbar.snoop_fanout::samples       282356                       # Request fanout histogram
 system.l0subsys0.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys0.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -392,6 +393,7 @@ system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsy
 system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side       545392                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys1.xbar.pkt_size::total         1066832                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys1.xbar.snoops                   140058                       # Total snoops (count)
+system.l0subsys1.xbar.snoopTraffic            1579904                       # Total snoop traffic (bytes)
 system.l0subsys1.xbar.snoop_fanout::samples       276384                       # Request fanout histogram
 system.l0subsys1.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys1.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -441,6 +443,7 @@ system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsy
 system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side       522048                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys2.xbar.pkt_size::total         1043824                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys2.xbar.snoops                   138132                       # Total snoops (count)
+system.l0subsys2.xbar.snoopTraffic            1465472                       # Total snoop traffic (bytes)
 system.l0subsys2.xbar.snoop_fanout::samples       271270                       # Request fanout histogram
 system.l0subsys2.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys2.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -490,6 +493,7 @@ system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsy
 system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side       510192                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys3.xbar.pkt_size::total         1038312                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys3.xbar.snoops                   140587                       # Total snoops (count)
+system.l0subsys3.xbar.snoopTraffic            1458624                       # Total snoop traffic (bytes)
 system.l0subsys3.xbar.snoop_fanout::samples       272839                       # Request fanout histogram
 system.l0subsys3.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys3.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -539,6 +543,7 @@ system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsy
 system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side       526040                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys4.xbar.pkt_size::total         1063512                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys4.xbar.snoops                   137978                       # Total snoops (count)
+system.l0subsys4.xbar.snoopTraffic            1507200                       # Total snoop traffic (bytes)
 system.l0subsys4.xbar.snoop_fanout::samples       273585                       # Request fanout histogram
 system.l0subsys4.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys4.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -588,6 +593,7 @@ system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsy
 system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side       522456                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys5.xbar.pkt_size::total         1059400                       # Cumulative packet size per connected master and slave (bytes)
 system.l0subsys5.xbar.snoops                   141834                       # Total snoops (count)
+system.l0subsys5.xbar.snoopTraffic            1525248                       # Total snoop traffic (bytes)
 system.l0subsys5.xbar.snoop_fanout::samples       276831                       # Request fanout histogram
 system.l0subsys5.xbar.snoop_fanout::mean            0                       # Request fanout histogram
 system.l0subsys5.xbar.snoop_fanout::stdev            0                       # Request fanout histogram
@@ -946,6 +952,7 @@ system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys
 system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side      9043712                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys0.xbar.pkt_size::total        18352320                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys0.xbar.snoops                   293338                       # Total snoops (count)
+system.l1subsys0.xbar.snoopTraffic            6950656                       # Total snoop traffic (bytes)
 system.l1subsys0.xbar.snoop_fanout::samples       440460                       # Request fanout histogram
 system.l1subsys0.xbar.snoop_fanout::mean     0.353033                       # Request fanout histogram
 system.l1subsys0.xbar.snoop_fanout::stdev     0.545932                       # Request fanout histogram
@@ -1308,6 +1315,7 @@ system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys
 system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side      8958272                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys1.xbar.pkt_size::total        17742848                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys1.xbar.snoops                   288962                       # Total snoops (count)
+system.l1subsys1.xbar.snoopTraffic            6862464                       # Total snoop traffic (bytes)
 system.l1subsys1.xbar.snoop_fanout::samples       427858                       # Request fanout histogram
 system.l1subsys1.xbar.snoop_fanout::mean     0.369602                       # Request fanout histogram
 system.l1subsys1.xbar.snoop_fanout::stdev     0.556507                       # Request fanout histogram
@@ -1670,6 +1678,7 @@ system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys
 system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side      9148608                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys2.xbar.pkt_size::total        18051584                       # Cumulative packet size per connected master and slave (bytes)
 system.l1subsys2.xbar.snoops                   290665                       # Total snoops (count)
+system.l1subsys2.xbar.snoopTraffic            6825600                       # Total snoop traffic (bytes)
 system.l1subsys2.xbar.snoop_fanout::samples       435074                       # Request fanout histogram
 system.l1subsys2.xbar.snoop_fanout::mean     0.354188                       # Request fanout histogram
 system.l1subsys2.xbar.snoop_fanout::stdev     0.543249                       # Request fanout histogram
@@ -2756,6 +2765,7 @@ system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.
 system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port      2937216                       # Cumulative packet size per connected master and slave (bytes)
 system.l2subsys0.xbar.pkt_size::total        37220160                       # Cumulative packet size per connected master and slave (bytes)
 system.l2subsys0.xbar.snoops                   200506                       # Total snoops (count)
+system.l2subsys0.xbar.snoopTraffic           10418304                       # Total snoop traffic (bytes)
 system.l2subsys0.xbar.snoop_fanout::samples       652264                       # Request fanout histogram
 system.l2subsys0.xbar.snoop_fanout::mean     0.480016                       # Request fanout histogram
 system.l2subsys0.xbar.snoop_fanout::stdev     0.745912                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 60c231209..9503e5d69 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 96d4044c7..0dad23f1c 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:03
-gem5 executing on zizzer, pid 34012
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:28
+gem5 executing on e108600-lin, pid 4296
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-atomic
 
 Couldn't unlink  build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
 Couldn't unlink  build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index ba862710c..767676900 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3168591                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3168590                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1584296087                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288936                       # Number of bytes of host memory used
-host_seconds                                    29.00                       # Real time elapsed on the host
+host_inst_rate                                1662720                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1662720                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              831360258                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243160                       # Number of bytes of host memory used
+host_seconds                                    55.27                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    367612356
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    139258495                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               506870851                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         118400390                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.776206                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.416786                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 65b4d26d0..5f464084f 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -203,8 +238,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -212,10 +252,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -246,7 +291,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -278,10 +323,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -296,11 +346,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index fc1844e03..833b11d37 100755
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:00
-gem5 executing on zizzer, pid 33964
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:28
+gem5 executing on e108600-lin, pid 4297
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-timing
 
 Couldn't unlink  build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sav
 Couldn't unlink  build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 12386b790..7a58e848d 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118763                       # Nu
 sim_ticks                                118762761500                       # Number of ticks simulated
 final_tick                               118762761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1861883                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1861883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2406038400                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298932                       # Number of bytes of host memory used
-host_seconds                                    49.36                       # Real time elapsed on the host
+host_inst_rate                                1076459                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1076459                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1391065983                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253156                       # Number of bytes of host memory used
+host_seconds                                    85.38                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -500,6 +500,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149120                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total            1121344                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples        10733                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
@@ -527,6 +528,7 @@ system.membus.pkt_count::total                   9530                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       304960                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  304960                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              4765                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 291d88b45..ac8a9f7d1 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[4]
 
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.membus.slave[3]
 
@@ -218,7 +248,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -250,10 +280,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
index 01f7a2d96..5f855da74 100755
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -3,11 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:39
-gem5 executing on zizzer, pid 20766
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:25
+gem5 executing on e108600-lin, pid 23093
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-atomic
 
+Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index a504e35f9..1f598d967 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.099596                       # Nu
 sim_ticks                                 99596491500                       # Number of ticks simulated
 final_tick                                99596491500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2111044                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2225381                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1220146763                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306656                       # Number of bytes of host memory used
-host_seconds                                    81.63                       # Real time elapsed on the host
+host_inst_rate                                 985729                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1039117                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              569734073                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259900                       # Number of bytes of host memory used
+host_seconds                                   174.81                       # Real time elapsed on the host
 sim_insts                                   172317410                       # Number of instructions simulated
 sim_ops                                     181650342                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    759440208
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    155786601                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               915226809                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         230024467                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.825391                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.379633                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index ca7f3c7de..4b53ac3b8 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -114,8 +129,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -191,8 +226,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 
 [system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -303,8 +358,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -312,10 +372,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -346,7 +411,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -378,10 +443,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
index 64f9b8146..c9961e3be 100755
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -3,11 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:45:42
-gem5 started Jan 21 2016 14:46:22
-gem5 executing on zizzer, pid 20735
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:45:16
+gem5 executing on e108600-lin, pid 23175
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-timing
 
+Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index f6691b610..b87761f8a 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.230198                       # Nu
 sim_ticks                                230197694500                       # Number of ticks simulated
 final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1499491                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1580842                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2008696236                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 315632                       # Number of bytes of host memory used
-host_seconds                                   114.60                       # Real time elapsed on the host
+host_inst_rate                                 688414                       # Simulator instruction rate (inst/s)
+host_op_rate                                   725763                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              922189750                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268612                       # Number of bytes of host memory used
+host_seconds                                   249.62                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -614,6 +614,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       115520                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             407168                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples         4840                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.033471                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.179882                       # Request fanout histogram
@@ -641,6 +642,7 @@ system.membus.pkt_count::total                   6906                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       220992                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  220992                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              3453                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 141a140d3..3fd1ef26a 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -117,7 +127,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -149,10 +159,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 51e17a4c6..87c7a18cb 100755
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:26
-gem5 executing on zizzer, pid 8722
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38671
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-atomic
 
 Couldn't unlink  build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 00d6259ce..8e1219235 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722945000                       # Number of ticks simulated
 final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2890225                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2890229                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1445122551                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 288744                       # Number of bytes of host memory used
-host_seconds                                    66.93                       # Real time elapsed on the host
+host_inst_rate                                2018052                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2018054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1009032749                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243964                       # Number of bytes of host memory used
+host_seconds                                    95.86                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -114,6 +114,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    773782140
 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    295708073                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total              1069490213                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         270179448                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.715989                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.450942                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 86ee03838..f82285b56 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -112,8 +127,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -153,8 +178,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
@@ -178,12 +208,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -202,8 +237,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -211,10 +251,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -245,7 +290,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -277,10 +322,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -295,11 +345,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout
index d9abfd9b9..fcd3cff78 100755
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:24
-gem5 executing on zizzer, pid 8707
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:36
+gem5 executing on e108600-lin, pid 38674
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing
 
 Couldn't unlink  build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index a32bf8738..68f4496ce 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270600                       # Nu
 sim_ticks                                270599529500                       # Number of ticks simulated
 final_tick                               270599529500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1741327                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1741329                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2435851420                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298736                       # Number of bytes of host memory used
-host_seconds                                   111.09                       # Real time elapsed on the host
+host_inst_rate                                1216795                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1216796                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1702111428                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252676                       # Number of bytes of host memory used
+host_seconds                                   158.98                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -481,6 +481,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       100992                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total            1550592                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples        13864                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000072                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.008493                       # Request fanout histogram
@@ -508,6 +509,7 @@ system.membus.pkt_count::total                  10346                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       331072                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  331072                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              5173                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 51d8f4004..f53bc72d5 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -101,18 +111,28 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[5]
 int_slave=system.membus.master[2]
@@ -132,8 +152,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.membus.slave[3]
 
@@ -151,7 +176,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -183,10 +208,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -201,11 +231,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 5842ab9bc..f40711d5c 100755
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:53
-gem5 executing on zizzer, pid 17904
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:17
+gem5 executing on e108600-lin, pid 18540
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic
 
 Couldn't unlink  build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav
 Couldn't unlink  build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 044a8cac9..d9da66da0 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393279000                       # Number of ticks simulated
 final_tick                               131393279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1595970                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2674991                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1587777431                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 331680                       # Number of bytes of host memory used
-host_seconds                                    82.75                       # Real time elapsed on the host
+host_inst_rate                                 762262                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1277621                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              758349320                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285232                       # Number of bytes of host memory used
+host_seconds                                   173.26                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -120,6 +120,7 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    410245943
 system.membus.pkt_size_system.cpu.dcache_port::total    410245943                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total              1798200879                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples         250692103                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.692062                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.461641                       # Request fanout histogram
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 03ef1ba17..d04de745f 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -118,8 +133,13 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=262144
 
@@ -133,8 +153,13 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -145,12 +170,17 @@ addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -169,18 +199,28 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.membus.slave[2]
 int_slave=system.membus.master[2]
@@ -200,8 +240,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
@@ -212,12 +257,17 @@ addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
 hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
@@ -236,8 +286,13 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=2097152
 
@@ -245,10 +300,15 @@ size=2097152
 type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=false
+power_model=Null
 response_latency=1
 snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
@@ -279,7 +339,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
@@ -311,10 +371,15 @@ transition_latency=100000000
 [system.membus]
 type=CoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 point_of_coherency=true
+power_model=Null
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -329,11 +394,16 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 range=0:134217727
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr
@@ -1 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout
index 985e23889..6626953b4 100755
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:53
-gem5 executing on zizzer, pid 17898
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing
+gem5 compiled Jul 21 2016 14:35:23
+gem5 started Jul 21 2016 14:36:18
+gem5 executing on e108600-lin, pid 18557
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing
 
 Couldn't unlink  build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 42017c57f..1f70ed165 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250987                       # Nu
 sim_ticks                                250987138500                       # Number of ticks simulated
 final_tick                               250987138500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1028477                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1723822                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1954510825                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 341680                       # Number of bytes of host memory used
-host_seconds                                   128.41                       # Real time elapsed on the host
+host_inst_rate                                 493662                       # Simulator instruction rate (inst/s)
+host_op_rate                                   827423                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              938152393                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294200                       # Number of bytes of host memory used
+host_seconds                                   267.53                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -474,6 +474,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       122368                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total             604288                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples         6599                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000152                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.012310                       # Request fanout histogram
@@ -503,6 +504,7 @@ system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       30
 system.membus.pkt_size_system.cpu.l2cache.mem_side::total       303040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  303040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples              4735                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-- 
cgit v1.2.3