From 89ea32325094665c16688212b5a2cd7b7bbf5f03 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@gmail.com>
Date: Mon, 16 Feb 2009 12:09:45 -0500
Subject: Update stats for new prefetching fixes. Prefetching is not enabled in
 any of our regressions, so no significant stat values have changed, but
 zero-valued prefetch stats no longer show up when prefetching is disabled so
 there are noticable changes in the reference stat files anyway.

---
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  | 12 +--
 .../00.hello/ref/alpha/linux/o3-timing/simerr      |  4 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout      | 10 +--
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   | 35 +--------
 .../ref/alpha/linux/simple-atomic/config.ini       |  3 +
 .../00.hello/ref/alpha/linux/simple-atomic/simerr  |  4 +-
 .../00.hello/ref/alpha/linux/simple-atomic/simout  | 10 +--
 .../ref/alpha/linux/simple-atomic/stats.txt        |  8 +-
 .../ref/alpha/linux/simple-timing/config.ini       | 12 +--
 .../00.hello/ref/alpha/linux/simple-timing/simerr  |  4 +-
 .../00.hello/ref/alpha/linux/simple-timing/simout  | 10 +--
 .../ref/alpha/linux/simple-timing/stats.txt        | 35 +--------
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  | 12 +--
 .../00.hello/ref/alpha/tru64/o3-timing/simerr      |  5 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout      | 10 +--
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   | 35 +--------
 .../ref/alpha/tru64/simple-atomic/config.ini       |  3 +
 .../00.hello/ref/alpha/tru64/simple-atomic/simerr  |  5 +-
 .../00.hello/ref/alpha/tru64/simple-atomic/simout  | 10 +--
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       | 12 +--
 .../00.hello/ref/alpha/tru64/simple-timing/simerr  |  5 +-
 .../00.hello/ref/alpha/tru64/simple-timing/simout  | 10 +--
 .../ref/alpha/tru64/simple-timing/stats.txt        | 33 +-------
 .../ref/mips/linux/simple-atomic/config.ini        |  3 +
 .../00.hello/ref/mips/linux/simple-atomic/simerr   |  4 +-
 .../00.hello/ref/mips/linux/simple-atomic/simout   | 10 +--
 .../ref/mips/linux/simple-atomic/stats.txt         |  8 +-
 .../ref/mips/linux/simple-timing/config.ini        | 12 +--
 .../00.hello/ref/mips/linux/simple-timing/simerr   |  4 +-
 .../00.hello/ref/mips/linux/simple-timing/simout   | 10 +--
 .../ref/mips/linux/simple-timing/stats.txt         | 35 +--------
 .../ref/sparc/linux/simple-atomic/config.ini       |  3 +
 .../00.hello/ref/sparc/linux/simple-atomic/simerr  |  3 +-
 .../00.hello/ref/sparc/linux/simple-atomic/simout  |  9 +--
 .../ref/sparc/linux/simple-atomic/stats.txt        |  8 +-
 .../ref/sparc/linux/simple-timing/config.ini       | 12 +--
 .../00.hello/ref/sparc/linux/simple-timing/simerr  |  3 +-
 .../00.hello/ref/sparc/linux/simple-timing/simout  |  9 +--
 .../ref/sparc/linux/simple-timing/stats.txt        | 35 +--------
 .../ref/x86/linux/simple-atomic/config.ini         |  3 +
 .../00.hello/ref/x86/linux/simple-atomic/simerr    |  5 +-
 .../00.hello/ref/x86/linux/simple-atomic/simout    | 11 ++-
 .../00.hello/ref/x86/linux/simple-atomic/stats.txt |  8 +-
 .../ref/x86/linux/simple-timing/config.ini         | 12 +--
 .../00.hello/ref/x86/linux/simple-timing/simerr    |  5 +-
 .../00.hello/ref/x86/linux/simple-timing/simout    | 11 ++-
 .../00.hello/ref/x86/linux/simple-timing/stats.txt | 35 +--------
 .../ref/alpha/linux/o3-timing/config.ini           | 12 +--
 .../ref/alpha/linux/o3-timing/simerr               |  5 +-
 .../ref/alpha/linux/o3-timing/simout               | 11 +--
 .../ref/alpha/linux/o3-timing/stats.txt            | 35 +--------
 .../ref/sparc/linux/o3-timing/config.ini           | 12 +--
 .../02.insttest/ref/sparc/linux/o3-timing/simerr   |  3 +-
 .../02.insttest/ref/sparc/linux/o3-timing/simout   |  9 +--
 .../ref/sparc/linux/o3-timing/stats.txt            | 35 +--------
 .../ref/sparc/linux/simple-atomic/config.ini       |  3 +
 .../ref/sparc/linux/simple-atomic/simerr           |  3 +-
 .../ref/sparc/linux/simple-atomic/simout           |  9 +--
 .../ref/sparc/linux/simple-atomic/stats.txt        |  8 +-
 .../ref/sparc/linux/simple-timing/config.ini       | 12 +--
 .../ref/sparc/linux/simple-timing/simerr           |  3 +-
 .../ref/sparc/linux/simple-timing/simout           |  9 +--
 .../ref/sparc/linux/simple-timing/stats.txt        | 35 +--------
 .../linux/tsunami-simple-atomic-dual/config.ini    | 34 ++++++---
 .../alpha/linux/tsunami-simple-atomic-dual/simerr  |  6 +-
 .../alpha/linux/tsunami-simple-atomic-dual/simout  | 10 +--
 .../linux/tsunami-simple-atomic-dual/stats.txt     | 62 +--------------
 .../alpha/linux/tsunami-simple-atomic/config.ini   | 27 +++++--
 .../ref/alpha/linux/tsunami-simple-atomic/simerr   |  5 +-
 .../ref/alpha/linux/tsunami-simple-atomic/simout   | 10 +--
 .../alpha/linux/tsunami-simple-atomic/stats.txt    | 44 +----------
 .../linux/tsunami-simple-timing-dual/config.ini    | 34 ++++++---
 .../alpha/linux/tsunami-simple-timing-dual/simerr  |  6 +-
 .../alpha/linux/tsunami-simple-timing-dual/simout  | 10 +--
 .../linux/tsunami-simple-timing-dual/stats.txt     | 62 +--------------
 .../alpha/linux/tsunami-simple-timing/config.ini   | 27 +++++--
 .../ref/alpha/linux/tsunami-simple-timing/simerr   |  5 +-
 .../ref/alpha/linux/tsunami-simple-timing/simout   | 10 +--
 .../alpha/linux/tsunami-simple-timing/stats.txt    | 44 +----------
 .../ref/alpha/eio/simple-atomic/config.ini         |  3 +
 .../ref/alpha/eio/simple-atomic/simerr             |  3 +-
 .../ref/alpha/eio/simple-atomic/simout             |  9 +--
 .../ref/alpha/eio/simple-atomic/stats.txt          |  8 +-
 .../ref/alpha/eio/simple-timing/config.ini         | 12 +--
 .../ref/alpha/eio/simple-timing/simerr             |  3 +-
 .../ref/alpha/eio/simple-timing/simout             |  9 +--
 .../ref/alpha/eio/simple-timing/stats.txt          | 35 +--------
 .../ref/alpha/eio/simple-atomic-mp/config.ini      | 39 +++++-----
 .../ref/alpha/eio/simple-atomic-mp/simerr          |  3 +-
 .../ref/alpha/eio/simple-atomic-mp/simout          |  9 +--
 .../ref/alpha/eio/simple-atomic-mp/stats.txt       | 89 +---------------------
 .../ref/alpha/eio/simple-timing-mp/config.ini      | 39 +++++-----
 .../ref/alpha/eio/simple-timing-mp/simerr          |  3 +-
 .../ref/alpha/eio/simple-timing-mp/simout          |  9 +--
 .../ref/alpha/eio/simple-timing-mp/stats.txt       | 89 +---------------------
 .../50.memtest/ref/alpha/linux/memtest/config.ini  | 27 +++----
 .../50.memtest/ref/alpha/linux/memtest/simerr      |  2 +-
 .../50.memtest/ref/alpha/linux/memtest/simout      |  9 +--
 .../50.memtest/ref/alpha/linux/memtest/stats.txt   | 87 +--------------------
 .../linux/twosys-tsunami-simple-atomic/config.ini  | 34 ++++++++-
 .../linux/twosys-tsunami-simple-atomic/simerr      |  7 +-
 .../linux/twosys-tsunami-simple-atomic/simout      | 11 +--
 .../linux/twosys-tsunami-simple-atomic/stats.txt   | 14 ++--
 104 files changed, 545 insertions(+), 1161 deletions(-)

(limited to 'tests/quick')

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 3764c941e..46ef9d2b9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 cachePorts=200
+checker=Null
 choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
 decodeWidth=8
 defer_registration=false
 dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
 fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index b502697af..0d9f81ac8 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:44
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 12474500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 93747295c..b0c4635e4 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    440                       # Nu
 global.BPredUnit.condPredicted                   1370                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         2263                       # Number of BP lookups
 global.BPredUnit.usedRAS                          304                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   7058                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199016                       # Number of bytes of host memory used
-host_seconds                                     0.90                       # Real time elapsed on the host
-host_tick_rate                               13784618                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  68343                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200684                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                              133183507                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 36                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                29                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  2287                       # Number of loads inserted to the mem dependence unit.
@@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.070730                       # ms
 system.cpu.dcache.overall_mshr_misses             188                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    174                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.170366                       # ms
 system.cpu.icache.overall_mshr_misses             307                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    307                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -405,15 +387,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.997921                       # m
 system.cpu.l2cache.overall_mshr_misses            480                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   393                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index f3b922bb8..5b4a31473 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 9a255c446..8975ff812 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:44
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 3215000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 712fc898c..93917b1eb 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   6758                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190848                       # Number of bytes of host memory used
-host_seconds                                     0.95                       # Real time elapsed on the host
-host_tick_rate                                3391912                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 122377                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192524                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                               61135620                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 0b9f96b2e..26edcc7cf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index c3d847e3f..22d348b2d 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:46
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 33777000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index f97f1c530..dc4411624 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  68165                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198212                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                              358563073                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 344098                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199968                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1795121173                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000034                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.088780                       # ms
 system.cpu.dcache.overall_mshr_misses             182                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.043492                       # ms
 system.cpu.icache.overall_mshr_misses             279                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    279                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -223,15 +205,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.997763                       # m
 system.cpu.l2cache.overall_mshr_misses            446                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   359                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 21f8bc603..9abe15dfc 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 cachePorts=200
+checker=Null
 choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
 decodeWidth=8
 defer_registration=false
 dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
 fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index e4872d461..d373e353b 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:29:52
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 7183000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 12af7d1b2..af633c5e8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    209                       # Nu
 global.BPredUnit.condPredicted                    447                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          859                       # Number of BP lookups
 global.BPredUnit.usedRAS                          165                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  31288                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198012                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                               93885607                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  22600                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199684                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                               67889683                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                  7                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   738                       # Number of loads inserted to the mem dependence unit.
@@ -109,15 +109,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.113033                       # ms
 system.cpu.dcache.overall_mshr_misses              98                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -218,15 +209,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.242303                       # ms
 system.cpu.icache.overall_mshr_misses             181                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    181                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -404,15 +386,6 @@ system.cpu.l2cache.overall_mshr_miss_rate            1                       # m
 system.cpu.l2cache.overall_mshr_misses            266                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   228                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index bbdfaa101..8ca1fff45 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 55a4a98f7..7c13e1d4c 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:24:43
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 1297500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 051f6dec4..ddfd1ad69 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 334328                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 189900                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              162370166                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 147781                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 191596                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                               73371409                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 6a2eadca9..f0bdf09de 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
index 28251ddf8..bb8489f81 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 779993228..3560f6496 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:46
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello world!
 Exiting @ tick 17374000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index af7d3609f..5c25b785f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  59950                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197352                       # Number of bytes of host memory used
+host_inst_rate                                  73131                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199016                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                              402241104                       # Simulator tick rate (ticks/s)
+host_tick_rate                              490513834                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.131171                       # ms
 system.cpu.dcache.overall_mshr_misses              93                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.063032                       # ms
 system.cpu.icache.overall_mshr_misses             163                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -222,15 +204,6 @@ system.cpu.l2cache.overall_mshr_miss_rate            1                       # m
 system.cpu.l2cache.overall_mshr_misses            245                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   207                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 83f026450..766c4f486 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -67,9 +67,12 @@ CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
 UnifiedTLB=true
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 77c8639ab..7b1955a4b 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:37:50
+M5 compiled Feb 16 2009 00:16:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:16:42
 M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello World!
 Exiting @ tick 2828000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 6c370ab2d..20921ce17 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  10079                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192068                       # Number of bytes of host memory used
-host_seconds                                     0.56                       # Real time elapsed on the host
-host_tick_rate                                5037819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  24803                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193824                       # Number of bytes of host memory used
+host_seconds                                     0.23                       # Real time elapsed on the host
+host_tick_rate                               12384497                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 9ef900f1f..d6fb3e91a 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -67,9 +67,12 @@ CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
 UnifiedTLB=true
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -99,12 +102,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -136,12 +138,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -173,12 +174,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
index 5ff857a03..eabe42249 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
@@ -1,3 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 17fb9f581..a5bd2cd4d 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:37:51
+M5 compiled Feb 16 2009 00:16:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:16:42
 M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
 Hello World!
 Exiting @ tick 32322000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index d5658e44c..de10d4a74 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 334992                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199532                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1887416058                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26568                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201268                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                              151609105                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.071081                       # ms
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    132                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -135,15 +126,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.053552                       # ms
 system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                     13                       # number of replacements
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.995402                       # m
 system.cpu.l2cache.overall_mshr_misses            433                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 7ebff17bf..970388ae5 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index 946edd9f0..eefaf1737 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:55:47
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:17:34
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 8a19f5ea4..b09b910ba 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 371297                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191740                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              185101425                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  25851                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193720                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                               13060676                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index c8a9fb583..f68b9582f 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 92edc3116..fcae28521 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:41:19
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:17:34
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 29031000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 7d5ee5db9..cf7518d98 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 419811                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199192                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2213741040                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  21374                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201092                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
+host_tick_rate                              116036277                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.107991                       # ms
 system.cpu.dcache.overall_mshr_misses             150                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.047734                       # ms
 system.cpu.icache.overall_mshr_misses             257                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -207,15 +189,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.992347                       # m
 system.cpu.l2cache.overall_mshr_misses            389                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   293                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 140ac8ef9..1a9a034e8 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
index 72ba90ece..94d399eab 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 66f32751d..5d849e6d3 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 26 2008 18:29:56
-M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
-M5 commit date Fri Dec 26 18:25:21 2008 -0800
-M5 started Dec 26 2008 18:30:07
-M5 executing on fajita
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:19:16
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 2ee3e5703..a5ec37276 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   5132                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192872                       # Number of bytes of host memory used
-host_seconds                                     1.85                       # Real time elapsed on the host
-host_tick_rate                                2983162                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  51320                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193224                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
+host_tick_rate                               29796099                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9484                       # Number of instructions simulated
 sim_seconds                                  0.000006                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 6b3961ac8..d1edd6c59 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
index 72ba90ece..94d399eab 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index e9fb59225..23d83ecb3 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 26 2008 18:29:56
-M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
-M5 commit date Fri Dec 26 18:25:21 2008 -0800
-M5 started Dec 26 2008 19:57:21
-M5 executing on fajita
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:19:16
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index 4bf18211b..58aaf6112 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 494241                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200332                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1743803782                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  63293                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200624                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
+host_tick_rate                              225441997                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9484                       # Number of instructions simulated
 sim_seconds                                  0.000034                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.076497                       # ms
 system.cpu.dcache.overall_mshr_misses             152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    133                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.020731                       # ms
 system.cpu.icache.overall_mshr_misses             228                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -207,15 +189,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.997230                       # m
 system.cpu.l2cache.overall_mshr_misses            360                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   262                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 62ebb142a..9c8da927d 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 cachePorts=200
+checker=Null
 choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
 decodeWidth=8
 defer_registration=false
 dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
 fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
index fc5805f9e..eabe42249 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 958798ce3..73f0d5969 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,14 +5,15 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:28:54
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 Hello world!
 Hello world!
 Exiting @ tick 14251500 because target called exit()
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index ecc7ae363..c9242b886 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   1595                       # Nu
 global.BPredUnit.condPredicted                   3153                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         5548                       # Number of BP lookups
 global.BPredUnit.usedRAS                          681                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  85524                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199540                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-host_tick_rate                               95322021                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  67823                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201212                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
+host_tick_rate                               75589135                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 22                       # Number of conflicting loads.
 memdepunit.memDep.conflictingLoads                 58                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 4                       # Number of conflicting stores.
@@ -195,15 +195,6 @@ system.cpu.dcache.overall_mshr_uncacheable_latency_1            0
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.replacements_0                    0                       # number of replacements
 system.cpu.dcache.replacements_1                    0                       # number of replacements
@@ -369,15 +360,6 @@ system.cpu.icache.overall_mshr_uncacheable_latency_1            0
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      6                       # number of replacements
 system.cpu.icache.replacements_0                    6                       # number of replacements
 system.cpu.icache.replacements_1                    0                       # number of replacements
@@ -707,15 +689,6 @@ system.cpu.l2cache.overall_mshr_uncacheable_latency_1            0
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.replacements_0                   0                       # number of replacements
 system.cpu.l2cache.replacements_1                   0                       # number of replacements
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index b0fb0c129..102ce19a3 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -22,6 +22,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 cachePorts=200
+checker=Null
 choiceCtrBits=2
 choicePredictorSize=8192
 clock=500
@@ -36,6 +37,8 @@ decodeToRenameDelay=1
 decodeWidth=8
 defer_registration=false
 dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
 fetchTrapLatency=1
@@ -107,12 +110,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -281,12 +283,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -318,12 +319,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 1f6eb4b07..d0efe85b3 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:43:55
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:17:34
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index d80957aed..0584aa2e2 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   2923                       # Nu
 global.BPredUnit.condPredicted                  11413                       # Number of conditional branches predicted
 global.BPredUnit.lookups                        11413                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  55497                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199732                       # Number of bytes of host memory used
-host_seconds                                     0.26                       # Real time elapsed on the host
-host_tick_rate                              106451563                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  30716                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201632                       # Number of bytes of host memory used
+host_seconds                                     0.47                       # Real time elapsed on the host
+host_tick_rate                               58973694                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 26                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  4960                       # Number of loads inserted to the mem dependence unit.
@@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.031593                       # ms
 system.cpu.dcache.overall_mshr_misses             167                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    148                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -205,15 +196,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.048804                       # ms
 system.cpu.icache.overall_mshr_misses             359                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      1                       # number of replacements
 system.cpu.icache.sampled_refs                    358                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -388,15 +370,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.992110                       # m
 system.cpu.l2cache.overall_mshr_misses            503                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   400                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index bd75b6dd2..c81ee3264 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index 7103e96c6..cb610b0c6 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:43:56
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:17:34
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index fa5cbc97a..d9897842c 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 641188                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191520                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              319099476                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  61727                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193528                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
+host_tick_rate                               30956425                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000008                       # Number of seconds simulated
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 35e384fb9..8777df95f 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
index ee69ae99e..eabe42249 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 796520389..65fc22a94 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov  5 2008 22:43:56
+M5 compiled Feb 16 2009 00:17:12
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:17:34
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index f45ffd986..323f23c0d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 494848                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199068                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                             1383502218                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  71328                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200972                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                              200611199                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000043                       # Number of seconds simulated
@@ -66,15 +66,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.042257                       # ms
 system.cpu.dcache.overall_mshr_misses             155                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -128,15 +119,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.018396                       # ms
 system.cpu.icache.overall_mshr_misses             280                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.995215                       # m
 system.cpu.l2cache.overall_mshr_misses            416                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   314                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 9d8e5c8ed..56dec3815 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -36,6 +36,7 @@ side_b=system.membus.port[0]
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
@@ -74,12 +75,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -111,12 +111,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -146,6 +145,7 @@ type=ExeTracer
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
@@ -184,12 +184,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -221,12 +220,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -264,6 +262,7 @@ image=system.disk0.image
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -283,6 +282,7 @@ image=system.disk2.image
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -317,12 +317,11 @@ latency=50000
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -350,12 +349,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -485,16 +483,22 @@ pio=system.iobus.port[1]
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -863,16 +867,22 @@ pio=system.iobus.port[22]
 [system.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index d445cb942..5a1d0bef0 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -1,5 +1,7 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: 97861500: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/8f7d2563
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 2e7c9e61b..8c40366bc 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:48:26
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:50
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 55ea1f24a..8ed468432 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1560779                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292076                       # Number of bytes of host memory used
-host_seconds                                    40.46                       # Real time elapsed on the host
-host_tick_rate                            46222973494                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2804596                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292704                       # Number of bytes of host memory used
+host_seconds                                    22.52                       # Real time elapsed on the host
+host_tick_rate                            83058483755                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -60,15 +60,6 @@ system.cpu0.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.dcache.replacements               1978962                       # number of replacements
 system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -128,15 +119,6 @@ system.cpu0.icache.overall_mshr_miss_rate            0                       # m
 system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.icache.replacements                884404                       # number of replacements
 system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -294,15 +276,6 @@ system.cpu1.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.dcache.replacements                 62338                       # number of replacements
 system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -362,15 +335,6 @@ system.cpu1.icache.overall_mshr_miss_rate            0                       # m
 system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.icache.replacements                103091                       # number of replacements
 system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -513,15 +477,6 @@ system.iocache.overall_mshr_miss_rate               0                       # ms
 system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.iocache.replacements                     41695                       # number of replacements
 system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -577,15 +532,6 @@ system.l2c.overall_mshr_miss_rate                   0                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                       1056803                       # number of replacements
 system.l2c.sampled_refs                       1091452                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index a6db3884d..15e3ec649 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -36,6 +36,7 @@ side_b=system.membus.port[0]
 [system.cpu]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
@@ -74,12 +75,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -111,12 +111,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -154,6 +153,7 @@ image=system.disk0.image
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -173,6 +173,7 @@ image=system.disk2.image
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -207,12 +208,11 @@ latency=50000
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -240,12 +240,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -375,16 +374,22 @@ pio=system.iobus.port[1]
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -753,16 +758,22 @@ pio=system.iobus.port[22]
 [system.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 1a557daf8..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
@@ -1,4 +1,5 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 2ea90534e..778e7a3b4 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:47:54
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:52
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 19b0c43d9..749efa0bc 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1610025                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 290828                       # Number of bytes of host memory used
-host_seconds                                    37.29                       # Real time elapsed on the host
-host_tick_rate                            49056237387                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2844723                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 291452                       # Number of bytes of host memory used
+host_seconds                                    21.11                       # Real time elapsed on the host
+host_tick_rate                            86676065750                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -60,15 +60,6 @@ system.cpu.dcache.overall_mshr_miss_rate            0                       # ms
 system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                2042700                       # number of replacements
 system.cpu.dcache.sampled_refs                2043212                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -128,15 +119,6 @@ system.cpu.icache.overall_mshr_miss_rate            0                       # ms
 system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                 919594                       # number of replacements
 system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -291,15 +273,6 @@ system.iocache.overall_mshr_miss_rate               0                       # ms
 system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.iocache.replacements                     41686                       # number of replacements
 system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -355,15 +328,6 @@ system.l2c.overall_mshr_miss_rate                   0                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                       1050724                       # number of replacements
 system.l2c.sampled_refs                       1081067                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index de9bfc9e4..f8e47e1b8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -36,6 +36,7 @@ side_b=system.membus.port[0]
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
@@ -71,12 +72,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -108,12 +108,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -143,6 +142,7 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
@@ -178,12 +178,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -215,12 +214,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -258,6 +256,7 @@ image=system.disk0.image
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -277,6 +276,7 @@ image=system.disk2.image
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -311,12 +311,11 @@ latency=50000
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -344,12 +343,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -479,16 +477,22 @@ pio=system.iobus.port[1]
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -857,16 +861,22 @@ pio=system.iobus.port[22]
 [system.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index dad1cad88..e077a7fd9 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -1,5 +1,7 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: 591544000: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/8f7d2563
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 9f8bf8070..6b56db972 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:47:52
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:51
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1972135461000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 2f2449fdc..4a6754053 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 741695                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289172                       # Number of bytes of host memory used
-host_seconds                                    80.11                       # Real time elapsed on the host
-host_tick_rate                            24616375840                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1382701                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 289788                       # Number of bytes of host memory used
+host_seconds                                    42.97                       # Real time elapsed on the host
+host_tick_rate                            45890646030                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59420593                       # Number of instructions simulated
 sim_seconds                                  1.972135                       # Number of seconds simulated
@@ -88,15 +88,6 @@ system.cpu0.dcache.overall_mshr_miss_rate     0.098910                       # m
 system.cpu0.dcache.overall_mshr_misses        1417958                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency   2124474000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.dcache.replacements               1338610                       # number of replacements
 system.cpu0.dcache.sampled_refs               1339122                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -162,15 +153,6 @@ system.cpu0.icache.overall_mshr_miss_rate     0.016917                       # m
 system.cpu0.icache.overall_mshr_misses         916324                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.icache.replacements                915684                       # number of replacements
 system.cpu0.icache.sampled_refs                916195                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -356,15 +338,6 @@ system.cpu1.dcache.overall_mshr_miss_rate     0.037169                       # m
 system.cpu1.dcache.overall_mshr_misses          62092                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency    315545000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.dcache.replacements                 53724                       # number of replacements
 system.cpu1.dcache.sampled_refs                 54120                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -430,15 +403,6 @@ system.cpu1.icache.overall_mshr_miss_rate     0.016597                       # m
 system.cpu1.icache.overall_mshr_misses          87436                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.icache.replacements                 86896                       # number of replacements
 system.cpu1.icache.sampled_refs                 87408                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -597,15 +561,6 @@ system.iocache.overall_mshr_miss_rate               1                       # ms
 system.iocache.overall_mshr_misses              41730                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.iocache.replacements                     41698                       # number of replacements
 system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -684,15 +639,6 @@ system.l2c.overall_mshr_miss_rate            0.256233                       # ms
 system.l2c.overall_mshr_misses                 614222                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   2197317000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                        399005                       # number of replacements
 system.l2c.sampled_refs                        430732                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 3e8e04375..468bf0248 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -36,6 +36,7 @@ side_b=system.membus.port[0]
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts itb tracer
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
@@ -71,12 +72,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -108,12 +108,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -151,6 +150,7 @@ image=system.disk0.image
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -170,6 +170,7 @@ image=system.disk2.image
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -204,12 +205,11 @@ latency=50000
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -237,12 +237,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -372,16 +371,22 @@ pio=system.iobus.port[1]
 [system.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -750,16 +755,22 @@ pio=system.iobus.port[22]
 [system.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 1a557daf8..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -1,4 +1,5 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index b196d52a3..ba86a45b9 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:47:59
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:52
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1930164593000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 76e60eed0..cbf231e85 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 715830                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 287924                       # Number of bytes of host memory used
-host_seconds                                    78.52                       # Real time elapsed on the host
-host_tick_rate                            24582295405                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1953289                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 288556                       # Number of bytes of host memory used
+host_seconds                                    28.78                       # Real time elapsed on the host
+host_tick_rate                            67077404616                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56205703                       # Number of instructions simulated
 sim_seconds                                  1.930165                       # Number of seconds simulated
@@ -88,15 +88,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.097749                       # ms
 system.cpu.dcache.overall_mshr_misses         1471029                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency   2064006500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                1391606                       # number of replacements
 system.cpu.dcache.sampled_refs                1392118                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -162,15 +153,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.016562                       # ms
 system.cpu.icache.overall_mshr_misses          931101                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                 930429                       # number of replacements
 system.cpu.icache.sampled_refs                 930940                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -337,15 +319,6 @@ system.iocache.overall_mshr_miss_rate               1                       # ms
 system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -423,15 +396,6 @@ system.l2c.overall_mshr_miss_rate            0.263528                       # ms
 system.l2c.overall_mshr_misses                 612229                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   1857972500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                        394928                       # number of replacements
 system.l2c.sampled_refs                        425903                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 836233457..014feb13e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index a1d152694..c0312fe31 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 539afef68..103b40a61 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:27:20
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 51d5de7dc..1e8dfa007 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4911987                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 189996                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                             2448419888                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4171159                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 191588                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                             2080999983                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 0f1cefdac..84839b10d 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -117,12 +118,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=10
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
index a1d152694..c0312fe31 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
@@ -1,4 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
index 337a3a052..d93e92292 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:29:51
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 041421492..66e101984 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 883179                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197372                       # Number of bytes of host memory used
-host_seconds                                     0.57                       # Real time elapsed on the host
-host_tick_rate                             1301859777                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1619389                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199040                       # Number of bytes of host memory used
+host_seconds                                     0.31                       # Real time elapsed on the host
+host_tick_rate                             2386410783                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000737                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate     0.003463                       # ms
 system.cpu.dcache.overall_mshr_misses             626                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    454                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate     0.000806                       # ms
 system.cpu.icache.overall_mshr_misses             403                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    403                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -222,15 +204,6 @@ system.cpu.l2cache.overall_mshr_miss_rate            1                       # m
 system.cpu.l2cache.overall_mshr_misses            857                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   546                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 78394da28..af926f81c 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu0.dtb
 function_trace=false
 function_trace_start=0
@@ -46,12 +49,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -83,12 +85,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -125,9 +126,12 @@ system=system
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
@@ -159,12 +163,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -196,12 +199,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -238,9 +240,12 @@ system=system
 [system.cpu2]
 type=AtomicSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=2
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu2.dtb
 function_trace=false
 function_trace_start=0
@@ -272,12 +277,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -309,12 +313,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -351,9 +354,12 @@ system=system
 [system.cpu3]
 type=AtomicSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=3
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu3.dtb
 function_trace=false
 function_trace_start=0
@@ -385,12 +391,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -422,12 +427,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -472,12 +476,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 496a7244f..75c83d350 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -1,5 +1,6 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
 
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index b1dd747a5..0c841053d 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:45
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:11
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 12655b8fd..aecd60ac7 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2958551                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1121980                       # Number of bytes of host memory used
-host_seconds                                     0.68                       # Real time elapsed on the host
-host_tick_rate                              369689554                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4658528                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1123612                       # Number of bytes of host memory used
+host_seconds                                     0.43                       # Real time elapsed on the host
+host_tick_rate                              582033733                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -52,15 +52,6 @@ system.cpu0.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.dcache.replacements                    61                       # number of replacements
 system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -120,15 +111,6 @@ system.cpu0.icache.overall_mshr_miss_rate            0                       # m
 system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.icache.replacements                   152                       # number of replacements
 system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -190,15 +172,6 @@ system.cpu1.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.dcache.replacements                    61                       # number of replacements
 system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -258,15 +231,6 @@ system.cpu1.icache.overall_mshr_miss_rate            0                       # m
 system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.icache.replacements                   152                       # number of replacements
 system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -328,15 +292,6 @@ system.cpu2.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu2.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu2.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu2.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu2.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu2.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu2.dcache.replacements                    61                       # number of replacements
 system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -396,15 +351,6 @@ system.cpu2.icache.overall_mshr_miss_rate            0                       # m
 system.cpu2.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu2.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu2.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu2.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu2.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu2.icache.replacements                   152                       # number of replacements
 system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -466,15 +412,6 @@ system.cpu3.dcache.overall_mshr_miss_rate            0                       # m
 system.cpu3.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu3.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu3.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu3.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu3.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu3.dcache.replacements                    61                       # number of replacements
 system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -534,15 +471,6 @@ system.cpu3.icache.overall_mshr_miss_rate            0                       # m
 system.cpu3.icache.overall_mshr_misses              0                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu3.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu3.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu3.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu3.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu3.icache.replacements                   152                       # number of replacements
 system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -608,15 +536,6 @@ system.l2c.overall_mshr_miss_rate                   0                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                             0                       # number of replacements
 system.l2c.sampled_refs                          2300                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 0077a0004..2d269877c 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -12,9 +12,12 @@ physmem=system.physmem
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu0.dtb
 function_trace=false
 function_trace_start=0
@@ -43,12 +46,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -80,12 +82,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -122,9 +123,12 @@ system=system
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
@@ -153,12 +157,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -190,12 +193,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -232,9 +234,12 @@ system=system
 [system.cpu2]
 type=TimingSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=2
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu2.dtb
 function_trace=false
 function_trace_start=0
@@ -263,12 +268,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -300,12 +304,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -342,9 +345,12 @@ system=system
 [system.cpu3]
 type=TimingSimpleCPU
 children=dcache dtb icache itb tracer workload
+checker=Null
 clock=500
 cpu_id=3
 defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
 dtb=system.cpu3.dtb
 function_trace=false
 function_trace_start=0
@@ -373,12 +379,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -410,12 +415,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -460,12 +464,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 496a7244f..75c83d350 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -1,5 +1,6 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
 
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index edbace7b2..edab14950 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:30:50
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:12
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 5dc3a25b6..1fb750134 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1370296                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204468                       # Number of bytes of host memory used
-host_seconds                                     1.46                       # Real time elapsed on the host
-host_tick_rate                              505820394                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1521087                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206108                       # Number of bytes of host memory used
+host_seconds                                     1.32                       # Real time elapsed on the host
+host_tick_rate                              561475161                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1999941                       # Number of instructions simulated
 sim_seconds                                  0.000738                       # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu0.dcache.overall_mshr_miss_rate     0.003513                       # m
 system.cpu0.dcache.overall_mshr_misses            635                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.dcache.replacements                    61                       # number of replacements
 system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -138,15 +129,6 @@ system.cpu0.icache.overall_mshr_miss_rate     0.000926                       # m
 system.cpu0.icache.overall_mshr_misses            463                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.icache.replacements                   152                       # number of replacements
 system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -220,15 +202,6 @@ system.cpu1.dcache.overall_mshr_miss_rate     0.003513                       # m
 system.cpu1.dcache.overall_mshr_misses            635                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.dcache.replacements                    61                       # number of replacements
 system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -294,15 +267,6 @@ system.cpu1.icache.overall_mshr_miss_rate     0.000926                       # m
 system.cpu1.icache.overall_mshr_misses            463                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.icache.replacements                   152                       # number of replacements
 system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -376,15 +340,6 @@ system.cpu2.dcache.overall_mshr_miss_rate     0.003513                       # m
 system.cpu2.dcache.overall_mshr_misses            635                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu2.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu2.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu2.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu2.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu2.dcache.replacements                    61                       # number of replacements
 system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -450,15 +405,6 @@ system.cpu2.icache.overall_mshr_miss_rate     0.000926                       # m
 system.cpu2.icache.overall_mshr_misses            463                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu2.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu2.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu2.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu2.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu2.icache.replacements                   152                       # number of replacements
 system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -532,15 +478,6 @@ system.cpu3.dcache.overall_mshr_miss_rate     0.003513                       # m
 system.cpu3.dcache.overall_mshr_misses            635                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu3.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu3.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu3.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu3.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu3.dcache.replacements                    61                       # number of replacements
 system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -606,15 +543,6 @@ system.cpu3.icache.overall_mshr_miss_rate     0.000926                       # m
 system.cpu3.icache.overall_mshr_misses            463                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu3.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu3.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu3.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu3.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu3.icache.replacements                   152                       # number of replacements
 system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
 system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
@@ -698,15 +626,6 @@ system.l2c.overall_mshr_miss_rate            0.925486                       # ms
 system.l2c.overall_mshr_misses                   3428                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                             0                       # number of replacements
 system.l2c.sampled_refs                          2300                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 3ae48f3b4..f9dfac7de 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -36,12 +36,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -85,12 +84,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -134,12 +132,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -183,12 +180,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -232,12 +228,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -281,12 +276,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -330,12 +324,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -379,12 +372,11 @@ latency=1000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
@@ -422,12 +414,11 @@ latency=10000
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
-prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
 prefetch_past_page=false
 prefetch_policy=none
 prefetch_serial_squash=false
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
index 507652626..b09f497b8 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
@@ -71,4 +71,4 @@ system.cpu5: completed 90000 read accesses @243633950
 system.cpu4: completed 90000 read accesses @243710816
 system.cpu2: completed 90000 read accesses @243974160
 system.cpu6: completed 100000 read accesses @268915439
-warn: be nice to actually delete the event here
+hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index a9b5dbd1a..9d66255a0 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -5,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:21:45
+M5 compiled Feb 16 2009 00:22:05
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:22:11
 M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 268915439 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 07a437af0..7f0400045 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 324480                       # Number of bytes of host memory used
-host_seconds                                   257.27                       # Real time elapsed on the host
-host_tick_rate                                1045249                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 326140                       # Number of bytes of host memory used
+host_seconds                                   207.97                       # Real time elapsed on the host
+host_tick_rate                                1293031                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000269                       # Number of seconds simulated
 sim_ticks                                   268915439                       # Number of ticks simulated
@@ -66,15 +66,6 @@ system.cpu0.l1c.overall_mshr_miss_rate       0.875088                       # ms
 system.cpu0.l1c.overall_mshr_misses             60767                       # number of overall MSHR misses
 system.cpu0.l1c.overall_mshr_uncacheable_latency   1353267171                       # number of overall MSHR uncacheable cycles
 system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu0.l1c.replacements                    28158                       # number of replacements
 system.cpu0.l1c.sampled_refs                    28502                       # Sample count of references to valid blocks.
 system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -145,15 +136,6 @@ system.cpu1.l1c.overall_mshr_miss_rate       0.876074                       # ms
 system.cpu1.l1c.overall_mshr_misses             60450                       # number of overall MSHR misses
 system.cpu1.l1c.overall_mshr_uncacheable_latency   1346826370                       # number of overall MSHR uncacheable cycles
 system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu1.l1c.replacements                    27563                       # number of replacements
 system.cpu1.l1c.sampled_refs                    27921                       # Sample count of references to valid blocks.
 system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -224,15 +206,6 @@ system.cpu2.l1c.overall_mshr_miss_rate       0.877723                       # ms
 system.cpu2.l1c.overall_mshr_misses             60562                       # number of overall MSHR misses
 system.cpu2.l1c.overall_mshr_uncacheable_latency   1332423623                       # number of overall MSHR uncacheable cycles
 system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu2.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu2.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu2.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu2.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu2.l1c.replacements                    27725                       # number of replacements
 system.cpu2.l1c.sampled_refs                    28081                       # Sample count of references to valid blocks.
 system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -303,15 +276,6 @@ system.cpu3.l1c.overall_mshr_miss_rate       0.876426                       # ms
 system.cpu3.l1c.overall_mshr_misses             60533                       # number of overall MSHR misses
 system.cpu3.l1c.overall_mshr_uncacheable_latency   1344489859                       # number of overall MSHR uncacheable cycles
 system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu3.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu3.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu3.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu3.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu3.l1c.replacements                    27562                       # number of replacements
 system.cpu3.l1c.sampled_refs                    27915                       # Sample count of references to valid blocks.
 system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -382,15 +346,6 @@ system.cpu4.l1c.overall_mshr_miss_rate       0.877493                       # ms
 system.cpu4.l1c.overall_mshr_misses             60418                       # number of overall MSHR misses
 system.cpu4.l1c.overall_mshr_uncacheable_latency   1350722770                       # number of overall MSHR uncacheable cycles
 system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu4.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu4.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu4.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu4.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu4.l1c.replacements                    27721                       # number of replacements
 system.cpu4.l1c.sampled_refs                    28078                       # Sample count of references to valid blocks.
 system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -461,15 +416,6 @@ system.cpu5.l1c.overall_mshr_miss_rate       0.878516                       # ms
 system.cpu5.l1c.overall_mshr_misses             60470                       # number of overall MSHR misses
 system.cpu5.l1c.overall_mshr_uncacheable_latency   1358757678                       # number of overall MSHR uncacheable cycles
 system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu5.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu5.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu5.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu5.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu5.l1c.replacements                    27632                       # number of replacements
 system.cpu5.l1c.sampled_refs                    27965                       # Sample count of references to valid blocks.
 system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -540,15 +486,6 @@ system.cpu6.l1c.overall_mshr_miss_rate       0.878966                       # ms
 system.cpu6.l1c.overall_mshr_misses             60973                       # number of overall MSHR misses
 system.cpu6.l1c.overall_mshr_uncacheable_latency   1360988652                       # number of overall MSHR uncacheable cycles
 system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu6.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu6.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu6.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu6.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu6.l1c.replacements                    28139                       # number of replacements
 system.cpu6.l1c.sampled_refs                    28470                       # Sample count of references to valid blocks.
 system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -619,15 +556,6 @@ system.cpu7.l1c.overall_mshr_miss_rate       0.876946                       # ms
 system.cpu7.l1c.overall_mshr_misses             60440                       # number of overall MSHR misses
 system.cpu7.l1c.overall_mshr_uncacheable_latency   1352128927                       # number of overall MSHR uncacheable cycles
 system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu7.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu7.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu7.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu7.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu7.l1c.replacements                    27627                       # number of replacements
 system.cpu7.l1c.sampled_refs                    27994                       # Sample count of references to valid blocks.
 system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
@@ -711,15 +639,6 @@ system.l2c.overall_mshr_miss_rate            0.570509                       # ms
 system.l2c.overall_mshr_misses                 121555                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   4880792865                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.l2c.replacements                         73303                       # number of replacements
 system.l2c.sampled_refs                         73894                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 3bf761d34..a2a52df64 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS
+readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -36,6 +36,7 @@ side_b=drivesys.membus.port[0]
 [drivesys.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts itb tracer
+checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
@@ -88,6 +89,7 @@ image=drivesys.disk0.image
 type=CowDiskImage
 children=child
 child=drivesys.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -107,6 +109,7 @@ image=drivesys.disk2.image
 type=CowDiskImage
 children=child
 child=drivesys.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -215,16 +218,22 @@ pio=drivesys.iobus.port[1]
 [drivesys.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -594,16 +603,22 @@ pio=drivesys.iobus.port[22]
 [drivesys.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -703,7 +718,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS
+readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -725,6 +740,7 @@ side_b=testsys.membus.port[0]
 [testsys.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts itb tracer
+checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
@@ -777,6 +793,7 @@ image=testsys.disk0.image
 type=CowDiskImage
 children=child
 child=testsys.disk0.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -796,6 +813,7 @@ image=testsys.disk2.image
 type=CowDiskImage
 children=child
 child=testsys.disk2.image.child
+image_file=
 read_only=false
 table_size=65536
 
@@ -904,16 +922,22 @@ pio=testsys.iobus.port[1]
 [testsys.tsunami.ethernet]
 type=NSGigE
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=256
 BAR1=0
+BAR1LegacyIO=false
 BAR1Size=4096
 BAR2=0
+BAR2LegacyIO=false
 BAR2Size=0
 BAR3=0
+BAR3LegacyIO=false
 BAR3Size=0
 BAR4=0
+BAR4LegacyIO=false
 BAR4Size=0
 BAR5=0
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
@@ -1283,16 +1307,22 @@ pio=testsys.iobus.port[22]
 [testsys.tsunami.ide]
 type=IdeController
 BAR0=1
+BAR0LegacyIO=false
 BAR0Size=8
 BAR1=1
+BAR1LegacyIO=false
 BAR1Size=4
 BAR2=1
+BAR2LegacyIO=false
 BAR2Size=8
 BAR3=1
+BAR3LegacyIO=false
 BAR3Size=4
 BAR4=1
+BAR4LegacyIO=false
 BAR4Size=16
 BAR5=1
+BAR5LegacyIO=false
 BAR5Size=0
 BIST=0
 CacheLineSize=0
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index 73103c03f..c18ca3505 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
@@ -1,6 +1,7 @@
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
 warn: Sockets disabled, not accepting terminal connections
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
+For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
 warn: Obsolete M5 ivlb instruction encountered.
-warn: be nice to actually delete the event here
+For more information see: http://www.m5sim.org/warn/fcbd217d
+hack: be nice to actually delete the event here
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 361a090ba..70f17d877 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -5,12 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec 14 2008 21:47:07
-M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
-M5 commit date Sun Dec 14 21:45:15 2008 -0800
-M5 started Dec 14 2008 21:48:20
-M5 executing on tater
+M5 compiled Feb 16 2009 00:15:24
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 00:15:51
+M5 executing on zizzer
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4300236804024 because checkpoint
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 80d312c00..267fa9175 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              184651715                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478008                       # Number of bytes of host memory used
-host_seconds                                     1.48                       # Real time elapsed on the host
-host_tick_rate                           135077074315                       # Simulator tick rate (ticks/s)
+host_inst_rate                              151383583                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 478624                       # Number of bytes of host memory used
+host_seconds                                     1.81                       # Real time elapsed on the host
+host_tick_rate                           110738300112                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           161951915284                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478008                       # Number of bytes of host memory used
+host_inst_rate                           133483805176                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 478624                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              438603795                       # Simulator tick rate (ticks/s)
+host_tick_rate                              360871442                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
-- 
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