From 076d04a653f5a4252c6c16e010ad0d7bf36c1674 Mon Sep 17 00:00:00 2001
From: Akash Bagdia <akash.bagdia@arm.com>
Date: Thu, 27 Jun 2013 05:49:49 -0400
Subject: config: Add a system clock command-line option

This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
---
 tests/configs/base_config.py                  | 1 +
 tests/configs/inorder-timing.py               | 1 +
 tests/configs/memtest-ruby.py                 | 1 +
 tests/configs/memtest.py                      | 1 +
 tests/configs/o3-timing-checker.py            | 1 +
 tests/configs/o3-timing-mp-ruby.py            | 1 +
 tests/configs/o3-timing-mp.py                 | 1 +
 tests/configs/o3-timing-ruby.py               | 1 +
 tests/configs/o3-timing.py                    | 1 +
 tests/configs/rubytest-ruby.py                | 1 +
 tests/configs/simple-atomic-dummychecker.py   | 1 +
 tests/configs/simple-atomic-mp-ruby.py        | 1 +
 tests/configs/simple-atomic-mp.py             | 2 +-
 tests/configs/simple-atomic.py                | 1 +
 tests/configs/simple-timing-mp-ruby.py        | 1 +
 tests/configs/simple-timing-mp.py             | 1 +
 tests/configs/simple-timing-ruby.py           | 1 +
 tests/configs/simple-timing.py                | 1 +
 tests/configs/tgen-simple-dram.py             | 1 +
 tests/configs/tgen-simple-mem.py              | 1 +
 tests/configs/twosys-tsunami-simple-atomic.py | 2 ++
 21 files changed, 22 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 60ba31665..a4b3969ef 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -131,6 +131,7 @@ class BaseSystem(object):
         Arguments:
           system -- System to initialize.
         """
+        system.clock = '1GHz'
         system.cpu = self.create_cpus()
 
         if _have_kvm_support and \
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index b19014328..30e12f777 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -42,6 +42,7 @@ system = System(cpu = cpu,
                 physmem = DDR3_1600_x64(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index a252bc881..dbd1082d1 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -81,6 +81,7 @@ system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
                 physmem = SimpleMemory(null = True),
                 funcbus = NoncoherentBus())
+system.clock = options.sys_clock
 
 Ruby.create_system(options, system)
 
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 379b1e421..efaae6133 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -40,6 +40,7 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
                 membus = CoherentBus(width=16))
+system.clock = '1GHz'
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 84fcb0f83..14948fc87 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -55,6 +55,7 @@ system = System(cpu = cpu,
                 physmem = DDR3_1600_x64(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 cpu.connectAllPorts(system.membus)
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 126e71ed5..0060689b8 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -40,6 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 # system simulated
 system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 
 for cpu in cpus:
     # create the interrupt controller
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index b7401f629..9b4f362e7 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -39,6 +39,7 @@ system = System(cpu = cpus,
                 physmem = DDR3_1600_x64(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 26dbb000b..22e1047a3 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -42,6 +42,7 @@ system = System(cpu = cpu,
                 physmem = ruby_memory,
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 system.physmem.port = system.membus.master
 # create the interrupt controller
 cpu.createInterruptController()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index a370beef4..2be0556a6 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -44,6 +44,7 @@ system = System(cpu = cpu,
                 physmem = DDR3_1600_x64(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 861205acc..328337190 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -78,6 +78,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
                     wakeup_frequency = 10, num_cpus = options.num_cpus)
 
 system = System(tester = tester, physmem = SimpleMemory(null = True))
+system.clock = options.sys_clock
 
 Ruby.create_system(options, system)
 
diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py
index 5192afb1c..d28501403 100644
--- a/tests/configs/simple-atomic-dummychecker.py
+++ b/tests/configs/simple-atomic-dummychecker.py
@@ -41,6 +41,7 @@ from m5.objects import *
 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = SimpleMemory(),
                 membus = CoherentBus())
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 system.cpu.addCheckerCpu()
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 9cb3f9eb4..12c26d97b 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -39,6 +39,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
 system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system.clock = '1GHz'
 
 # add L1 caches
 for cpu in cpus:
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 0324bcc04..d43371eb5 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -38,7 +38,7 @@ cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 system = System(cpu = cpus,
                 physmem = SimpleMemory(range = AddrRange('1024MB')),
                 membus = CoherentBus())
-
+system.clock = '1GHz'
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 3b81d9769..b9baba164 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -32,6 +32,7 @@ from m5.objects import *
 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = SimpleMemory(),
                 membus = CoherentBus())
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 6e3489fa8..2fa314d09 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -72,6 +72,7 @@ options.num_cpus = nb_cores
 
 # system simulated
 system = System(cpu = cpus, physmem = SimpleMemory())
+system.clock = options.sys_clock
 
 Ruby.create_system(options, system)
 
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index aad15a2ac..1acfacbdf 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -36,6 +36,7 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
+system.clock = '1GHz'
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 41b4fdb1f..9057475a5 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -68,6 +68,7 @@ options.num_cpus = 1
 
 cpu = TimingSimpleCPU(cpu_id=0)
 system = System(cpu = cpu, physmem = SimpleMemory(null = True))
+system.clock = options.sys_clock
 
 Ruby.create_system(options, system)
 
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index b366f01e5..046ee96dd 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,6 +39,7 @@ system = System(cpu = cpu,
                 physmem = SimpleMemory(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
+system.clock = '1GHz'
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index b57817c95..a79b65d43 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
                 membus = NoncoherentBus(width = 16))
+system.clock = '1GHz'
 
 # add a communication monitor
 system.monitor = CommMonitor()
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index 200834ec3..b93165f50 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
 # system simulated
 system = System(cpu = cpu, physmem = SimpleMemory(),
                 membus = NoncoherentBus(width = 16))
+system.clock = '1GHz'
 
 # add a communication monitor, and also trace all the packets
 system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 484236fae..8025b4e7b 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -34,6 +34,7 @@ from Benchmarks import *
 
 test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
                                  SysConfig('netperf-stream-client.rcS'))
+test_sys.clock = '1GHz'
 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
 # create the interrupt controller
 test_sys.cpu.createInterruptController()
@@ -48,6 +49,7 @@ test_sys.iobridge.master = test_sys.membus.slave
 
 drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
                                  SysConfig('netperf-server.rcS'))
+drive_sys.clock = '1GHz'
 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
 # create the interrupt controller
 drive_sys.cpu.createInterruptController()
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