From 05c487ef3ce6eb015bc8716df7e9caeedfe520da Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 17 Oct 2006 21:15:11 -0700 Subject: Enable MP systems via cmd-line flag in fs.py. configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now). --HG-- extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf --- tests/configs/tsunami-simple-atomic-dual.py | 3 --- tests/configs/tsunami-simple-timing-dual.py | 3 --- 2 files changed, 6 deletions(-) (limited to 'tests') diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index f798213db..1e6c10243 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,9 +31,6 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig -AlphaConsole.cpu = Parent.cpu[0] -IntrControl.cpu = Parent.cpu[0] - cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpus diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index bf94214fd..516495d18 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,9 +31,6 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig -AlphaConsole.cpu = Parent.cpu[0] -IntrControl.cpu = Parent.cpu[0] - cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus -- cgit v1.2.3 From 780aa0a0ebb765781a31d0fb58257b1efb1f324a Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 19 Oct 2006 21:26:46 -0400 Subject: Fix corner case on assertion. I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode. src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses --HG-- extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f --- tests/configs/memtest.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 116e71af6..2b990418c 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -53,7 +53,7 @@ class L2(BaseCache): #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ] +cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), @@ -90,6 +90,6 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort Bus" -#root.trace.cycle=3810800 +#root.trace.flags="Cache CachePort MemoryAccess" +#root.trace.cycle=1 -- cgit v1.2.3