From 5a9a743cfc4517f93e5c94533efa767b92272c59 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 13 Feb 2012 06:43:09 -0500 Subject: MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. --- tests/configs/inorder-timing.py | 4 ++-- tests/configs/memtest-ruby.py | 2 +- tests/configs/memtest.py | 10 +++++----- tests/configs/o3-timing-mp-ruby.py | 4 ++-- tests/configs/o3-timing-mp.py | 8 ++++---- tests/configs/o3-timing-ruby.py | 4 ++-- tests/configs/o3-timing.py | 4 ++-- tests/configs/pc-o3-timing.py | 8 ++++---- tests/configs/pc-simple-atomic.py | 8 ++++---- tests/configs/pc-simple-timing.py | 8 ++++---- tests/configs/realview-o3-dual.py | 8 ++++---- tests/configs/realview-o3.py | 8 ++++---- tests/configs/realview-simple-atomic-dual.py | 8 ++++---- tests/configs/realview-simple-atomic.py | 8 ++++---- tests/configs/realview-simple-timing-dual.py | 8 ++++---- tests/configs/realview-simple-timing.py | 8 ++++---- tests/configs/rubytest-ruby.py | 2 +- tests/configs/simple-atomic-mp-ruby.py | 4 ++-- tests/configs/simple-atomic-mp.py | 8 ++++---- tests/configs/simple-atomic.py | 4 ++-- tests/configs/simple-timing-mp.py | 8 ++++---- tests/configs/simple-timing.py | 4 ++-- tests/configs/tsunami-inorder.py | 8 ++++---- tests/configs/tsunami-o3-dual.py | 8 ++++---- tests/configs/tsunami-o3.py | 8 ++++---- tests/configs/tsunami-simple-atomic-dual.py | 8 ++++---- tests/configs/tsunami-simple-atomic.py | 8 ++++---- tests/configs/tsunami-simple-timing-dual.py | 8 ++++---- tests/configs/tsunami-simple-timing.py | 8 ++++---- tests/configs/twosys-tsunami-simple-atomic.py | 8 ++++---- 30 files changed, 101 insertions(+), 101 deletions(-) (limited to 'tests') diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index 2a87cb663..dcef25be8 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -50,8 +50,8 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) -system.system_port = system.membus.port -system.physmem.port = system.membus.port +system.system_port = system.membus.slave +system.physmem.port = system.membus.master cpu.connectAllPorts(system.membus) root = Root(full_system = False, system = system) diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 43031dd02..e2c59497e 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -91,7 +91,7 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # Tie the cpu test and functional ports to the ruby cpu ports and # physmem, respectively # - cpus[i].test = ruby_port.port + cpus[i].test = ruby_port.slave cpus[i].functional = system.funcmem.port # diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index edb18f39a..6fface748 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -63,22 +63,22 @@ system = System(cpu = cpus, funcmem = PhysicalMemory(), # l2cache & bus system.toL2Bus = Bus(clock="500GHz", width=16) system.l2c = L2(size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port +system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus -system.l2c.mem_side = system.membus.port +system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test - cpu.l1c.mem_side = system.toL2Bus.port + cpu.l1c.mem_side = system.toL2Bus.slave system.funcmem.port = cpu.functional -system.system_port = system.membus.port +system.system_port = system.membus.slave # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # ----------------------- diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index cff511bf8..3e5e34e71 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -44,10 +44,10 @@ for cpu in cpus: cpu.clock = '2GHz' # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # Connect the system port for loading of binaries etc -system.system_port = system.membus.port +system.system_port = system.membus.slave # ----------------------- # run simulation diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 95323c2f6..1974d686f 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -62,10 +62,10 @@ Bus()) # l2cache & bus system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port +system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus -system.l2c.mem_side = system.membus.port +system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: @@ -76,10 +76,10 @@ for cpu in cpus: cpu.clock = '2GHz' # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # connect system port to membus -system.system_port = system.membus.port +system.system_port = system.membus.slave # ----------------------- # run simulation diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index 14b0ff1ab..0bdb73445 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -40,10 +40,10 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = ruby_memory, membus = Bus()) -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master cpu.connectAllPorts(system.membus) # Connect the system port for loading of binaries etc -system.system_port = system.membus.port +system.system_port = system.membus.slave root = Root(full_system = False, system = system) diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 9701b1012..3003f0bcd 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -50,8 +50,8 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) -system.system_port = system.membus.port -system.physmem.port = system.membus.port +system.system_port = system.membus.slave +system.physmem.port = system.membus.master cpu.connectAllPorts(system.membus) root = Root(full_system = False, system = system) diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index f3b8e700f..a04b04134 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -87,8 +87,8 @@ mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.iocache = IOCache(addr_range=mem_size) -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpu #create the l1/l2 bus @@ -96,8 +96,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index 62c7c7bd4..24270edb0 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -89,8 +89,8 @@ mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.iocache = IOCache(addr_range=mem_size) -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpu #create the l1/l2 bus @@ -98,8 +98,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index cbfda22a2..97a607d8e 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -92,14 +92,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache(addr_range=mem_size) -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index 42532065b..ad1c4752b 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -72,8 +72,8 @@ cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index f466bc480..058111d67 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -76,14 +76,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py index 5baa3c91a..985f2016b 100644 --- a/tests/configs/realview-simple-atomic-dual.py +++ b/tests/configs/realview-simple-atomic-dual.py @@ -72,8 +72,8 @@ cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave system.l2c.num_cpus = 2 #connect up the cpu and l1s diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index f1de86411..1e5bab50c 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -71,8 +71,8 @@ cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpu #create the l1/l2 bus @@ -80,8 +80,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 95daa81b6..e55cb72cb 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -72,8 +72,8 @@ cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 8d1840571..1e27a5dc9 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -76,14 +76,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 116afa2b6..c53ed26bd 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -88,7 +88,7 @@ for ruby_port in system.ruby._cpu_ruby_ports: # # Tie the ruby tester ports to the ruby cpu ports # - tester.cpuPort = ruby_port.port + tester.cpuPort = ruby_port.slave # # Tell the sequencer this is the ruby tester so that it diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 8b61fd1f2..a9ee3c4d0 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -45,10 +45,10 @@ for cpu in cpus: cpu.clock = '2GHz' # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # Connect the system port for loading of binaries etc -system.system_port = system.membus.port +system.system_port = system.membus.slave # ----------------------- # run simulation diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index 2fa7edb2a..8bc2e6e4f 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -61,10 +61,10 @@ Bus()) # l2cache & bus system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port +system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus -system.l2c.mem_side = system.membus.port +system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: @@ -75,10 +75,10 @@ for cpu in cpus: cpu.clock = '2GHz' # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # connect system port to membus -system.system_port = system.membus.port +system.system_port = system.membus.slave # ----------------------- # run simulation diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index eb7415b8d..5e5b94f27 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -32,8 +32,8 @@ from m5.objects import * system = System(cpu = AtomicSimpleCPU(cpu_id=0), physmem = PhysicalMemory(), membus = Bus()) -system.system_port = system.membus.port -system.physmem.port = system.membus.port +system.system_port = system.membus.slave +system.physmem.port = system.membus.master system.cpu.connectAllPorts(system.membus) system.cpu.clock = '2GHz' diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 06d535154..5ec7a6067 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -61,10 +61,10 @@ Bus()) # l2cache & bus system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port +system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus -system.l2c.mem_side = system.membus.port +system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: @@ -74,10 +74,10 @@ for cpu in cpus: cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' -system.system_port = system.membus.port +system.system_port = system.membus.slave # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # ----------------------- diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 19b40fe48..ea9428d8a 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -46,8 +46,8 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) -system.system_port = system.membus.port -system.physmem.port = system.membus.port +system.system_port = system.membus.slave +system.physmem.port = system.membus.master cpu.connectAllPorts(system.membus) cpu.clock = '2GHz' diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py index dc30633b3..0c3323f62 100644 --- a/tests/configs/tsunami-inorder.py +++ b/tests/configs/tsunami-inorder.py @@ -80,14 +80,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 1acfc903b..c30b1da04 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -77,14 +77,14 @@ system.cpu = cpus #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index accf350b3..015de3d0f 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -77,14 +77,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index ddc7dd1d7..08c71df33 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -72,8 +72,8 @@ cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('atomic') system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 897b1c946..69337ac14 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -72,8 +72,8 @@ cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeLinuxAlphaSystem('atomic') system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpu #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 48740ea15..f61a3f054 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -72,8 +72,8 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('timing') system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index e3a764e16..e705e35dd 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -77,14 +77,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index d32e5dd87..552acc0e1 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -41,8 +41,8 @@ test_sys.cpu.connectAllPorts(test_sys.membus) # from masters on the IO bus to the memory bus test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', ranges = [AddrRange(0, '8GB')]) -test_sys.iobridge.slave = test_sys.iobus.port -test_sys.iobridge.master = test_sys.membus.port +test_sys.iobridge.slave = test_sys.iobus.master +test_sys.iobridge.master = test_sys.membus.slave drive_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-server.rcS')) @@ -50,8 +50,8 @@ drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) drive_sys.cpu.connectAllPorts(drive_sys.membus) drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', ranges = [AddrRange(0, '8GB')]) -drive_sys.iobridge.slave = drive_sys.iobus.port -drive_sys.iobridge.master = drive_sys.membus.port +drive_sys.iobridge.slave = drive_sys.iobus.master +drive_sys.iobridge.master = drive_sys.membus.slave root = makeDualRoot(True, test_sys, drive_sys, "ethertrace") -- cgit v1.2.3