From 7e27860ef4e5016f5a3c907fbe4c7858f83c8100 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sun, 23 Feb 2014 19:16:16 -0600 Subject: ruby: route all packets through ruby port Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch. --- tests/configs/pc-simple-timing-ruby.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 57f9b6679..81ec2fa9b 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -82,9 +82,9 @@ for (i, cpu) in enumerate(system.cpu): cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.pio = system.piobus.master - cpu.interrupts.int_master = system.piobus.slave - cpu.interrupts.int_slave = system.piobus.master + cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master + cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave + cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master # Set access_phys_mem to True for ruby port system.ruby._cpu_ruby_ports[i].access_phys_mem = True -- cgit v1.2.3