From 45f881a4ced25105267799432c0f526400f0ba9e Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 5 Oct 2006 21:10:03 -0400 Subject: First pass at snooping stuff that compiles and doesn't break. Still need: -Handle NACK's on the recieve side -Distinguish top level caches -Handle repsonses from caches failing the fast path -Handle BusError and propogate it -Fix the invalidate packet associated with snooping in the cache src/mem/bus.cc: Make sure to snoop on functional accesses src/mem/cache/base_cache.cc: Wait to make a request into a response until it is ready to be issued src/mem/cache/base_cache.hh: Support range changes for snoops Set up snoop responses for cache->cache transfers src/mem/cache/cache_impl.hh: Only access the cache if it wasn't satisfied by cache->cache transfer Handle snoop phases (detect block, then snoop) Fix functional access to work properly (still need to fix snoop path for functional accesses) --HG-- extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8 --- tests/configs/o3-timing-mp.py | 90 +++++++++++++++++++++++++++++++++++++++ tests/configs/simple-atomic-mp.py | 86 +++++++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 tests/configs/o3-timing-mp.py create mode 100644 tests/configs/simple-atomic-mp.py (limited to 'tests') diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py new file mode 100644 index 000000000..881c23156 --- /dev/null +++ b/tests/configs/o3-timing-mp.py @@ -0,0 +1,90 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +from FullO3Config import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'timing' +root.trace.flags="Bus Cache" +#root.trace.flags = "BusAddrRanges" diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py new file mode 100644 index 000000000..cc1a36dda --- /dev/null +++ b/tests/configs/simple-atomic-mp.py @@ -0,0 +1,86 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'atomic' -- cgit v1.2.3 From 212c5aefb580375417d357d821255c67a8d90fdf Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 5 Oct 2006 23:28:03 -0400 Subject: Fixes for functional accesses to use the snoop path. And small other tweaks to snooping coherence. src/mem/cache/base_cache.hh: Make timing response at the time of send. src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: Update probe interface to be bi-directional for functional accesses src/mem/packet.hh: Add the function to create an atomic response to a given request --HG-- extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6 --- tests/configs/simple-timing-mp.py | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 tests/configs/simple-timing-mp.py (limited to 'tests') diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py new file mode 100644 index 000000000..9fc5f3874 --- /dev/null +++ b/tests/configs/simple-timing-mp.py @@ -0,0 +1,86 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'timing' -- cgit v1.2.3 From 230fb85a8a9990e1c2511f34a07ba4250becff82 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 6 Oct 2006 00:39:21 -0400 Subject: update full system references for newest disk image from linux-dist. --HG-- extra : convert_revision : c1232dafff0d92d8041af1b9de1dc8c55ee50f40 --- .../linux/tsunami-simple-atomic-dual/config.ini | 4 + .../linux/tsunami-simple-atomic-dual/config.out | 7 + .../console.system.sim_console | 10 +- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 409 ++++++++++----------- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-atomic/config.ini | 3 + .../alpha/linux/tsunami-simple-atomic/config.out | 6 + .../console.system.sim_console | 10 +- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 219 ++++++----- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 6 +- .../linux/tsunami-simple-timing-dual/config.ini | 4 + .../linux/tsunami-simple-timing-dual/config.out | 7 + .../console.system.sim_console | 10 +- .../linux/tsunami-simple-timing-dual/m5stats.txt | 407 ++++++++++---------- .../alpha/linux/tsunami-simple-timing-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-timing/config.ini | 3 + .../alpha/linux/tsunami-simple-timing/config.out | 6 + .../console.system.sim_console | 10 +- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 217 ++++++----- .../ref/alpha/linux/tsunami-simple-timing/stdout | 6 +- 20 files changed, 680 insertions(+), 676 deletions(-) (limited to 'tests') diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index c2bcb99aa..3d719c501 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -58,6 +58,7 @@ mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -116,6 +118,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -584,6 +587,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 737ee6611..b8290213e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu0.itb @@ -113,6 +115,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu1.itb @@ -492,6 +495,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -535,6 +539,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console index c3c7b2676..4a397ddbf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console @@ -74,7 +74,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -102,10 +102,6 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 480k freed - init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index c7715aeac..376929ebb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,239 +1,232 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1382023 # Simulator instruction rate (inst/s) -host_mem_usage 194588 # Number of bytes of host memory used -host_seconds 45.78 # Real time elapsed on the host -host_tick_rate 77681401 # Simulator tick rate (ticks/s) +host_inst_rate 1361363 # Simulator instruction rate (inst/s) +host_mem_usage 194440 # Number of bytes of host memory used +host_seconds 45.04 # Real time elapsed on the host +host_tick_rate 78691874 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63264995 # Number of instructions simulated -sim_seconds 1.778030 # Number of seconds simulated -sim_ticks 3556060806 # Number of ticks simulated -system.cpu0.dtb.accesses 1831687 # DTB accesses -system.cpu0.dtb.acv 360 # DTB access violations -system.cpu0.dtb.hits 12876975 # DTB hits -system.cpu0.dtb.misses 11050 # DTB misses -system.cpu0.dtb.read_accesses 495437 # DTB read accesses -system.cpu0.dtb.read_acv 219 # DTB read access violations -system.cpu0.dtb.read_hits 7121424 # DTB read hits -system.cpu0.dtb.read_misses 9036 # DTB read misses -system.cpu0.dtb.write_accesses 1336250 # DTB write accesses -system.cpu0.dtb.write_acv 141 # DTB write access violations -system.cpu0.dtb.write_hits 5755551 # DTB write hits -system.cpu0.dtb.write_misses 2014 # DTB write misses -system.cpu0.idle_fraction 0.984569 # Percentage of idle cycles -system.cpu0.itb.accesses 2328068 # ITB accesses -system.cpu0.itb.acv 216 # ITB acv -system.cpu0.itb.hits 2323500 # ITB hits -system.cpu0.itb.misses 4568 # ITB misses -system.cpu0.kern.callpal 179206 # number of callpals executed +sim_insts 61314617 # Number of instructions simulated +sim_seconds 1.772124 # Number of seconds simulated +sim_ticks 3544247159 # Number of ticks simulated +system.cpu0.dtb.accesses 1850344 # DTB accesses +system.cpu0.dtb.acv 301 # DTB access violations +system.cpu0.dtb.hits 12691711 # DTB hits +system.cpu0.dtb.misses 8349 # DTB misses +system.cpu0.dtb.read_accesses 509385 # DTB read accesses +system.cpu0.dtb.read_acv 184 # DTB read access violations +system.cpu0.dtb.read_hits 7018751 # DTB read hits +system.cpu0.dtb.read_misses 6579 # DTB read misses +system.cpu0.dtb.write_accesses 1340959 # DTB write accesses +system.cpu0.dtb.write_acv 117 # DTB write access violations +system.cpu0.dtb.write_hits 5672960 # DTB write hits +system.cpu0.dtb.write_misses 1770 # DTB write misses +system.cpu0.idle_fraction 0.984893 # Percentage of idle cycles +system.cpu0.itb.accesses 1981604 # ITB accesses +system.cpu0.itb.acv 161 # ITB acv +system.cpu0.itb.hits 1978255 # ITB hits +system.cpu0.itb.misses 3349 # ITB misses +system.cpu0.kern.callpal 176688 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1375 0.77% 0.82% # number of callpals executed -system.cpu0.kern.callpal_tbi 20 0.01% 0.83% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.84% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168681 94.13% 94.96% # number of callpals executed -system.cpu0.kern.callpal_rdps 4713 2.63% 97.59% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.59% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.59% # number of callpals executed -system.cpu0.kern.callpal_rdusp 11 0.01% 97.60% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.60% # number of callpals executed -system.cpu0.kern.callpal_rti 3639 2.03% 99.63% # number of callpals executed -system.cpu0.kern.callpal_callsys 461 0.26% 99.89% # number of callpals executed -system.cpu0.kern.callpal_imb 197 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 97 0.05% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 1117 0.63% 0.69% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 0.71% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 0.72% # number of callpals executed +system.cpu0.kern.callpal_swpipl 166811 94.41% 95.13% # number of callpals executed +system.cpu0.kern.callpal_rdps 4911 2.78% 97.91% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.91% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.91% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 97.91% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.92% # number of callpals executed +system.cpu0.kern.callpal_rti 3236 1.83% 99.75% # number of callpals executed +system.cpu0.kern.callpal_callsys 325 0.18% 99.93% # number of callpals executed +system.cpu0.kern.callpal_imb 121 0.07% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197512 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 190918 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1917 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174431 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 73383 42.07% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 286 0.16% 42.23% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5540 3.18% 45.41% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 45.41% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 95214 54.59% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 156222 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 73336 46.94% 46.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 286 0.18% 47.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5540 3.55% 50.67% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 77052 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3555570558 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3533670973 99.38% 99.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 45785 0.00% 99.39% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1008642 0.03% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1988 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 20843170 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.895609 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999360 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 1922 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 172116 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72060 41.87% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 251 0.15% 42.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 5518 3.21% 45.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 7 0.00% 45.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 94280 54.78% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 153515 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 72019 46.91% 46.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 251 0.16% 47.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 5518 3.59% 50.67% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 7 0.00% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 75720 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3543835079 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3521923327 99.38% 99.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 39982 0.00% 99.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1005040 0.03% 99.41% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1756 0.00% 99.41% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 20864974 0.59% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.891928 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.999431 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.809251 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1633 -system.cpu0.kern.mode_good_user 1486 -system.cpu0.kern.mode_good_idle 147 -system.cpu0.kern.mode_switch_kernel 2898 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1486 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2090 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.504479 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.563492 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.803140 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1277 +system.cpu0.kern.mode_good_user 1129 +system.cpu0.kern.mode_good_idle 148 +system.cpu0.kern.mode_switch_kernel 2253 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1129 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 2074 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.468109 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.566800 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.070335 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 29671488 0.83% 0.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2605758 0.07% 0.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3523245106 99.09% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1376 # number of times the context was actually changed -system.cpu0.kern.syscall 312 # number of syscalls executed -system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed -system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed -system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed -system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed -system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed -system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed -system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed -system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed -system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed -system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed -system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed -system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed -system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed -system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed -system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed -system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed -system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015431 # Percentage of non-idle cycles -system.cpu0.numCycles 54873632 # number of cpu cycles simulated -system.cpu0.num_insts 54868848 # Number of instructions executed -system.cpu0.num_refs 12918621 # Number of memory references -system.cpu1.dtb.accesses 524398 # DTB accesses -system.cpu1.dtb.acv 60 # DTB access violations -system.cpu1.dtb.hits 2058922 # DTB hits -system.cpu1.dtb.misses 5263 # DTB misses -system.cpu1.dtb.read_accesses 337746 # DTB read accesses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_hits 1301369 # DTB read hits -system.cpu1.dtb.read_misses 4766 # DTB read misses -system.cpu1.dtb.write_accesses 186652 # DTB write accesses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_hits 757553 # DTB write hits -system.cpu1.dtb.write_misses 497 # DTB write misses -system.cpu1.idle_fraction 0.997638 # Percentage of idle cycles -system.cpu1.itb.accesses 1711917 # ITB accesses +system.cpu0.kern.mode_switch_good_idle 0.071360 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 28710240 0.81% 0.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2184201 0.06% 0.87% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 3512891779 99.13% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 1118 # number of times the context was actually changed +system.cpu0.kern.syscall 192 # number of syscalls executed +system.cpu0.kern.syscall_fork 7 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall_read 13 6.77% 10.42% # number of syscalls executed +system.cpu0.kern.syscall_write 4 2.08% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_close 28 14.58% 27.08% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.52% 27.60% # number of syscalls executed +system.cpu0.kern.syscall_obreak 7 3.65% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_lseek 6 3.12% 34.37% # number of syscalls executed +system.cpu0.kern.syscall_getpid 4 2.08% 36.46% # number of syscalls executed +system.cpu0.kern.syscall_setuid 1 0.52% 36.98% # number of syscalls executed +system.cpu0.kern.syscall_getuid 3 1.56% 38.54% # number of syscalls executed +system.cpu0.kern.syscall_access 7 3.65% 42.19% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 1.04% 43.23% # number of syscalls executed +system.cpu0.kern.syscall_open 34 17.71% 60.94% # number of syscalls executed +system.cpu0.kern.syscall_getgid 3 1.56% 62.50% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 8 4.17% 66.67% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 4.69% 71.35% # number of syscalls executed +system.cpu0.kern.syscall_readlink 1 0.52% 71.87% # number of syscalls executed +system.cpu0.kern.syscall_execve 5 2.60% 74.48% # number of syscalls executed +system.cpu0.kern.syscall_mmap 22 11.46% 85.94% # number of syscalls executed +system.cpu0.kern.syscall_munmap 2 1.04% 86.98% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 6 3.12% 90.10% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.52% 90.62% # number of syscalls executed +system.cpu0.kern.syscall_dup2 2 1.04% 91.67% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 4.17% 95.83% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 1.04% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 1.04% 97.92% # number of syscalls executed +system.cpu0.kern.syscall_setgid 1 0.52% 98.44% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 1 0.52% 98.96% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 1.04% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015107 # Percentage of non-idle cycles +system.cpu0.numCycles 53543489 # number of cpu cycles simulated +system.cpu0.num_insts 53539979 # Number of instructions executed +system.cpu0.num_refs 12727196 # Number of memory references +system.cpu1.dtb.accesses 460215 # DTB accesses +system.cpu1.dtb.acv 72 # DTB access violations +system.cpu1.dtb.hits 2012555 # DTB hits +system.cpu1.dtb.misses 4236 # DTB misses +system.cpu1.dtb.read_accesses 319867 # DTB read accesses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_hits 1276251 # DTB read hits +system.cpu1.dtb.read_misses 3800 # DTB read misses +system.cpu1.dtb.write_accesses 140348 # DTB write accesses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_hits 736304 # DTB write hits +system.cpu1.dtb.write_misses 436 # DTB write misses +system.cpu1.idle_fraction 0.997806 # Percentage of idle cycles +system.cpu1.itb.accesses 1302484 # ITB accesses system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 1709682 # ITB hits -system.cpu1.itb.misses 2235 # ITB misses -system.cpu1.kern.callpal 25990 # number of callpals executed +system.cpu1.itb.hits 1300768 # ITB hits +system.cpu1.itb.misses 1716 # ITB misses +system.cpu1.kern.callpal 27118 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 8 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed +system.cpu1.kern.callpal_wripir 7 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal_swpctx 554 2.13% 2.17% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.03% 2.20% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.03% 2.23% # number of callpals executed -system.cpu1.kern.callpal_swpipl 22366 86.06% 88.28% # number of callpals executed -system.cpu1.kern.callpal_rdps 98 0.38% 88.66% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 88.66% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.02% 88.68% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 88.68% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 88.70% # number of callpals executed -system.cpu1.kern.callpal_rti 2613 10.05% 98.75% # number of callpals executed -system.cpu1.kern.callpal_callsys 208 0.80% 99.55% # number of callpals executed -system.cpu1.kern.callpal_imb 116 0.45% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 515 1.90% 1.94% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.04% 1.97% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.03% 2.00% # number of callpals executed +system.cpu1.kern.callpal_swpipl 23496 86.64% 88.64% # number of callpals executed +system.cpu1.kern.callpal_rdps 251 0.93% 89.57% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 89.57% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 89.59% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 89.59% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 89.60% # number of callpals executed +system.cpu1.kern.callpal_rti 2552 9.41% 99.01% # number of callpals executed +system.cpu1.kern.callpal_callsys 208 0.77% 99.78% # number of callpals executed +system.cpu1.kern.callpal_imb 59 0.22% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 35475 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 35069 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1946 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 26882 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9636 35.85% 35.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5504 20.47% 56.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 91 0.34% 56.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 11651 43.34% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 26602 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9607 36.11% 36.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5504 20.69% 56.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 91 0.34% 57.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11400 42.85% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3556060349 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3533823708 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1040434 0.03% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 23860 0.00% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21172347 0.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.989584 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.996990 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 1947 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 27951 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10084 36.08% 36.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 5485 19.62% 55.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 97 0.35% 56.05% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 12285 43.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 27484 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10061 36.61% 36.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 5485 19.96% 56.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 97 0.35% 56.92% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 11841 43.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3544246744 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3521927913 99.37% 99.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1037048 0.03% 99.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 25211 0.00% 99.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 21256572 0.60% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.983292 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.997719 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.978457 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 691 -system.cpu1.kern.mode_good_user 692 +system.cpu1.kern.ipl_used_31 0.963858 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 636 +system.cpu1.kern.mode_good_user 637 system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 3163 # number of protection mode switches -system.cpu1.kern.mode_switch_user 692 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 3063 # number of protection mode switches +system.cpu1.kern.mode_switch_user 637 # number of protection mode switches system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.358755 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.218463 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 0.344054 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.207640 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3554209770 99.95% 99.95% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1850577 0.05% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 3542834137 99.96% 99.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1412605 0.04% 100.00% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 555 # number of times the context was actually changed -system.cpu1.kern.syscall 163 # number of syscalls executed -system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed -system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed -system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed -system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed -system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed -system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed -system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed -system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed -system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed -system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed -system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed -system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed -system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002362 # Percentage of non-idle cycles -system.cpu1.numCycles 8398405 # number of cpu cycles simulated -system.cpu1.num_insts 8396147 # Number of instructions executed -system.cpu1.num_refs 2073144 # Number of memory references +system.cpu1.kern.swap_context 516 # number of times the context was actually changed +system.cpu1.kern.syscall 137 # number of syscalls executed +system.cpu1.kern.syscall_fork 1 0.73% 0.73% # number of syscalls executed +system.cpu1.kern.syscall_read 17 12.41% 13.14% # number of syscalls executed +system.cpu1.kern.syscall_close 15 10.95% 24.09% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 0.73% 24.82% # number of syscalls executed +system.cpu1.kern.syscall_obreak 8 5.84% 30.66% # number of syscalls executed +system.cpu1.kern.syscall_lseek 4 2.92% 33.58% # number of syscalls executed +system.cpu1.kern.syscall_getpid 2 1.46% 35.04% # number of syscalls executed +system.cpu1.kern.syscall_setuid 3 2.19% 37.23% # number of syscalls executed +system.cpu1.kern.syscall_getuid 3 2.19% 39.42% # number of syscalls executed +system.cpu1.kern.syscall_access 4 2.92% 42.34% # number of syscalls executed +system.cpu1.kern.syscall_open 21 15.33% 57.66% # number of syscalls executed +system.cpu1.kern.syscall_getgid 3 2.19% 59.85% # number of syscalls executed +system.cpu1.kern.syscall_sigprocmask 2 1.46% 61.31% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 0.73% 62.04% # number of syscalls executed +system.cpu1.kern.syscall_execve 2 1.46% 63.50% # number of syscalls executed +system.cpu1.kern.syscall_mmap 32 23.36% 86.86% # number of syscalls executed +system.cpu1.kern.syscall_munmap 1 0.73% 87.59% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 10 7.30% 94.89% # number of syscalls executed +system.cpu1.kern.syscall_dup2 1 0.73% 95.62% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 1.46% 97.08% # number of syscalls executed +system.cpu1.kern.syscall_setgid 3 2.19% 99.27% # number of syscalls executed +system.cpu1.kern.syscall_getrlimit 1 0.73% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.002194 # Percentage of non-idle cycles +system.cpu1.numCycles 7776377 # number of cpu cycles simulated +system.cpu1.num_insts 7774638 # Number of instructions executed +system.cpu1.num_refs 2025195 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index c8330eef2..039088577 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:43:12 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:24:12 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3556060806 because m5_exit instruction encountered +Exiting @ tick 3544247159 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c017495f6..e30428078 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -58,6 +58,7 @@ mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -554,6 +556,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 018308862..ea63dce8b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu.itb @@ -465,6 +467,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -508,6 +511,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console index ea7a20777..d6e3955cc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console @@ -69,7 +69,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -97,10 +97,6 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 480k freed - init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 3a7dc1cd4..5c403c0a9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,130 +1,127 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1346129 # Simulator instruction rate (inst/s) -host_mem_usage 194392 # Number of bytes of host memory used -host_seconds 44.52 # Real time elapsed on the host -host_tick_rate 78470813 # Simulator tick rate (ticks/s) +host_inst_rate 1121378 # Simulator instruction rate (inst/s) +host_mem_usage 194272 # Number of bytes of host memory used +host_seconds 51.72 # Real time elapsed on the host +host_tick_rate 67313414 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 59929520 # Number of instructions simulated -sim_seconds 1.746773 # Number of seconds simulated -sim_ticks 3493545624 # Number of ticks simulated -system.cpu.dtb.accesses 2354955 # DTB accesses -system.cpu.dtb.acv 413 # DTB access violations -system.cpu.dtb.hits 13929995 # DTB hits -system.cpu.dtb.misses 16187 # DTB misses -system.cpu.dtb.read_accesses 832415 # DTB read accesses -system.cpu.dtb.read_acv 242 # DTB read access violations -system.cpu.dtb.read_hits 7718636 # DTB read hits -system.cpu.dtb.read_misses 13695 # DTB read misses -system.cpu.dtb.write_accesses 1522540 # DTB write accesses -system.cpu.dtb.write_acv 171 # DTB write access violations -system.cpu.dtb.write_hits 6211359 # DTB write hits -system.cpu.dtb.write_misses 2492 # DTB write misses -system.cpu.idle_fraction 0.982844 # Percentage of idle cycles -system.cpu.itb.accesses 4037380 # ITB accesses -system.cpu.itb.acv 239 # ITB acv -system.cpu.itb.hits 4030656 # ITB hits -system.cpu.itb.misses 6724 # ITB misses -system.cpu.kern.callpal 184022 # number of callpals executed +sim_insts 58001813 # Number of instructions simulated +sim_seconds 1.740863 # Number of seconds simulated +sim_ticks 3481726167 # Number of ticks simulated +system.cpu.dtb.accesses 2309470 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 13711941 # DTB hits +system.cpu.dtb.misses 12493 # DTB misses +system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 7597829 # DTB read hits +system.cpu.dtb.read_misses 10298 # DTB read misses +system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6114112 # DTB write hits +system.cpu.dtb.write_misses 2195 # DTB write misses +system.cpu.idle_fraction 0.983340 # Percentage of idle cycles +system.cpu.itb.accesses 3281346 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 3276356 # ITB hits +system.cpu.itb.misses 4990 # ITB misses +system.cpu.kern.callpal 182718 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1864 1.01% 1.02% # number of callpals executed -system.cpu.kern.callpal_tbi 28 0.02% 1.03% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 1.03% # number of callpals executed -system.cpu.kern.callpal_swpipl 172016 93.48% 94.51% # number of callpals executed -system.cpu.kern.callpal_rdps 4808 2.61% 97.12% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.12% # number of callpals executed -system.cpu.kern.callpal_wrusp 8 0.00% 97.13% # number of callpals executed -system.cpu.kern.callpal_rdusp 12 0.01% 97.13% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.14% # number of callpals executed -system.cpu.kern.callpal_rti 4291 2.33% 99.47% # number of callpals executed -system.cpu.kern.callpal_callsys 667 0.36% 99.83% # number of callpals executed -system.cpu.kern.callpal_imb 314 0.17% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 1574 0.86% 0.86% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed +system.cpu.kern.callpal_swpipl 171359 93.78% 94.68% # number of callpals executed +system.cpu.kern.callpal_rdps 5159 2.82% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rti 3829 2.10% 99.61% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 209657 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 202783 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1868 # number of quiesce instructions executed -system.cpu.kern.ipl_count 178378 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75463 42.31% 42.31% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 286 0.16% 42.47% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5446 3.05% 45.52% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 97183 54.48% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 160188 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 75397 47.07% 47.07% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 286 0.18% 47.25% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5446 3.40% 50.65% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 79059 49.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3493545167 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3471576124 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 45785 0.00% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 934362 0.03% 99.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 20988896 0.60% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.898026 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999125 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 1877 # number of quiesce instructions executed +system.cpu.kern.ipl_count 177218 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74624 42.11% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 251 0.14% 42.25% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 5425 3.06% 45.31% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 96918 54.69% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 158463 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74570 47.06% 47.06% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 251 0.16% 47.22% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 5425 3.42% 50.64% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 78217 49.36% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3481725752 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3459659082 99.37% 99.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 39982 0.00% 99.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 930159 0.03% 99.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 21096529 0.61% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.894170 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.999276 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.813506 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 2342 -system.cpu.kern.mode_good_user 2171 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 4092 # number of protection mode switches -system.cpu.kern.mode_switch_user 2171 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2041 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.564066 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.572336 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.807043 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1939 +system.cpu.kern.mode_good_user 1757 +system.cpu.kern.mode_good_idle 182 +system.cpu.kern.mode_switch_kernel 3320 # number of protection mode switches +system.cpu.kern.mode_switch_user 1757 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2061 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.543289 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.584036 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.083782 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 33028385 0.95% 0.95% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 4450361 0.13% 1.07% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3456066419 98.93% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1865 # number of times the context was actually changed -system.cpu.kern.syscall 475 # number of syscalls executed -system.cpu.kern.syscall_fork 10 2.11% 2.11% # number of syscalls executed -system.cpu.kern.syscall_read 33 6.95% 9.05% # number of syscalls executed -system.cpu.kern.syscall_write 7 1.47% 10.53% # number of syscalls executed -system.cpu.kern.syscall_close 49 10.32% 20.84% # number of syscalls executed -system.cpu.kern.syscall_chdir 1 0.21% 21.05% # number of syscalls executed -system.cpu.kern.syscall_chmod 1 0.21% 21.26% # number of syscalls executed -system.cpu.kern.syscall_obreak 44 9.26% 30.53% # number of syscalls executed -system.cpu.kern.syscall_lseek 13 2.74% 33.26% # number of syscalls executed -system.cpu.kern.syscall_getpid 10 2.11% 35.37% # number of syscalls executed -system.cpu.kern.syscall_setuid 4 0.84% 36.21% # number of syscalls executed -system.cpu.kern.syscall_getuid 8 1.68% 37.89% # number of syscalls executed -system.cpu.kern.syscall_access 4 0.84% 38.74% # number of syscalls executed -system.cpu.kern.syscall_dup 4 0.84% 39.58% # number of syscalls executed -system.cpu.kern.syscall_open 68 14.32% 53.89% # number of syscalls executed -system.cpu.kern.syscall_getgid 8 1.68% 55.58% # number of syscalls executed -system.cpu.kern.syscall_sigprocmask 14 2.95% 58.53% # number of syscalls executed -system.cpu.kern.syscall_ioctl 16 3.37% 61.89% # number of syscalls executed -system.cpu.kern.syscall_readlink 2 0.42% 62.32% # number of syscalls executed -system.cpu.kern.syscall_execve 8 1.68% 64.00% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_stat 31 6.53% 70.53% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_lstat 1 0.21% 70.74% # number of syscalls executed -system.cpu.kern.syscall_mmap 55 11.58% 82.32% # number of syscalls executed -system.cpu.kern.syscall_munmap 6 1.26% 83.58% # number of syscalls executed -system.cpu.kern.syscall_mprotect 14 2.95% 86.53% # number of syscalls executed -system.cpu.kern.syscall_gethostname 2 0.42% 86.95% # number of syscalls executed -system.cpu.kern.syscall_dup2 4 0.84% 87.79% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_fstat 28 5.89% 93.68% # number of syscalls executed -system.cpu.kern.syscall_fcntl 14 2.95% 96.63% # number of syscalls executed -system.cpu.kern.syscall_socket 3 0.63% 97.26% # number of syscalls executed -system.cpu.kern.syscall_connect 3 0.63% 97.89% # number of syscalls executed -system.cpu.kern.syscall_setgid 4 0.84% 98.74% # number of syscalls executed -system.cpu.kern.syscall_getrlimit 3 0.63% 99.37% # number of syscalls executed -system.cpu.kern.syscall_setsid 3 0.63% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017156 # Percentage of non-idle cycles -system.cpu.numCycles 59936483 # number of cpu cycles simulated -system.cpu.num_insts 59929520 # Number of instructions executed -system.cpu.num_refs 13982880 # Number of memory references +system.cpu.kern.mode_switch_good_idle 0.088307 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 31887159 0.92% 0.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3591270 0.10% 1.02% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3446247321 98.98% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 1575 # number of times the context was actually changed +system.cpu.kern.syscall 329 # number of syscalls executed +system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed +system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed +system.cpu.kern.syscall_write 4 1.22% 12.77% # number of syscalls executed +system.cpu.kern.syscall_close 43 13.07% 25.84% # number of syscalls executed +system.cpu.kern.syscall_chdir 1 0.30% 26.14% # number of syscalls executed +system.cpu.kern.syscall_chmod 1 0.30% 26.44% # number of syscalls executed +system.cpu.kern.syscall_obreak 15 4.56% 31.00% # number of syscalls executed +system.cpu.kern.syscall_lseek 10 3.04% 34.04% # number of syscalls executed +system.cpu.kern.syscall_getpid 6 1.82% 35.87% # number of syscalls executed +system.cpu.kern.syscall_setuid 4 1.22% 37.08% # number of syscalls executed +system.cpu.kern.syscall_getuid 6 1.82% 38.91% # number of syscalls executed +system.cpu.kern.syscall_access 11 3.34% 42.25% # number of syscalls executed +system.cpu.kern.syscall_dup 2 0.61% 42.86% # number of syscalls executed +system.cpu.kern.syscall_open 55 16.72% 59.57% # number of syscalls executed +system.cpu.kern.syscall_getgid 6 1.82% 61.40% # number of syscalls executed +system.cpu.kern.syscall_sigprocmask 10 3.04% 64.44% # number of syscalls executed +system.cpu.kern.syscall_ioctl 10 3.04% 67.48% # number of syscalls executed +system.cpu.kern.syscall_readlink 1 0.30% 67.78% # number of syscalls executed +system.cpu.kern.syscall_execve 7 2.13% 69.91% # number of syscalls executed +system.cpu.kern.syscall_mmap 54 16.41% 86.32% # number of syscalls executed +system.cpu.kern.syscall_munmap 3 0.91% 87.23% # number of syscalls executed +system.cpu.kern.syscall_mprotect 16 4.86% 92.10% # number of syscalls executed +system.cpu.kern.syscall_gethostname 1 0.30% 92.40% # number of syscalls executed +system.cpu.kern.syscall_dup2 3 0.91% 93.31% # number of syscalls executed +system.cpu.kern.syscall_fcntl 10 3.04% 96.35% # number of syscalls executed +system.cpu.kern.syscall_socket 2 0.61% 96.96% # number of syscalls executed +system.cpu.kern.syscall_connect 2 0.61% 97.57% # number of syscalls executed +system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.016660 # Percentage of non-idle cycles +system.cpu.numCycles 58006987 # number of cpu cycles simulated +system.cpu.num_insts 58001813 # Number of instructions executed +system.cpu.num_refs 13757191 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c04cd5050..b3b3e8704 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:42:26 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:23:19 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3493545624 because m5_exit instruction encountered +Exiting @ tick 3481726167 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 97e9007e7..65401b549 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -58,6 +58,7 @@ mem_mode=timing pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[3] icache_port=system.membus.port[2] @@ -114,6 +116,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[5] icache_port=system.membus.port[4] @@ -580,6 +583,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 96c734e15..ed03e445d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu0.itb @@ -113,6 +115,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu1.itb @@ -492,6 +495,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -535,6 +539,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console index c3c7b2676..4a397ddbf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console @@ -74,7 +74,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -102,10 +102,6 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 480k freed - init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 666766e20..bf7320067 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,239 +1,232 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 804715 # Simulator instruction rate (inst/s) -host_mem_usage 194628 # Number of bytes of host memory used -host_seconds 78.40 # Real time elapsed on the host -host_tick_rate 45146741 # Simulator tick rate (ticks/s) +host_inst_rate 825990 # Simulator instruction rate (inst/s) +host_mem_usage 193572 # Number of bytes of host memory used +host_seconds 74.01 # Real time elapsed on the host +host_tick_rate 47654938 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63088076 # Number of instructions simulated -sim_seconds 1.769718 # Number of seconds simulated -sim_ticks 3539435029 # Number of ticks simulated -system.cpu0.dtb.accesses 1831687 # DTB accesses -system.cpu0.dtb.acv 360 # DTB access violations -system.cpu0.dtb.hits 10286150 # DTB hits -system.cpu0.dtb.misses 11050 # DTB misses -system.cpu0.dtb.read_accesses 495437 # DTB read accesses -system.cpu0.dtb.read_acv 219 # DTB read access violations -system.cpu0.dtb.read_hits 5741423 # DTB read hits -system.cpu0.dtb.read_misses 9036 # DTB read misses -system.cpu0.dtb.write_accesses 1336250 # DTB write accesses -system.cpu0.dtb.write_acv 141 # DTB write access violations -system.cpu0.dtb.write_hits 4544727 # DTB write hits -system.cpu0.dtb.write_misses 2014 # DTB write misses -system.cpu0.idle_fraction 0.984526 # Percentage of idle cycles -system.cpu0.itb.accesses 2328068 # ITB accesses -system.cpu0.itb.acv 216 # ITB acv -system.cpu0.itb.hits 2323500 # ITB hits -system.cpu0.itb.misses 4568 # ITB misses -system.cpu0.kern.callpal 145575 # number of callpals executed +sim_insts 61131962 # Number of instructions simulated +sim_seconds 1.763494 # Number of seconds simulated +sim_ticks 3526987181 # Number of ticks simulated +system.cpu0.dtb.accesses 1987164 # DTB accesses +system.cpu0.dtb.acv 291 # DTB access violations +system.cpu0.dtb.hits 10431590 # DTB hits +system.cpu0.dtb.misses 9590 # DTB misses +system.cpu0.dtb.read_accesses 606328 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 5831565 # DTB read hits +system.cpu0.dtb.read_misses 7663 # DTB read misses +system.cpu0.dtb.write_accesses 1380836 # DTB write accesses +system.cpu0.dtb.write_acv 117 # DTB write access violations +system.cpu0.dtb.write_hits 4600025 # DTB write hits +system.cpu0.dtb.write_misses 1927 # DTB write misses +system.cpu0.idle_fraction 0.984514 # Percentage of idle cycles +system.cpu0.itb.accesses 2372045 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 2368331 # ITB hits +system.cpu0.itb.misses 3714 # ITB misses +system.cpu0.kern.callpal 145084 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 45 0.03% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1334 0.92% 0.95% # number of callpals executed -system.cpu0.kern.callpal_tbi 20 0.01% 0.96% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.97% # number of callpals executed -system.cpu0.kern.callpal_swpipl 135235 92.90% 93.87% # number of callpals executed -system.cpu0.kern.callpal_rdps 4594 3.16% 97.02% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal_rdusp 11 0.01% 97.03% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal_rti 3660 2.51% 99.55% # number of callpals executed -system.cpu0.kern.callpal_callsys 461 0.32% 99.86% # number of callpals executed -system.cpu0.kern.callpal_imb 197 0.14% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 54 0.04% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_swpctx 1182 0.81% 0.85% # number of callpals executed +system.cpu0.kern.callpal_tbi 42 0.03% 0.88% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 0.89% # number of callpals executed +system.cpu0.kern.callpal_swpipl 135050 93.08% 93.97% # number of callpals executed +system.cpu0.kern.callpal_rdps 4795 3.30% 97.28% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal_wrusp 5 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 97.29% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.29% # number of callpals executed +system.cpu0.kern.callpal_rti 3431 2.36% 99.65% # number of callpals executed +system.cpu0.kern.callpal_callsys 364 0.25% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 139 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 163916 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 160926 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1952 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 141041 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 56950 40.38% 40.38% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 286 0.20% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5513 3.91% 44.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 52 0.04% 44.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78240 55.47% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 123339 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 56917 46.15% 46.15% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 286 0.23% 46.38% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5513 4.47% 50.85% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 52 0.04% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 60571 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3539063979 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3513499166 99.28% 99.28% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 60705 0.00% 99.28% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1354114 0.04% 99.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 18748 0.00% 99.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 24131246 0.68% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.874490 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999421 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 1958 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 140584 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 56549 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 251 0.18% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 5487 3.90% 44.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 51 0.04% 44.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 78246 55.66% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 122461 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 56518 46.15% 46.15% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 251 0.20% 46.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 5487 4.48% 50.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 51 0.04% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 60154 49.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3526986735 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3501352281 99.27% 99.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 53019 0.00% 99.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1348211 0.04% 99.31% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 18326 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 24214898 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.871088 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.999452 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.774169 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1632 -system.cpu0.kern.mode_good_user 1487 -system.cpu0.kern.mode_good_idle 145 -system.cpu0.kern.mode_switch_kernel 2857 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1487 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2125 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.504560 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.571229 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.768781 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1448 +system.cpu0.kern.mode_good_user 1300 +system.cpu0.kern.mode_good_idle 148 +system.cpu0.kern.mode_switch_kernel 2490 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1300 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 2110 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.490847 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.581526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.068235 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 23634401 0.67% 0.67% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3241731 0.09% 0.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3511854943 99.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1335 # number of times the context was actually changed -system.cpu0.kern.syscall 312 # number of syscalls executed -system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed -system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed -system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed -system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed -system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed -system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed -system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed -system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed -system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed -system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed -system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed -system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed -system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed -system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed -system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed -system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed -system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015474 # Percentage of non-idle cycles +system.cpu0.kern.mode_switch_good_idle 0.070142 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 23256451 0.66% 0.66% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3397192 0.10% 0.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 3500333090 99.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 1183 # number of times the context was actually changed +system.cpu0.kern.syscall 231 # number of syscalls executed +system.cpu0.kern.syscall_fork 6 2.60% 2.60% # number of syscalls executed +system.cpu0.kern.syscall_read 17 7.36% 9.96% # number of syscalls executed +system.cpu0.kern.syscall_write 4 1.73% 11.69% # number of syscalls executed +system.cpu0.kern.syscall_close 31 13.42% 25.11% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.43% 25.54% # number of syscalls executed +system.cpu0.kern.syscall_obreak 11 4.76% 30.30% # number of syscalls executed +system.cpu0.kern.syscall_lseek 6 2.60% 32.90% # number of syscalls executed +system.cpu0.kern.syscall_getpid 4 1.73% 34.63% # number of syscalls executed +system.cpu0.kern.syscall_setuid 2 0.87% 35.50% # number of syscalls executed +system.cpu0.kern.syscall_getuid 4 1.73% 37.23% # number of syscalls executed +system.cpu0.kern.syscall_access 9 3.90% 41.13% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 0.87% 41.99% # number of syscalls executed +system.cpu0.kern.syscall_open 42 18.18% 60.17% # number of syscalls executed +system.cpu0.kern.syscall_getgid 4 1.73% 61.90% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 7 3.03% 64.94% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 3.90% 68.83% # number of syscalls executed +system.cpu0.kern.syscall_readlink 1 0.43% 69.26% # number of syscalls executed +system.cpu0.kern.syscall_execve 4 1.73% 71.00% # number of syscalls executed +system.cpu0.kern.syscall_mmap 35 15.15% 86.15% # number of syscalls executed +system.cpu0.kern.syscall_munmap 2 0.87% 87.01% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 10 4.33% 91.34% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.43% 91.77% # number of syscalls executed +system.cpu0.kern.syscall_dup2 2 0.87% 92.64% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 3.46% 96.10% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 0.87% 96.97% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 0.87% 97.84% # number of syscalls executed +system.cpu0.kern.syscall_setgid 2 0.87% 98.70% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 1 0.43% 99.13% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 0.87% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015486 # Percentage of non-idle cycles system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 44447414 # Number of instructions executed -system.cpu0.num_refs 10321518 # Number of memory references -system.cpu1.dtb.accesses 524398 # DTB accesses -system.cpu1.dtb.acv 60 # DTB access violations -system.cpu1.dtb.hits 4612716 # DTB hits -system.cpu1.dtb.misses 5263 # DTB misses -system.cpu1.dtb.read_accesses 337746 # DTB read accesses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_hits 2649302 # DTB read hits -system.cpu1.dtb.read_misses 4766 # DTB read misses -system.cpu1.dtb.write_accesses 186652 # DTB write accesses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_hits 1963414 # DTB write hits -system.cpu1.dtb.write_misses 497 # DTB write misses -system.cpu1.idle_fraction 0.993423 # Percentage of idle cycles -system.cpu1.itb.accesses 1711918 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 1709683 # ITB hits -system.cpu1.itb.misses 2235 # ITB misses -system.cpu1.kern.callpal 58341 # number of callpals executed +system.cpu0.num_insts 44155958 # Number of instructions executed +system.cpu0.num_refs 10463340 # Number of memory references +system.cpu1.dtb.accesses 323344 # DTB accesses +system.cpu1.dtb.acv 82 # DTB access violations +system.cpu1.dtb.hits 4234985 # DTB hits +system.cpu1.dtb.misses 2977 # DTB misses +system.cpu1.dtb.read_accesses 222873 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 2431648 # DTB read hits +system.cpu1.dtb.read_misses 2698 # DTB read misses +system.cpu1.dtb.write_accesses 100471 # DTB write accesses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_hits 1803337 # DTB write hits +system.cpu1.dtb.write_misses 279 # DTB write misses +system.cpu1.idle_fraction 0.993979 # Percentage of idle cycles +system.cpu1.itb.accesses 912010 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 910678 # ITB hits +system.cpu1.itb.misses 1332 # ITB misses +system.cpu1.kern.callpal 57529 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 52 0.09% 0.09% # number of callpals executed +system.cpu1.kern.callpal_wripir 51 0.09% 0.09% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.09% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu1.kern.callpal_swpctx 588 1.01% 1.10% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 1.11% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 1.13% # number of callpals executed -system.cpu1.kern.callpal_swpipl 54562 93.52% 94.65% # number of callpals executed -system.cpu1.kern.callpal_rdps 217 0.37% 95.02% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 95.02% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 95.03% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 95.03% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 95.04% # number of callpals executed -system.cpu1.kern.callpal_rti 2571 4.41% 99.44% # number of callpals executed -system.cpu1.kern.callpal_callsys 208 0.36% 99.80% # number of callpals executed -system.cpu1.kern.callpal_imb 116 0.20% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 451 0.78% 0.88% # number of callpals executed +system.cpu1.kern.callpal_tbi 12 0.02% 0.90% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 0.91% # number of callpals executed +system.cpu1.kern.callpal_swpipl 54081 94.01% 94.92% # number of callpals executed +system.cpu1.kern.callpal_rdps 368 0.64% 95.56% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 95.56% # number of callpals executed +system.cpu1.kern.callpal_wrusp 2 0.00% 95.56% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.00% 95.57% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 95.57% # number of callpals executed +system.cpu1.kern.callpal_rti 2337 4.06% 99.63% # number of callpals executed +system.cpu1.kern.callpal_callsys 169 0.29% 99.93% # number of callpals executed +system.cpu1.kern.callpal_imb 41 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 67770 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 63811 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 58980 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 25467 43.18% 43.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5476 9.28% 52.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 45 0.08% 52.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 27992 47.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 58199 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 25424 43.68% 43.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5476 9.41% 53.09% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 45 0.08% 53.17% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 27254 46.83% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3539434499 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3510645847 99.19% 99.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1415637 0.04% 99.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 16792 0.00% 99.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 27356223 0.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.986758 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998312 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 1898 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 58267 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 25040 42.97% 42.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 5452 9.36% 52.33% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 54 0.09% 52.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 27721 47.58% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 57331 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 25007 43.62% 43.62% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 5452 9.51% 53.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 54 0.09% 53.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 26818 46.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3526422675 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3497592433 99.18% 99.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1410084 0.04% 99.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 19740 0.00% 99.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 27400418 0.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.983936 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.998682 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.973635 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 690 -system.cpu1.kern.mode_good_user 691 +system.cpu1.kern.ipl_used_31 0.967425 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 465 +system.cpu1.kern.mode_good_user 465 system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 3141 # number of protection mode switches -system.cpu1.kern.mode_switch_user 691 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 2771 # number of protection mode switches +system.cpu1.kern.mode_switch_user 465 # number of protection mode switches system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.360386 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.219675 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 0.287392 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.167809 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3537141786 99.94% 99.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 2292711 0.06% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good_idle no value # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3525066043 99.96% 99.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1294184 0.04% 100.00% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 589 # number of times the context was actually changed -system.cpu1.kern.syscall 163 # number of syscalls executed -system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed -system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed -system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed -system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed -system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed -system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed -system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed -system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed -system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed -system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed -system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed -system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed -system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.006577 # Percentage of non-idle cycles +system.cpu1.kern.swap_context 452 # number of times the context was actually changed +system.cpu1.kern.syscall 98 # number of syscalls executed +system.cpu1.kern.syscall_fork 2 2.04% 2.04% # number of syscalls executed +system.cpu1.kern.syscall_read 13 13.27% 15.31% # number of syscalls executed +system.cpu1.kern.syscall_close 12 12.24% 27.55% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 1.02% 28.57% # number of syscalls executed +system.cpu1.kern.syscall_obreak 4 4.08% 32.65% # number of syscalls executed +system.cpu1.kern.syscall_lseek 4 4.08% 36.73% # number of syscalls executed +system.cpu1.kern.syscall_getpid 2 2.04% 38.78% # number of syscalls executed +system.cpu1.kern.syscall_setuid 2 2.04% 40.82% # number of syscalls executed +system.cpu1.kern.syscall_getuid 2 2.04% 42.86% # number of syscalls executed +system.cpu1.kern.syscall_access 2 2.04% 44.90% # number of syscalls executed +system.cpu1.kern.syscall_open 13 13.27% 58.16% # number of syscalls executed +system.cpu1.kern.syscall_getgid 2 2.04% 60.20% # number of syscalls executed +system.cpu1.kern.syscall_sigprocmask 3 3.06% 63.27% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 1.02% 64.29% # number of syscalls executed +system.cpu1.kern.syscall_execve 3 3.06% 67.35% # number of syscalls executed +system.cpu1.kern.syscall_mmap 19 19.39% 86.73% # number of syscalls executed +system.cpu1.kern.syscall_munmap 1 1.02% 87.76% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 6 6.12% 93.88% # number of syscalls executed +system.cpu1.kern.syscall_dup2 1 1.02% 94.90% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 2.04% 96.94% # number of syscalls executed +system.cpu1.kern.syscall_setgid 2 2.04% 98.98% # number of syscalls executed +system.cpu1.kern.syscall_getrlimit 1 1.02% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.006021 # Percentage of non-idle cycles system.cpu1.numCycles 0 # number of cpu cycles simulated -system.cpu1.num_insts 18640662 # Number of instructions executed -system.cpu1.num_refs 4633112 # Number of memory references +system.cpu1.num_insts 16976004 # Number of instructions executed +system.cpu1.num_refs 4251312 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 33c194686..2c496b914 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:45:11 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:26:09 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3539435029 because m5_exit instruction encountered +Exiting @ tick 3526987181 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 2a354dee0..7f27ca121 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -58,6 +58,7 @@ mem_mode=timing pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[3] icache_port=system.membus.port[2] @@ -552,6 +554,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 1b99934c9..deba80368 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu.itb @@ -465,6 +467,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -508,6 +511,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console index ea7a20777..d6e3955cc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console @@ -69,7 +69,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -97,10 +97,6 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 480k freed - init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 0adb4cc31..1d45d41a9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,130 +1,127 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 835908 # Simulator instruction rate (inst/s) -host_mem_usage 194192 # Number of bytes of host memory used -host_seconds 71.68 # Real time elapsed on the host -host_tick_rate 48916813 # Simulator tick rate (ticks/s) +host_inst_rate 820839 # Simulator instruction rate (inst/s) +host_mem_usage 193264 # Number of bytes of host memory used +host_seconds 70.65 # Real time elapsed on the host +host_tick_rate 49454399 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 59915182 # Number of instructions simulated -sim_seconds 1.753109 # Number of seconds simulated -sim_ticks 3506218170 # Number of ticks simulated -system.cpu.dtb.accesses 2354955 # DTB accesses -system.cpu.dtb.acv 413 # DTB access violations -system.cpu.dtb.hits 13926686 # DTB hits -system.cpu.dtb.misses 16187 # DTB misses -system.cpu.dtb.read_accesses 832415 # DTB read accesses -system.cpu.dtb.read_acv 242 # DTB read access violations -system.cpu.dtb.read_hits 7716658 # DTB read hits -system.cpu.dtb.read_misses 13695 # DTB read misses -system.cpu.dtb.write_accesses 1522540 # DTB write accesses -system.cpu.dtb.write_acv 171 # DTB write access violations -system.cpu.dtb.write_hits 6210028 # DTB write hits -system.cpu.dtb.write_misses 2492 # DTB write misses -system.cpu.idle_fraction 0.978925 # Percentage of idle cycles -system.cpu.itb.accesses 4037381 # ITB accesses -system.cpu.itb.acv 239 # ITB acv -system.cpu.itb.hits 4030657 # ITB hits -system.cpu.itb.misses 6724 # ITB misses -system.cpu.kern.callpal 183644 # number of callpals executed +sim_insts 57989043 # Number of instructions simulated +sim_seconds 1.746889 # Number of seconds simulated +sim_ticks 3493777466 # Number of ticks simulated +system.cpu.dtb.accesses 2309470 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 13707871 # DTB hits +system.cpu.dtb.misses 12493 # DTB misses +system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 7595606 # DTB read hits +system.cpu.dtb.read_misses 10298 # DTB read misses +system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6112265 # DTB write hits +system.cpu.dtb.write_misses 2195 # DTB write misses +system.cpu.idle_fraction 0.979465 # Percentage of idle cycles +system.cpu.itb.accesses 3281347 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 3276357 # ITB hits +system.cpu.itb.misses 4990 # ITB misses +system.cpu.kern.callpal 182454 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1861 1.01% 1.02% # number of callpals executed -system.cpu.kern.callpal_tbi 28 0.02% 1.03% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 1.03% # number of callpals executed -system.cpu.kern.callpal_swpipl 171635 93.46% 94.50% # number of callpals executed -system.cpu.kern.callpal_rdps 4808 2.62% 97.11% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.11% # number of callpals executed -system.cpu.kern.callpal_wrusp 8 0.00% 97.12% # number of callpals executed -system.cpu.kern.callpal_rdusp 12 0.01% 97.12% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.13% # number of callpals executed -system.cpu.kern.callpal_rti 4297 2.34% 99.47% # number of callpals executed -system.cpu.kern.callpal_callsys 667 0.36% 99.83% # number of callpals executed -system.cpu.kern.callpal_imb 314 0.17% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 1571 0.86% 0.86% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed +system.cpu.kern.callpal_swpipl 171092 93.77% 94.67% # number of callpals executed +system.cpu.kern.callpal_rdps 5160 2.83% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rti 3834 2.10% 99.61% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 209285 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 202524 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1867 # number of quiesce instructions executed -system.cpu.kern.ipl_count 178009 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75254 42.28% 42.28% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 286 0.16% 42.44% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5465 3.07% 45.51% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 97004 54.49% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 159802 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 75188 47.05% 47.05% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 286 0.18% 47.23% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5465 3.42% 50.65% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 78863 49.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3506217640 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3478896122 99.22% 99.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 60705 0.00% 99.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 1274059 0.04% 99.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 25986754 0.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.897719 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999123 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 1876 # number of quiesce instructions executed +system.cpu.kern.ipl_count 176961 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74471 42.08% 42.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 251 0.14% 42.23% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 5439 3.07% 45.30% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 96800 54.70% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 158180 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74417 47.05% 47.05% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 251 0.16% 47.20% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 5439 3.44% 50.64% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 78073 49.36% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3493777020 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3466334940 99.21% 99.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 53019 0.00% 99.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 1268195 0.04% 99.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 26120866 0.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.893869 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.999275 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.812987 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 2339 -system.cpu.kern.mode_good_user 2168 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 4093 # number of protection mode switches -system.cpu.kern.mode_switch_user 2168 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2043 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.563343 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.571463 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.806539 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1938 +system.cpu.kern.mode_good_user 1757 +system.cpu.kern.mode_good_idle 181 +system.cpu.kern.mode_switch_kernel 3323 # number of protection mode switches +system.cpu.kern.mode_switch_user 1757 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2060 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.542857 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.583208 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.083700 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 40644475 1.16% 1.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5527486 0.16% 1.32% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3460045677 98.68% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1862 # number of times the context was actually changed -system.cpu.kern.syscall 475 # number of syscalls executed -system.cpu.kern.syscall_fork 10 2.11% 2.11% # number of syscalls executed -system.cpu.kern.syscall_read 33 6.95% 9.05% # number of syscalls executed -system.cpu.kern.syscall_write 7 1.47% 10.53% # number of syscalls executed -system.cpu.kern.syscall_close 49 10.32% 20.84% # number of syscalls executed -system.cpu.kern.syscall_chdir 1 0.21% 21.05% # number of syscalls executed -system.cpu.kern.syscall_chmod 1 0.21% 21.26% # number of syscalls executed -system.cpu.kern.syscall_obreak 44 9.26% 30.53% # number of syscalls executed -system.cpu.kern.syscall_lseek 13 2.74% 33.26% # number of syscalls executed -system.cpu.kern.syscall_getpid 10 2.11% 35.37% # number of syscalls executed -system.cpu.kern.syscall_setuid 4 0.84% 36.21% # number of syscalls executed -system.cpu.kern.syscall_getuid 8 1.68% 37.89% # number of syscalls executed -system.cpu.kern.syscall_access 4 0.84% 38.74% # number of syscalls executed -system.cpu.kern.syscall_dup 4 0.84% 39.58% # number of syscalls executed -system.cpu.kern.syscall_open 68 14.32% 53.89% # number of syscalls executed -system.cpu.kern.syscall_getgid 8 1.68% 55.58% # number of syscalls executed -system.cpu.kern.syscall_sigprocmask 14 2.95% 58.53% # number of syscalls executed -system.cpu.kern.syscall_ioctl 16 3.37% 61.89% # number of syscalls executed -system.cpu.kern.syscall_readlink 2 0.42% 62.32% # number of syscalls executed -system.cpu.kern.syscall_execve 8 1.68% 64.00% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_stat 31 6.53% 70.53% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_lstat 1 0.21% 70.74% # number of syscalls executed -system.cpu.kern.syscall_mmap 55 11.58% 82.32% # number of syscalls executed -system.cpu.kern.syscall_munmap 6 1.26% 83.58% # number of syscalls executed -system.cpu.kern.syscall_mprotect 14 2.95% 86.53% # number of syscalls executed -system.cpu.kern.syscall_gethostname 2 0.42% 86.95% # number of syscalls executed -system.cpu.kern.syscall_dup2 4 0.84% 87.79% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_fstat 28 5.89% 93.68% # number of syscalls executed -system.cpu.kern.syscall_fcntl 14 2.95% 96.63% # number of syscalls executed -system.cpu.kern.syscall_socket 3 0.63% 97.26% # number of syscalls executed -system.cpu.kern.syscall_connect 3 0.63% 97.89% # number of syscalls executed -system.cpu.kern.syscall_setgid 4 0.84% 98.74% # number of syscalls executed -system.cpu.kern.syscall_getrlimit 3 0.63% 99.37% # number of syscalls executed -system.cpu.kern.syscall_setsid 3 0.63% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.021075 # Percentage of non-idle cycles +system.cpu.kern.mode_switch_good_idle 0.087864 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 39254786 1.12% 1.12% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4685669 0.13% 1.26% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3449836563 98.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 1572 # number of times the context was actually changed +system.cpu.kern.syscall 329 # number of syscalls executed +system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed +system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed +system.cpu.kern.syscall_write 4 1.22% 12.77% # number of syscalls executed +system.cpu.kern.syscall_close 43 13.07% 25.84% # number of syscalls executed +system.cpu.kern.syscall_chdir 1 0.30% 26.14% # number of syscalls executed +system.cpu.kern.syscall_chmod 1 0.30% 26.44% # number of syscalls executed +system.cpu.kern.syscall_obreak 15 4.56% 31.00% # number of syscalls executed +system.cpu.kern.syscall_lseek 10 3.04% 34.04% # number of syscalls executed +system.cpu.kern.syscall_getpid 6 1.82% 35.87% # number of syscalls executed +system.cpu.kern.syscall_setuid 4 1.22% 37.08% # number of syscalls executed +system.cpu.kern.syscall_getuid 6 1.82% 38.91% # number of syscalls executed +system.cpu.kern.syscall_access 11 3.34% 42.25% # number of syscalls executed +system.cpu.kern.syscall_dup 2 0.61% 42.86% # number of syscalls executed +system.cpu.kern.syscall_open 55 16.72% 59.57% # number of syscalls executed +system.cpu.kern.syscall_getgid 6 1.82% 61.40% # number of syscalls executed +system.cpu.kern.syscall_sigprocmask 10 3.04% 64.44% # number of syscalls executed +system.cpu.kern.syscall_ioctl 10 3.04% 67.48% # number of syscalls executed +system.cpu.kern.syscall_readlink 1 0.30% 67.78% # number of syscalls executed +system.cpu.kern.syscall_execve 7 2.13% 69.91% # number of syscalls executed +system.cpu.kern.syscall_mmap 54 16.41% 86.32% # number of syscalls executed +system.cpu.kern.syscall_munmap 3 0.91% 87.23% # number of syscalls executed +system.cpu.kern.syscall_mprotect 16 4.86% 92.10% # number of syscalls executed +system.cpu.kern.syscall_gethostname 1 0.30% 92.40% # number of syscalls executed +system.cpu.kern.syscall_dup2 3 0.91% 93.31% # number of syscalls executed +system.cpu.kern.syscall_fcntl 10 3.04% 96.35% # number of syscalls executed +system.cpu.kern.syscall_socket 2 0.61% 96.96% # number of syscalls executed +system.cpu.kern.syscall_connect 2 0.61% 97.57% # number of syscalls executed +system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.020535 # Percentage of non-idle cycles system.cpu.numCycles 0 # number of cpu cycles simulated -system.cpu.num_insts 59915182 # Number of instructions executed -system.cpu.num_refs 13979549 # Number of memory references +system.cpu.num_insts 57989043 # Number of instructions executed +system.cpu.num_refs 13753099 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 2739943d2..88e69a41f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:43:59 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:24:58 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3506218170 because m5_exit instruction encountered +Exiting @ tick 3493777466 because m5_exit instruction encountered -- cgit v1.2.3 From 84dac99e2ef0c0c4fcf54d0ebba647b60448c049 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 6 Oct 2006 04:23:27 -0400 Subject: add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df --- .../ref/alpha/linux/o3-timing/config.ini | 315 +++++++++++++++++++++ .../ref/alpha/linux/o3-timing/config.out | 308 ++++++++++++++++++++ .../ref/alpha/linux/o3-timing/m5stats.txt | 305 ++++++++++++++++++++ .../ref/alpha/linux/o3-timing/stderr | 6 + .../ref/alpha/linux/o3-timing/stdout | 14 + tests/quick/01.hello-2T-smt/test.py | 32 +++ 6 files changed, 980 insertions(+) create mode 100644 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini create mode 100644 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out create mode 100644 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt create mode 100644 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr create mode 100644 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout create mode 100644 tests/quick/01.hello-2T-smt/test.py (limited to 'tests') diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..bd25cdab9 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,315 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=timing +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=fuPool workload0 workload1 +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload0 system.cpu.workload1 +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.workload0] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.cpu.workload1] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..6d68de2a1 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,308 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=timing + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload0] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.workload1] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload0 system.cpu.workload1 +mem=system.physmem +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..4473a39f8 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,305 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 669 # Number of BTB hits +global.BPredUnit.BTBLookups 3666 # Number of BTB lookups +global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1050 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2479 # Number of conditional branches predicted +global.BPredUnit.lookups 4216 # Number of BP lookups +global.BPredUnit.usedRAS 545 # Number of times the RAS was used to get a target. +host_inst_rate 13879 # Simulator instruction rate (inst/s) +host_mem_usage 150244 # Number of bytes of host memory used +host_seconds 0.82 # Real time elapsed on the host +host_tick_rate 9101 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 25 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 214 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1795 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1734 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1066 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1051 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 11399 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 7478 # Number of ticks simulated +system.cpu.commit.COM:branches 1756 # Number of branches committed +system.cpu.commit.COM:branches_0 878 # Number of branches committed +system.cpu.commit.COM:branches_1 878 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 177 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 7424 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3237 4360.18% + 1 1635 2202.32% + 2 920 1239.22% + 3 476 641.16% + 4 347 467.40% + 5 246 331.36% + 6 206 277.48% + 7 180 242.46% + 8 177 238.42% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 11433 # Number of instructions committed +system.cpu.commit.COM:count_0 5716 # Number of instructions committed +system.cpu.commit.COM:count_1 5717 # Number of instructions committed +system.cpu.commit.COM:loads 1976 # Number of loads committed +system.cpu.commit.COM:loads_0 988 # Number of loads committed +system.cpu.commit.COM:loads_1 988 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 3600 # Number of memory references committed +system.cpu.commit.COM:refs_0 1800 # Number of memory references committed +system.cpu.commit.COM:refs_1 1800 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 789 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 11433 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 6802 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5699 # Number of Instructions Simulated +system.cpu.committedInsts_1 5700 # Number of Instructions Simulated +system.cpu.committedInsts_total 11399 # Number of Instructions Simulated +system.cpu.cpi_0 1.312160 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.311930 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.656022 # CPI: Total CPI of All Threads +system.cpu.decode.DECODE:BlockedCycles 1617 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 282 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 364 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22220 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8058 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3571 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1260 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 277 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4216 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2762 # Number of cache lines fetched +system.cpu.fetch.Cycles 6837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Insts 25142 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1098 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.563712 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2762 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1214 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.361679 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 7479 +system.cpu.fetch.rateDist.min_value 0 + 0 3407 4555.42% + 1 266 355.66% + 2 222 296.83% + 3 265 354.33% + 4 317 423.85% + 5 275 367.70% + 6 279 373.04% + 7 264 352.99% + 8 2184 2920.18% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.iew.EXEC:branches 2294 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1156 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1138 # Number of branches executed +system.cpu.iew.EXEC:nop 59 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 28 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.993582 # Inst execution rate +system.cpu.iew.EXEC:refs 4718 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2364 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2354 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1857 # Number of stores executed +system.cpu.iew.EXEC:stores_0 924 # Number of stores executed +system.cpu.iew.EXEC:stores_1 933 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed +system.cpu.iew.WB:consumers 9920 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 4998 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 4922 # num instructions consuming a value +system.cpu.iew.WB:count 14666 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7373 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7293 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.776915 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.775710 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.778139 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 7707 # num instructions producing a value +system.cpu.iew.WB:producers_0 3877 # num instructions producing a value +system.cpu.iew.WB:producers_1 3830 # num instructions producing a value +system.cpu.iew.WB:rate 1.960957 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.985827 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.975130 # insts written-back per cycle +system.cpu.iew.WB:sent 14753 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7419 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7334 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 869 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 789 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2117 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18235 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2861 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1440 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1421 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 14910 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 807 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 254 # Number of stores squashed +system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 43 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.1.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.1.squashedLoads 746 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 239 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 733 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.762102 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.762236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.524338 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8140 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist +(null) 2 0.02% # Type of FU issued +IntAlu 5556 68.26% # Type of FU issued +IntMult 1 0.01% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 2 0.02% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 1619 19.89% # Type of FU issued +MemWrite 960 11.79% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_1 7958 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.start_dist + (null) 2 0.03% # Type of FU issued + IntAlu 5440 68.36% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1553 19.51% # Type of FU issued + MemWrite 960 12.06% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.end_dist +system.cpu.iq.ISSUE:FU_type 16098 # Type of FU issued +system.cpu.iq.ISSUE:FU_type.start_dist + (null) 4 0.02% # Type of FU issued + IntAlu 10996 68.31% # Type of FU issued + IntMult 2 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 4 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 3172 19.70% # Type of FU issued + MemWrite 1920 11.93% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 101 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.012300 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.006274 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.006026 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 9 4.55% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 114 57.58% # attempts to use FU when none available + MemWrite 75 37.88% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 7479 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 2160 2888.09% + 1 1088 1454.74% + 2 1332 1780.99% + 3 1011 1351.78% + 4 818 1093.73% + 5 568 759.46% + 6 358 478.67% + 7 99 132.37% + 8 45 60.17% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 2.152427 # Inst issue rate +system.cpu.iq.iqInstsAdded 18137 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16098 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 5869 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3337 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.numCycles 7479 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 350 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 8222 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 8416 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26609 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20867 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15602 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3486 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1260 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 771 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7380 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 500 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2217 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..a0835d526 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,6 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: cycle 5368: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 5369: fault (page_table_fault) detected @ PC 0x000000 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..5210b5740 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,14 @@ +Hello world! +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 6 2006 00:21:18 +M5 started Fri Oct 6 02:55:30 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.debug configs/example/se.py -d --cmd=tests/test-progs/hello/bin/alpha/linux/hello;tests/test-progs/hello/bin/alpha/linux/hello +Exiting @ tick 7478 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/test.py b/tests/quick/01.hello-2T-smt/test.py new file mode 100644 index 000000000..04ff8c2e6 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/test.py @@ -0,0 +1,32 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +process1 = LiveProcess(cmd = 'hello', executable = binpath('hello')) +process2 = LiveProcess(cmd = 'hello', executable = binpath('hello')) + +root.system.cpu.workload = [process1, process2] -- cgit v1.2.3 From 984579a6ada65b56c0552c74ef566bd04f59f755 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 7 Oct 2006 11:32:10 -0400 Subject: Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1 --- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 8 + .../00.hello/ref/alpha/linux/o3-timing/config.out | 11 + .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 1663 +------------------- .../00.hello/ref/alpha/linux/o3-timing/stdout | 4 +- .../ref/alpha/linux/simple-atomic/config.ini | 8 + .../ref/alpha/linux/simple-atomic/config.out | 11 + .../00.hello/ref/alpha/linux/simple-atomic/stdout | 4 +- .../ref/alpha/linux/simple-timing/config.ini | 8 + .../ref/alpha/linux/simple-timing/config.out | 11 + .../ref/alpha/linux/simple-timing/m5stats.txt | 10 +- .../00.hello/ref/alpha/linux/simple-timing/stdout | 4 +- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 8 + .../00.hello/ref/alpha/tru64/o3-timing/config.out | 11 + .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 1637 +------------------ .../00.hello/ref/alpha/tru64/o3-timing/stdout | 4 +- .../ref/alpha/tru64/simple-atomic/config.ini | 8 + .../ref/alpha/tru64/simple-atomic/config.out | 11 + .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-atomic/stdout | 4 +- .../ref/alpha/tru64/simple-timing/config.ini | 8 + .../ref/alpha/tru64/simple-timing/config.out | 11 + .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 4 +- .../ref/alpha/linux/o3-timing/config.ini | 141 +- .../ref/alpha/linux/o3-timing/config.out | 129 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 876 ++++++++--- .../ref/alpha/linux/o3-timing/stderr | 2 - .../ref/alpha/linux/o3-timing/stdout | 8 +- .../ref/alpha/eio/simple-atomic/config.ini | 2 + .../ref/alpha/eio/simple-atomic/config.out | 5 + .../ref/alpha/eio/simple-atomic/m5stats.txt | 6 +- .../ref/alpha/eio/simple-atomic/stdout | 4 +- .../ref/alpha/eio/simple-timing/config.ini | 2 + .../ref/alpha/eio/simple-timing/config.out | 5 + .../ref/alpha/eio/simple-timing/m5stats.txt | 8 +- .../ref/alpha/eio/simple-timing/stdout | 4 +- 36 files changed, 1177 insertions(+), 3479 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..903794729 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -389,11 +390,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -409,6 +416,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index f491a3081..2a9a97255 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +214,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -358,6 +365,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +409,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..f6d0699e0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted global.BPredUnit.lookups 2256 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) +host_inst_rate 25564 # Simulator instruction rate (inst/s) +host_mem_usage 160400 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 31189 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. @@ -51,16 +51,16 @@ system.cpu.committedInsts 5623 # Nu system.cpu.committedInsts_total 5623 # Number of Instructions Simulated system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 1539 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1414 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.081222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.064977 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency @@ -75,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # m system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.511236 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2360 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 2049 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.131780 # miss rate for demand accesses system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.072458 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2360 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_hits 2049 # number of overall hits system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.131780 # miss rate for overall accesses system.cpu.dcache.overall_misses 311 # number of overall misses system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.072458 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 2049 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked @@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits 6 # nu system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -223,22 +223,19 @@ system.cpu.icache.total_refs 1255 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:rate 1.157910 # Inst execution rate +system.cpu.iew.EXEC:refs 2596 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 985 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 5411 # num instructions consuming a value +system.cpu.iew.WB:count 7675 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744225 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4027 # num instructions producing a value +system.cpu.iew.WB:rate 1.117014 # insts written-back per cycle +system.cpu.iew.WB:sent 7748 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions @@ -246,6 +243,9 @@ system.cpu.iew.iewDispNonSpecInsts 21 # Nu system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7956 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -257,6 +257,7 @@ system.cpu.iew.lsq.thread.0.forwLoads 55 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed @@ -265,1578 +266,10 @@ system.cpu.iew.predictedNotTakenIncorrect 296 # N system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 8363 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued + IntAlu 5577 66.69% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 1757 21.01% # Type of FU issued + MemWrite 1024 12.24% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.013751 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 1 0.87% # attempts to use FU when none available @@ -1871,26 +304,26 @@ system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% + 0 3761 5473.73% + 1 893 1299.67% + 2 720 1047.88% + 3 615 895.07% + 4 447 650.56% + 5 278 404.60% 6 104 151.36% 7 41 59.67% 8 12 17.46% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.217145 # Inst issue rate system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8363 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 3993 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2571 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fbb329a2f..836a8b7b5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:12:59 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Exiting @ tick 6870 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index f84372165..f7e73950d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +75,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +101,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index a3621a08a..198d7df5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,6 +41,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -48,6 +55,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +99,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 17eea9aed..e26480539 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:14 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:02 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 5641 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 80d2a27e1..cefcf7f11 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +198,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +224,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 09d8f0c22..1ed18ff71 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -67,6 +67,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,6 +80,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -169,6 +176,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +220,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index fe2cd43a5..d7688c435 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113478 # Simulator instruction rate (inst/s) -host_mem_usage 159608 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 165749 # Simulator tick rate (ticks/s) +host_inst_rate 305072 # Simulator instruction rate (inst/s) +host_mem_usage 159668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 439277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 7104aa0ce..3edc94e09 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:15 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:04 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Exiting @ tick 8312 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 790ae6ab3..45904ca08 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -389,11 +390,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -409,6 +416,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 474ea3523..c5cec4f22 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +214,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -358,6 +365,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +409,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index db582e731..9ef54c308 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 159864 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 31894 # Simulator tick rate (ticks/s) +host_inst_rate 47938 # Simulator instruction rate (inst/s) +host_mem_usage 159916 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 57613 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. @@ -222,30 +222,30 @@ system.cpu.icache.tagsinuse 115.538968 # Cy system.cpu.icache.total_refs 550 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 533 # Number of branches executed -system.cpu.iew.EXEC:insts 3123 # Number of executed instructions -system.cpu.iew.EXEC:loads 578 # Number of load instructions executed +system.cpu.iew.EXEC:branches 532 # Number of branches executed system.cpu.iew.EXEC:nop 247 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate -system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate +system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed system.cpu.iew.EXEC:stores 336 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1801 # num instructions consuming a value -system.cpu.iew.WB:count 3070 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back +system.cpu.iew.WB:consumers 1788 # num instructions consuming a value +system.cpu.iew.WB:count 3053 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1425 # num instructions producing a value -system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle -system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1414 # num instructions producing a value +system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle +system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -257,1586 +257,19 @@ system.cpu.iew.lsq.thread.0.forwLoads 30 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2317 70.83% # Type of FU issued + IntAlu 2308 70.86% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 609 18.62% # Type of FU issued - MemWrite 344 10.52% # Type of FU issued + MemRead 605 18.58% # Type of FU issued + MemWrite 343 10.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 5 12.50% # attempts to use FU when none available @@ -1871,11 +304,11 @@ system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1603 5552.48% - 1 434 1503.29% - 2 301 1042.60% - 3 220 762.04% - 4 167 578.46% + 0 1607 5566.33% + 1 435 1506.75% + 2 298 1032.21% + 3 221 765.50% + 4 164 568.06% 5 94 325.60% 6 46 159.33% 7 15 51.96% @@ -1883,14 +316,14 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued +system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency @@ -1900,8 +333,8 @@ system.cpu.l2cache.ReadReq_misses 274 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 708b9587a..535ca4503 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:16 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:07 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 1ec052afb..34f5c0b32 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +75,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +101,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index ae24ae2a8..a474765ae 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,6 +41,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -48,6 +55,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +99,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index b4747f1f4..b120e12b9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 46556 # Simulator instruction rate (inst/s) -host_mem_usage 147672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 46204 # Simulator tick rate (ticks/s) +host_inst_rate 548861 # Simulator instruction rate (inst/s) +host_mem_usage 147820 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 504404 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 438e330f5..0c9b00960 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:09 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index e833d841e..0d7d34e64 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +198,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +224,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 1914b47e7..9b44f8ddd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -67,6 +67,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,6 +80,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -169,6 +176,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +220,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 47bcc1b3c..388ca35bb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 73626 # Simulator instruction rate (inst/s) -host_mem_usage 159128 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 106590 # Simulator tick rate (ticks/s) +host_inst_rate 250729 # Simulator instruction rate (inst/s) +host_mem_usage 159188 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 352925 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 4a02e57f0..81169c6d0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:10 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index bd25cdab9..5b6a4c7ff 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -49,12 +49,12 @@ text_file=m5stats.txt [system] type=System children=cpu membus physmem -mem_mode=timing +mem_mode=atomic physmem=system.physmem [system.cpu] type=DerivO3CPU -children=fuPool workload0 workload1 +children=dcache fuPool icache l2cache toL2Bus workload0 workload1 BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -102,7 +102,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.physmem +mem=system.cpu.dcache numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -122,8 +122,48 @@ trapLatency=13 wbDepth=1 wbWidth=8 workload=system.cpu.workload0 system.cpu.workload1 -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.fuPool] type=FUPool @@ -262,9 +302,94 @@ issueLat=3 opClass=IprAccess opLat=3 +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + [system.cpu.workload0] type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello +cmd=hello egid=100 env= euid=100 @@ -279,7 +404,7 @@ uid=100 [system.cpu.workload1] type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello +cmd=hello egid=100 env= euid=100 @@ -295,7 +420,7 @@ uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index 6d68de2a1..bfdd7bcde 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -14,7 +14,7 @@ latency=1 [system] type=System physmem=system.physmem -mem_mode=timing +mem_mode=atomic [system.membus] type=Bus @@ -22,7 +22,7 @@ bus_id=0 [system.cpu.workload0] type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello +cmd=hello executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout @@ -37,7 +37,7 @@ ppid=99 [system.cpu.workload1] type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello +cmd=hello executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout @@ -50,6 +50,45 @@ egid=100 pid=100 ppid=99 +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + [system.cpu.fuPool.FUList0.opList0] type=OpDesc opClass=IntAlu @@ -184,7 +223,7 @@ clock=1 numThreads=1 activity=0 workload=system.cpu.workload0 system.cpu.workload1 -mem=system.physmem +mem=system.cpu.dcache checker=null max_insts_any_thread=0 max_insts_all_threads=0 @@ -256,6 +295,88 @@ defer_registration=false function_trace=false function_trace_start=0 +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + [trace] flags= start=0 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 4473a39f8..bfecc213d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,230 +1,550 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 669 # Number of BTB hits -global.BPredUnit.BTBLookups 3666 # Number of BTB lookups -global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1050 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2479 # Number of conditional branches predicted -global.BPredUnit.lookups 4216 # Number of BP lookups -global.BPredUnit.usedRAS 545 # Number of times the RAS was used to get a target. -host_inst_rate 13879 # Simulator instruction rate (inst/s) -host_mem_usage 150244 # Number of bytes of host memory used -host_seconds 0.82 # Real time elapsed on the host -host_tick_rate 9101 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 25 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 214 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1795 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1734 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1066 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1051 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 638 # Number of BTB hits +global.BPredUnit.BTBLookups 3591 # Number of BTB lookups +global.BPredUnit.RASInCorrect 96 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1078 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2445 # Number of conditional branches predicted +global.BPredUnit.lookups 4165 # Number of BP lookups +global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. +host_inst_rate 26570 # Simulator instruction rate (inst/s) +host_mem_usage 161280 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host +host_tick_rate 19898 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1873 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1836 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1110 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11399 # Number of instructions simulated +sim_insts 11247 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 7478 # Number of ticks simulated -system.cpu.commit.COM:branches 1756 # Number of branches committed -system.cpu.commit.COM:branches_0 878 # Number of branches committed -system.cpu.commit.COM:branches_1 878 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 177 # number cycles where commit BW limit reached +sim_ticks 8429 # Number of ticks simulated +system.cpu.commit.COM:branches 1724 # Number of branches committed +system.cpu.commit.COM:branches_0 862 # Number of branches committed +system.cpu.commit.COM:branches_1 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 125 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 7424 +system.cpu.commit.COM:committed_per_cycle.samples 8381 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3237 4360.18% - 1 1635 2202.32% - 2 920 1239.22% - 3 476 641.16% - 4 347 467.40% - 5 246 331.36% - 6 206 277.48% - 7 180 242.46% - 8 177 238.42% + 0 3942 4703.50% + 1 1903 2270.61% + 2 930 1109.65% + 3 517 616.87% + 4 373 445.05% + 5 236 281.59% + 6 190 226.70% + 7 165 196.87% + 8 125 149.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 11433 # Number of instructions committed -system.cpu.commit.COM:count_0 5716 # Number of instructions committed -system.cpu.commit.COM:count_1 5717 # Number of instructions committed -system.cpu.commit.COM:loads 1976 # Number of loads committed -system.cpu.commit.COM:loads_0 988 # Number of loads committed -system.cpu.commit.COM:loads_1 988 # Number of loads committed +system.cpu.commit.COM:count 11281 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed +system.cpu.commit.COM:loads 1958 # Number of loads committed +system.cpu.commit.COM:loads_0 979 # Number of loads committed +system.cpu.commit.COM:loads_1 979 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3600 # Number of memory references committed -system.cpu.commit.COM:refs_0 1800 # Number of memory references committed -system.cpu.commit.COM:refs_1 1800 # Number of memory references committed +system.cpu.commit.COM:refs 3582 # Number of memory references committed +system.cpu.commit.COM:refs_0 1791 # Number of memory references committed +system.cpu.commit.COM:refs_1 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 789 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 11433 # The number of committed instructions +system.cpu.commit.branchMispredicts 829 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6802 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5699 # Number of Instructions Simulated -system.cpu.committedInsts_1 5700 # Number of Instructions Simulated -system.cpu.committedInsts_total 11399 # Number of Instructions Simulated -system.cpu.cpi_0 1.312160 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.311930 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656022 # CPI: Total CPI of All Threads -system.cpu.decode.DECODE:BlockedCycles 1617 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 282 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 364 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22220 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8058 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3571 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1260 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 277 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4216 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2762 # Number of cache lines fetched -system.cpu.fetch.Cycles 6837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.Insts 25142 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1098 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.563712 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2762 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1214 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 3.361679 # Number of inst fetches per cycle +system.cpu.commit.commitSquashedInsts 7542 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated +system.cpu.committedInsts_total 11247 # Number of Instructions Simulated +system.cpu.cpi_0 1.499022 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.498755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.749444 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2921 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 1470 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_1 1451 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.100000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 3.162393 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_1 3.035398 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.251282 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.323232 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_1 2.177083 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 1353 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_1 1338 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 370 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_1 343 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.078740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.079592 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_1 0.077877 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_1 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 18 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_1 17 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 230 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_1 209 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066758 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067347 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_1 0.066161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_1 96 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1642 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 830 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_1 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.649842 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 2.533333 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_1 2.776316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.076389 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.069444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_1 2.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1325 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 665 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_1 660 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 840 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 418 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_1 422 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.193057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.198795 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_1 0.187192 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 165 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_1 152 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 79 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_1 80 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 299 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 149 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_1 150 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.087698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.086747 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_1 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_0 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_1 72 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.376771 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 4563 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 2300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_1 2263 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.839122 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 2.794326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_1 2.886792 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 2018 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_1 1998 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1553 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 788 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_1 765 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.119877 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.122609 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 0.117101 # miss rate for demand accesses +system.cpu.dcache.demand_misses 547 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 282 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_1 265 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_1 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 379 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_1 359 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.074293 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.074348 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 0.074238 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 339 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_1 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 4563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 2300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_1 2263 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.839122 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 2.794326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_1 2.886792 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 4016 # number of overall hits +system.cpu.dcache.overall_hits_0 2018 # number of overall hits +system.cpu.dcache.overall_hits_1 1998 # number of overall hits +system.cpu.dcache.overall_miss_latency 1553 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 788 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_1 765 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.119877 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.122609 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 0.117101 # miss rate for overall accesses +system.cpu.dcache.overall_misses 547 # number of overall misses +system.cpu.dcache.overall_misses_0 282 # number of overall misses +system.cpu.dcache.overall_misses_1 265 # number of overall misses +system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_1 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 738 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 379 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_1 359 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.074293 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.074348 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 0.074238 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 339 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_1 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.replacements_0 0 # number of replacements +system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 236.409371 # Cycle average of tags in use +system.cpu.dcache.total_refs 4016 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks_0 0 # number of writebacks +system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1676 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 270 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22636 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9654 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3745 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 246 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 110 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4165 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2863 # Number of cache lines fetched +system.cpu.fetch.Cycles 6949 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 197 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 25207 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1140 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.494069 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1188 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.990154 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7479 +system.cpu.fetch.rateDist.samples 8430 system.cpu.fetch.rateDist.min_value 0 - 0 3407 4555.42% - 1 266 355.66% - 2 222 296.83% - 3 265 354.33% - 4 317 423.85% - 5 275 367.70% - 6 279 373.04% - 7 264 352.99% - 8 2184 2920.18% + 0 4345 5154.21% + 1 273 323.84% + 2 232 275.21% + 3 245 290.63% + 4 309 366.55% + 5 277 328.59% + 6 293 347.57% + 7 292 346.38% + 8 2164 2567.02% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.iew.EXEC:branches 2294 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1156 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1138 # Number of branches executed -system.cpu.iew.EXEC:nop 59 # number of nop insts executed +system.cpu.icache.ReadReq_accesses 2863 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 1463 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_1 1400 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 2.974441 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_1 2.990323 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.993548 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_1 1.996764 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2240 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 1150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_1 1090 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 931 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_1 927 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.217604 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.213944 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_1 0.221429 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 313 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_1 310 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 3 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_1 1 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 618 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_1 617 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.216207 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.211893 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_1 0.220714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_1 309 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.618740 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2863 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 1463 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_1 1400 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 2.974441 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_1 2.990323 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency +system.cpu.icache.demand_hits 2240 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 1150 # number of demand (read+write) hits +system.cpu.icache.demand_hits_1 1090 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 931 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_1 927 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.217604 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.213944 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 0.221429 # miss rate for demand accesses +system.cpu.icache.demand_misses 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 313 # number of demand (read+write) misses +system.cpu.icache.demand_misses_1 310 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 3 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_1 1 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 618 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_1 617 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.216207 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.211893 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 0.220714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_1 309 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2863 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 1463 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_1 1400 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 2.974441 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_1 2.990323 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2240 # number of overall hits +system.cpu.icache.overall_hits_0 1150 # number of overall hits +system.cpu.icache.overall_hits_1 1090 # number of overall hits +system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 931 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_1 927 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.217604 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.213944 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 0.221429 # miss rate for overall accesses +system.cpu.icache.overall_misses 623 # number of overall misses +system.cpu.icache.overall_misses_0 313 # number of overall misses +system.cpu.icache.overall_misses_1 310 # number of overall misses +system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 3 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_1 1 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 618 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_1 617 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.216207 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.211893 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 0.220714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_1 309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 332.781969 # Cycle average of tags in use +system.cpu.icache.total_refs 2240 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.writebacks_0 0 # number of writebacks +system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.iew.EXEC:branches 2317 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1161 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1156 # Number of branches executed +system.cpu.iew.EXEC:nop 65 # number of nop insts executed system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 28 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.993582 # Inst execution rate -system.cpu.iew.EXEC:refs 4718 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2364 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2354 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1857 # Number of stores executed -system.cpu.iew.EXEC:stores_0 924 # Number of stores executed -system.cpu.iew.EXEC:stores_1 933 # Number of stores executed +system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.816845 # Inst execution rate +system.cpu.iew.EXEC:refs 4932 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2476 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2456 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1873 # Number of stores executed +system.cpu.iew.EXEC:stores_0 938 # Number of stores executed +system.cpu.iew.EXEC:stores_1 935 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9920 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 4998 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 4922 # num instructions consuming a value -system.cpu.iew.WB:count 14666 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7373 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7293 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.776915 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.775710 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.778139 # average fanout of values written-back +system.cpu.iew.WB:consumers 9998 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5018 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 4980 # num instructions consuming a value +system.cpu.iew.WB:count 14809 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7426 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7383 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.777255 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776206 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.778313 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7707 # num instructions producing a value -system.cpu.iew.WB:producers_0 3877 # num instructions producing a value -system.cpu.iew.WB:producers_1 3830 # num instructions producing a value -system.cpu.iew.WB:rate 1.960957 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.985827 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.975130 # insts written-back per cycle -system.cpu.iew.WB:sent 14753 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7419 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7334 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 869 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 789 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2117 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18235 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2861 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1440 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1188 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 14910 # Number of executed instructions +system.cpu.iew.WB:producers 7771 # num instructions producing a value +system.cpu.iew.WB:producers_0 3895 # num instructions producing a value +system.cpu.iew.WB:producers_1 3876 # num instructions producing a value +system.cpu.iew.WB:rate 1.756702 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.880902 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.875801 # insts written-back per cycle +system.cpu.iew.WB:sent 14942 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7492 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7450 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 921 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3709 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 562 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2218 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18824 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3059 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1538 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1521 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 941 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15316 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1395 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 807 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 254 # Number of stores squashed +system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 894 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 298 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 43 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 44 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 746 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 239 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 56 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 733 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.762102 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.762236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.524338 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8140 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 857 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 763 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.667102 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.667220 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.334322 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8176 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist -(null) 2 0.02% # Type of FU issued -IntAlu 5556 68.26% # Type of FU issued -IntMult 1 0.01% # Type of FU issued -IntDiv 0 0.00% # Type of FU issued -FloatAdd 2 0.02% # Type of FU issued -FloatCmp 0 0.00% # Type of FU issued -FloatCvt 0 0.00% # Type of FU issued -FloatMult 0 0.00% # Type of FU issued -FloatDiv 0 0.00% # Type of FU issued -FloatSqrt 0 0.00% # Type of FU issued -MemRead 1619 19.89% # Type of FU issued -MemWrite 960 11.79% # Type of FU issued -IprAccess 0 0.00% # Type of FU issued -InstPrefetch 0 0.00% # Type of FU issued + (null) 2 0.02% # Type of FU issued + IntAlu 5526 67.59% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1667 20.39% # Type of FU issued + MemWrite 978 11.96% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 7958 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8081 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist - (null) 2 0.03% # Type of FU issued - IntAlu 5440 68.36% # Type of FU issued + (null) 2 0.02% # Type of FU issued + IntAlu 5475 67.75% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.03% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1553 19.51% # Type of FU issued - MemWrite 960 12.06% # Type of FU issued + MemRead 1638 20.27% # Type of FU issued + MemWrite 963 11.92% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16098 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16257 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 10996 68.31% # Type of FU issued + IntAlu 11001 67.67% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -233,20 +553,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3172 19.70% # Type of FU issued - MemWrite 1920 11.93% # Type of FU issued + MemRead 3305 20.33% # Type of FU issued + MemWrite 1941 11.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 101 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012300 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 185 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 102 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 83 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011380 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate_0 0.006274 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.006026 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005105 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 9 4.55% # attempts to use FU when none available + IntAlu 10 5.41% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -255,49 +575,189 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 114 57.58% # attempts to use FU when none available - MemWrite 75 37.88% # attempts to use FU when none available + MemRead 105 56.76% # attempts to use FU when none available + MemWrite 70 37.84% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7479 +system.cpu.iq.ISSUE:issued_per_cycle.samples 8430 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2160 2888.09% - 1 1088 1454.74% - 2 1332 1780.99% - 3 1011 1351.78% - 4 818 1093.73% - 5 568 759.46% - 6 358 478.67% - 7 99 132.37% - 8 45 60.17% + 0 2671 3168.45% + 1 1437 1704.63% + 2 1466 1739.03% + 3 1108 1314.35% + 4 752 892.05% + 5 584 692.76% + 6 285 338.08% + 7 90 106.76% + 8 37 43.89% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.152427 # Inst issue rate -system.cpu.iq.iqInstsAdded 18137 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16098 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 5869 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3337 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.numCycles 7479 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 350 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 8222 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8416 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26609 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 20867 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15602 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3486 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1260 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 771 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7380 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 500 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2217 # count of insts added to the skid buffer +system.cpu.iq.ISSUE:rate 1.928470 # Inst issue rate +system.cpu.iq.iqInstsAdded 18719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16257 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6696 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4128 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 972 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 495 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_1 477 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.035160 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.020325 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_1 2.050526 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_1 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_1 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1968 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 994 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_1 974 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994856 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.993939 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_1 0.995807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 967 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_1 475 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 953 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 478 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_1 475 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980453 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.965657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_1 0.995807 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_1 475 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005171 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 972 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 495 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_1 477 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.035160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 2.020325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_1 2.050526 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_1 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1968 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 994 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_1 974 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.994856 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.993939 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 0.995807 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 967 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 492 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_1 475 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 953 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 478 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_1 475 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.980453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.965657 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 0.995807 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_1 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 972 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 495 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_1 477 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.035160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 2.020325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_1 2.050526 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_1 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits +system.cpu.l2cache.overall_hits_1 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1968 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 994 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_1 974 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.994856 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.993939 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 0.995807 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 967 # number of overall misses +system.cpu.l2cache.overall_misses_0 492 # number of overall misses +system.cpu.l2cache.overall_misses_1 475 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 953 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 478 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_1 475 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.980453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.965657 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 0.995807 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 478 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_1 475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.replacements_0 0 # number of replacements +system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.sampled_refs 967 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 569.253381 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks_0 0 # number of writebacks +system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.numCycles 8430 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 9956 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 693 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21059 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15731 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3562 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7629 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 556 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1898 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index a0835d526..890488cd2 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -2,5 +2,3 @@ warn: Entering event queue @ 0. Starting simulation... warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 -warn: cycle 5368: fault (page_table_fault) detected @ PC 0x000000 -warn: cycle 5369: fault (page_table_fault) detected @ PC 0x000000 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 5210b5740..29d3771fb 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 6 2006 00:21:18 -M5 started Fri Oct 6 02:55:30 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:13 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.debug configs/example/se.py -d --cmd=tests/test-progs/hello/bin/alpha/linux/hello;tests/test-progs/hello/bin/alpha/linux/hello -Exiting @ tick 7478 because target called exit() +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Exiting @ tick 8429 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index a4b103732..8722c1b67 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -92,6 +93,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 8f236d9cc..6ae80aecf 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -33,6 +33,7 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -46,6 +47,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -89,3 +91,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 0132ecf1b..9fdf1d513 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1397534 # Simulator instruction rate (inst/s) -host_mem_usage 147632 # Number of bytes of host memory used +host_inst_rate 1393697 # Simulator instruction rate (inst/s) +host_mem_usage 147652 # Number of bytes of host memory used host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 1395943 # Simulator tick rate (ticks/s) +host_tick_rate 1391995 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index d3edcdc0a..207a0046c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:17 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 27568ad50..f4bdc8171 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -215,6 +216,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index ba6875a7b..71a6d33c4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -72,6 +72,7 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -167,6 +168,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -210,3 +212,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 6339e48b7..9a723049a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 620120 # Simulator instruction rate (inst/s) -host_mem_usage 159196 # Number of bytes of host memory used -host_seconds 0.81 # Real time elapsed on the host -host_tick_rate 845850 # Simulator tick rate (ticks/s) +host_inst_rate 309857 # Simulator instruction rate (inst/s) +host_mem_usage 159252 # Number of bytes of host memory used +host_seconds 1.61 # Real time elapsed on the host +host_tick_rate 422749 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 158dcfe2b..91e0bd147 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:19 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Exiting @ tick 682354 because a thread reached the max instruction count -- cgit v1.2.3 From 413a5379b86729d298d666f9ff2b51d2ed1d4463 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sat, 7 Oct 2006 12:58:37 -0400 Subject: Update stats for change in functional path in cache --HG-- extra : convert_revision : 5abc964ca95b80522266c5c1bc5e661d41f2798a --- .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 308 ++++---- .../00.hello/ref/alpha/linux/o3-timing/stdout | 6 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 144 ++-- .../00.hello/ref/alpha/linux/simple-timing/stdout | 6 +- .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 38 +- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 4 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 34 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 4 +- .../ref/mips/linux/simple-timing/m5stats.txt | 146 ++-- .../00.hello/ref/mips/linux/simple-timing/stdout | 6 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 857 ++++++++++----------- .../ref/alpha/linux/o3-timing/stdout | 6 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 146 ++-- .../ref/alpha/eio/simple-timing/stdout | 6 +- 14 files changed, 840 insertions(+), 871 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index f6d0699e0..c2c9affca 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -2,39 +2,39 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.BTBLookups 1936 # Number of BTB lookups global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted +global.BPredUnit.lookups 2254 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 25564 # Simulator instruction rate (inst/s) -host_mem_usage 160400 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 31189 # Simulator tick rate (ticks/s) +host_inst_rate 47059 # Simulator instruction rate (inst/s) +host_mem_usage 160380 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 57322 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated +sim_ticks 6868 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 6115 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 3908 6390.84% + 1 1063 1738.35% + 2 389 636.14% + 3 210 343.42% + 4 152 248.57% + 5 94 153.72% + 6 76 124.28% + 7 149 243.66% + 8 74 121.01% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1414 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.064977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.511236 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2360 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2049 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072458 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses +system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2360 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2049 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072458 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2040 # number of overall hits +system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses +system.cpu.dcache.overall_misses 308 # number of overall misses +system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,43 +119,43 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2049 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use +system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 6869 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 4548 6621.05% + 1 174 253.31% + 2 186 270.78% + 3 157 228.56% + 4 211 307.18% + 5 153 222.74% + 6 171 248.94% + 7 105 152.86% + 8 1164 1694.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist @@ -218,38 +218,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iew.EXEC:branches 1206 # Number of branches executed system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.157910 # Inst execution rate -system.cpu.iew.EXEC:refs 2596 # number of memory reference insts executed +system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate +system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed system.cpu.iew.EXEC:stores 985 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5411 # num instructions consuming a value -system.cpu.iew.WB:count 7675 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744225 # average fanout of values written-back +system.cpu.iew.WB:consumers 5409 # num instructions consuming a value +system.cpu.iew.WB:count 7670 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4027 # num instructions producing a value -system.cpu.iew.WB:rate 1.117014 # insts written-back per cycle -system.cpu.iew.WB:sent 7748 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4025 # num instructions producing a value +system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle +system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7956 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked @@ -259,17 +259,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8363 # Type of FU issued +system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5577 66.69% # Type of FU issued + IntAlu 5573 66.67% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -278,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 21.01% # Type of FU issued - MemWrite 1024 12.24% # Type of FU issued + MemRead 1757 21.02% # Type of FU issued + MemWrite 1024 12.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013751 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 1 0.87% # attempts to use FU when none available @@ -302,72 +302,74 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6869 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3761 5473.73% - 1 893 1299.67% - 2 720 1047.88% - 3 615 895.07% - 4 447 650.56% - 5 278 404.60% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 3761 5475.32% + 1 891 1297.13% + 2 720 1048.19% + 3 617 898.24% + 4 445 647.84% + 5 278 404.72% + 6 104 151.40% + 7 41 59.69% + 8 12 17.47% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.217145 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8363 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate +system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3993 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.008130 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_accesses 496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.991935 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.991935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_accesses 496 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 4 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.991935 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 492 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.991935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,22 +382,22 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.numCycles 6869 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 836a8b7b5..14ef519e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:12:59 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:34 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +Exiting @ tick 6868 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index d7688c435..97d39456e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 305072 # Simulator instruction rate (inst/s) -host_mem_usage 159668 # Number of bytes of host memory used +host_inst_rate 286207 # Simulator instruction rate (inst/s) +host_mem_usage 159648 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 439277 # Simulator tick rate (ticks/s) +host_tick_rate 413300 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8312 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 981 # number of ReadReq accesses(hits+misses) +sim_ticks 8316 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 891 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 270 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.091743 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 180 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.091743 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.737500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.097442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 80 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1632 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 489 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.094340 # miss rate for demand accesses -system.cpu.dcache.demand_misses 170 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses +system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.090455 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1632 # number of overall hits -system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses -system.cpu.dcache.overall_misses 170 # number of overall misses +system.cpu.dcache.overall_hits 1626 # number of overall hits +system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses +system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.090455 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.055094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1632 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use +system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) @@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.267292 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.968610 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 878 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997763 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 446 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.982103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002242 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006803 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 878 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.993243 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 439 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.982103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.993243 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 446 # number of overall misses +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.993243 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 439 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.982103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.993243 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 245.259112 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 3edc94e09..a9c37a14d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:04 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:38 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 8312 because target called exit() +Exiting @ tick 8316 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 9ef54c308..53d94a43f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 47938 # Simulator instruction rate (inst/s) -host_mem_usage 159916 # Number of bytes of host memory used +host_inst_rate 45832 # Simulator instruction rate (inst/s) +host_mem_usage 159900 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 57613 # Simulator tick rate (ticks/s) +host_tick_rate 55090 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. @@ -51,16 +51,16 @@ system.cpu.committedInsts 2387 # Nu system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency @@ -75,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 706 # number of overall hits +system.cpu.dcache.overall_hits 705 # number of overall hits system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses system.cpu.dcache.overall_misses 123 # number of overall misses system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use -system.cpu.dcache.total_refs 706 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 705 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked @@ -333,8 +333,8 @@ system.cpu.l2cache.ReadReq_misses 274 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 535ca4503..fa94f7eb9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:07 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:40 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 388ca35bb..916f9dad8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,22 +1,22 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 250729 # Simulator instruction rate (inst/s) -host_mem_usage 159188 # Number of bytes of host memory used +host_inst_rate 196989 # Simulator instruction rate (inst/s) +host_mem_usage 159172 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 352925 # Simulator tick rate (ticks/s) +host_tick_rate 279840 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated sim_ticks 3777 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency @@ -30,37 +30,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # m system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 628 # number of overall hits +system.cpu.dcache.overall_hits 627 # number of overall hits system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -77,7 +77,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use -system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 81169c6d0..d152dc89c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:10 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:45 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 5d054b950..bc5ad3cca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 129834 # Simulator instruction rate (inst/s) -host_mem_usage 158964 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 194881 # Simulator tick rate (ticks/s) +host_inst_rate 273933 # Simulator instruction rate (inst/s) +host_mem_usage 159012 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 403699 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8573 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +sim_ticks 8579 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.586207 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 387 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses -system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses +system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1927 # number of overall hits -system.cpu.dcache.overall_miss_latency 387 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses -system.cpu.dcache.overall_misses 137 # number of overall misses +system.cpu.dcache.overall_hits 1922 # number of overall hits +system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses +system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use -system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use +system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) @@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use +system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 1 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 1 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006928 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.993119 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.993119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 438 # number of overall misses +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.993119 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.993119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 11009935d..954193ee0 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:37:09 -M5 started Tue Sep 5 15:46:32 2006 +M5 compiled Oct 7 2006 12:52:26 +M5 started Sat Oct 7 12:52:42 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 8573 because target called exit() +Exiting @ tick 8579 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index bfecc213d..a249947ca 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 638 # Number of BTB hits -global.BPredUnit.BTBLookups 3591 # Number of BTB lookups -global.BPredUnit.RASInCorrect 96 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1078 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2445 # Number of conditional branches predicted -global.BPredUnit.lookups 4165 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 26570 # Simulator instruction rate (inst/s) -host_mem_usage 161280 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -host_tick_rate 19898 # Simulator tick rate (ticks/s) +global.BPredUnit.BTBHits 642 # Number of BTB hits +global.BPredUnit.BTBLookups 3598 # Number of BTB lookups +global.BPredUnit.RASInCorrect 99 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1081 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2449 # Number of conditional branches predicted +global.BPredUnit.lookups 4173 # Number of BP lookups +global.BPredUnit.usedRAS 551 # Number of times the RAS was used to get a target. +host_inst_rate 50082 # Simulator instruction rate (inst/s) +host_mem_usage 161260 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 37535 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1873 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1836 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1110 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1868 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1109 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8429 # Number of ticks simulated +sim_ticks 8441 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 125 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 126 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8381 +system.cpu.commit.COM:committed_per_cycle.samples 8393 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3942 4703.50% - 1 1903 2270.61% - 2 930 1109.65% - 3 517 616.87% - 4 373 445.05% - 5 236 281.59% - 6 190 226.70% - 7 165 196.87% - 8 125 149.15% + 0 3957 4714.64% + 1 1909 2274.51% + 2 919 1094.96% + 3 516 614.80% + 4 375 446.80% + 5 235 280.00% + 6 189 225.19% + 7 167 198.98% + 8 126 150.13% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,164 +61,142 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 829 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 832 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7542 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7525 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.499022 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.498755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.749444 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2921 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 1470 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_1 1451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.100000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 3.162393 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_1 3.035398 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.251282 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.323232 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_1 2.177083 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2691 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 1353 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_1 1338 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 713 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 370 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_1 343 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.078740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.079592 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_1 0.077877 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 230 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_1 113 # number of ReadReq misses +system.cpu.cpi_0 1.501156 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.500889 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750511 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 3.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.231156 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.231156 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2682 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2682 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 720 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 720 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.080247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 234 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 18 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_1 17 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 230 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_1 209 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066758 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067347 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_1 0.066161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_1 96 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 830 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_1 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.649842 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 2.533333 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_1 2.776316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.076389 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.069444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_1 2.083333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1325 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 665 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_1 660 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 840 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 418 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_1 422 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.193057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.198795 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_1 0.187192 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 165 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_1 152 # number of WriteReq misses +system.cpu.dcache.ReadReq_mshr_hits_0 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 444 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 444 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 303 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 303 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 79 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_1 80 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 299 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 149 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_1 150 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.087698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.086747 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate_1 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits_0 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.088670 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_0 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_1 72 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.376771 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.670554 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4563 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 2300 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_1 2263 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.839122 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 2.794326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_1 2.886792 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 2018 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_1 1998 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1553 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 788 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_1 765 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.119877 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.122609 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_1 0.117101 # miss rate for demand accesses -system.cpu.dcache.demand_misses 547 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 282 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_1 265 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 4540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1557 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 1557 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.118282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.118282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses +system.cpu.dcache.demand_misses 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_1 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 738 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 379 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_1 359 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.074293 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.074348 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_1 0.074238 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 339 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_1 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_hits_0 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075551 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075551 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 2300 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_1 2263 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.839122 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 2.794326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_1 2.886792 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4016 # number of overall hits -system.cpu.dcache.overall_hits_0 2018 # number of overall hits -system.cpu.dcache.overall_hits_1 1998 # number of overall hits -system.cpu.dcache.overall_miss_latency 1553 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 788 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_1 765 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.119877 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.122609 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_1 0.117101 # miss rate for overall accesses -system.cpu.dcache.overall_misses 547 # number of overall misses -system.cpu.dcache.overall_misses_0 282 # number of overall misses -system.cpu.dcache.overall_misses_1 265 # number of overall misses +system.cpu.dcache.overall_hits 4003 # number of overall hits +system.cpu.dcache.overall_hits_0 4003 # number of overall hits +system.cpu.dcache.overall_hits_1 0 # number of overall hits +system.cpu.dcache.overall_miss_latency 1557 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 1557 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.118282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.118282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.dcache.overall_misses 537 # number of overall misses +system.cpu.dcache.overall_misses_0 537 # number of overall misses +system.cpu.dcache.overall_misses_1 0 # number of overall misses system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_1 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 738 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 379 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_1 359 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.074293 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.074348 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 0.074238 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_1 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_hits_0 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles @@ -237,165 +215,154 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 236.409371 # Cycle average of tags in use -system.cpu.dcache.total_refs 4016 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 226.419332 # Cycle average of tags in use +system.cpu.dcache.total_refs 4003 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1676 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1682 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 270 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22636 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 9654 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3745 # Number of cycles decode is running +system.cpu.decode.DECODE:BranchResolved 368 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22713 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9663 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3758 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 246 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 110 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4165 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2863 # Number of cache lines fetched -system.cpu.fetch.Cycles 6949 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 197 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25207 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1140 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.494069 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2863 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1188 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.990154 # Number of inst fetches per cycle +system.cpu.decode.DECODE:SquashedInsts 233 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 106 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4173 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2872 # Number of cache lines fetched +system.cpu.fetch.Cycles 6967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 203 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 25244 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1143 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.494314 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.990287 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 8430 +system.cpu.fetch.rateDist.samples 8442 system.cpu.fetch.rateDist.min_value 0 - 0 4345 5154.21% - 1 273 323.84% - 2 232 275.21% - 3 245 290.63% - 4 309 366.55% - 5 277 328.59% - 6 293 347.57% - 7 292 346.38% - 8 2164 2567.02% + 0 4348 5150.44% + 1 274 324.57% + 2 232 274.82% + 3 248 293.77% + 4 311 368.40% + 5 277 328.12% + 6 296 350.63% + 7 291 344.71% + 8 2165 2564.56% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2863 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 1463 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_1 1400 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 2872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2872 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 2.974441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_1 2.990323 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 2.982343 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.993548 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_1 1.996764 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2240 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 1150 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_1 1090 # number of ReadReq hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2249 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 931 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_1 927 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.217604 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.213944 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_1 0.221429 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_latency_0 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.216922 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.216922 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 313 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_1 310 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 3 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_1 1 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 4 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 618 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_1 617 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.216207 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.211893 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_1 0.220714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency_0 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.215529 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215529 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 310 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_1 309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.618740 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.633279 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2863 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 1463 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_1 1400 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 2.974441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_1 2.990323 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency -system.cpu.icache.demand_hits 2240 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 1150 # number of demand (read+write) hits -system.cpu.icache.demand_hits_1 1090 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.icache.demand_hits 2249 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2249 # number of demand (read+write) hits +system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 931 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_1 927 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.217604 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.213944 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_1 0.221429 # miss rate for demand accesses +system.cpu.icache.demand_miss_latency_0 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.216922 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.216922 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.icache.demand_misses 623 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 313 # number of demand (read+write) misses -system.cpu.icache.demand_misses_1 310 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 3 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_1 1 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 618 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_1 617 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.216207 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.211893 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_1 0.220714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency_0 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.215529 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.215529 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 310 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_1 309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2863 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 1463 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_1 1400 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 2.974441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_1 2.990323 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2240 # number of overall hits -system.cpu.icache.overall_hits_0 1150 # number of overall hits -system.cpu.icache.overall_hits_1 1090 # number of overall hits +system.cpu.icache.overall_hits 2249 # number of overall hits +system.cpu.icache.overall_hits_0 2249 # number of overall hits +system.cpu.icache.overall_hits_1 0 # number of overall hits system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 931 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_1 927 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.217604 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.213944 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_1 0.221429 # miss rate for overall accesses +system.cpu.icache.overall_miss_latency_0 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.216922 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.216922 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses system.cpu.icache.overall_misses 623 # number of overall misses -system.cpu.icache.overall_misses_0 313 # number of overall misses -system.cpu.icache.overall_misses_1 310 # number of overall misses +system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses_1 0 # number of overall misses system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 3 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_1 1 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 618 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_1 617 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.216207 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.211893 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_1 0.220714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency_0 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.215529 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.215529 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 310 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_1 309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles @@ -418,64 +385,64 @@ system.cpu.icache.sampled_refs 619 # Sa system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 332.781969 # Cycle average of tags in use -system.cpu.icache.total_refs 2240 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 332.429874 # Cycle average of tags in use +system.cpu.icache.total_refs 2249 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.iew.EXEC:branches 2317 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1161 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1156 # Number of branches executed +system.cpu.iew.EXEC:branches 2318 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1160 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1158 # Number of branches executed system.cpu.iew.EXEC:nop 65 # number of nop insts executed system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.816845 # Inst execution rate +system.cpu.iew.EXEC:rate 1.814854 # Inst execution rate system.cpu.iew.EXEC:refs 4932 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2476 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2456 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2474 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2458 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1873 # Number of stores executed -system.cpu.iew.EXEC:stores_0 938 # Number of stores executed -system.cpu.iew.EXEC:stores_1 935 # Number of stores executed +system.cpu.iew.EXEC:stores_0 937 # Number of stores executed +system.cpu.iew.EXEC:stores_1 936 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9998 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5018 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 4980 # num instructions consuming a value +system.cpu.iew.WB:consumers 10005 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5007 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 4998 # num instructions consuming a value system.cpu.iew.WB:count 14809 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7426 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7383 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.777255 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776206 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.778313 # average fanout of values written-back +system.cpu.iew.WB:count_0 7412 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7397 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.777111 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776113 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.778111 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7771 # num instructions producing a value -system.cpu.iew.WB:producers_0 3895 # num instructions producing a value -system.cpu.iew.WB:producers_1 3876 # num instructions producing a value -system.cpu.iew.WB:rate 1.756702 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.880902 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.875801 # insts written-back per cycle +system.cpu.iew.WB:producers 7775 # num instructions producing a value +system.cpu.iew.WB:producers_0 3886 # num instructions producing a value +system.cpu.iew.WB:producers_1 3889 # num instructions producing a value +system.cpu.iew.WB:rate 1.754205 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.877991 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.876214 # insts written-back per cycle system.cpu.iew.WB:sent 14942 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7492 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7450 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 921 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent_0 7477 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7465 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3709 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 3701 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 562 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2218 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18824 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 606 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2217 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18807 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 3059 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1538 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1521 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 941 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15316 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts_0 1537 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1522 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 927 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15321 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -489,28 +456,28 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 894 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 298 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 889 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 297 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 857 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 763 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.667102 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.667220 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.334322 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8176 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 161 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.666153 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.666272 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332425 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8158 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5526 67.59% # Type of FU issued + IntAlu 5514 67.59% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -519,15 +486,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1667 20.39% # Type of FU issued - MemWrite 978 11.96% # Type of FU issued + MemRead 1662 20.37% # Type of FU issued + MemWrite 977 11.98% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8081 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5475 67.75% # Type of FU issued + IntAlu 5481 67.75% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -536,15 +503,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1638 20.27% # Type of FU issued - MemWrite 963 11.92% # Type of FU issued + MemRead 1640 20.27% # Type of FU issued + MemWrite 964 11.92% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16257 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16248 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11001 67.67% # Type of FU issued + IntAlu 10995 67.67% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -553,20 +520,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3305 20.33% # Type of FU issued - MemWrite 1941 11.94% # Type of FU issued + MemRead 3302 20.32% # Type of FU issued + MemWrite 1941 11.95% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 185 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 102 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 83 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011380 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.006274 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005105 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011140 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.006339 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004801 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 10 5.41% # attempts to use FU when none available + IntAlu 10 5.52% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -575,146 +542,140 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 105 56.76% # attempts to use FU when none available - MemWrite 70 37.84% # attempts to use FU when none available + MemRead 100 55.25% # attempts to use FU when none available + MemWrite 71 39.23% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 8430 +system.cpu.iq.ISSUE:issued_per_cycle.samples 8442 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2671 3168.45% - 1 1437 1704.63% - 2 1466 1739.03% - 3 1108 1314.35% - 4 752 892.05% - 5 584 692.76% - 6 285 338.08% - 7 90 106.76% - 8 37 43.89% + 0 2688 3184.08% + 1 1455 1723.53% + 2 1431 1695.10% + 3 1111 1316.04% + 4 762 902.63% + 5 581 688.23% + 6 288 341.15% + 7 91 107.79% + 8 35 41.46% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.928470 # Inst issue rate -system.cpu.iq.iqInstsAdded 18719 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16257 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.924662 # Inst issue rate +system.cpu.iq.iqInstsAdded 18702 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16248 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6696 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 6660 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4128 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 495 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_1 477 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.035160 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.020325 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_1 2.050526 # average ReadReq miss latency +system.cpu.iq.iqSquashedOperandsExamined 4124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.059561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059561 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_1 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_1 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1968 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 994 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_1 974 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994856 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.993939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_1 0.995807 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 967 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 492 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_1 475 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 953 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 478 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_1 475 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.965657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_1 0.995807 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 953 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_1 475 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1971 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 1971 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.994802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 957 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 957 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 957 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 957 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 4 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_accesses_0 4 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 4 # number of WriteReq hits +system.cpu.l2cache.WriteReq_hits_0 4 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005171 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009404 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 972 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 495 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_1 477 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.035160 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 2.020325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_1 2.050526 # average overall miss latency +system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.059561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_1 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1968 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 994 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_1 974 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994856 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.993939 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 0.995807 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 967 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 492 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_1 475 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1971 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 1971 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.990683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.990683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.l2cache.demand_misses 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 953 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 478 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_1 475 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.980453 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.965657 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 0.995807 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 953 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 478 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_1 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.990683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.990683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 972 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 495 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_1 477 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.035160 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 2.020325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_1 2.050526 # average overall miss latency +system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.059561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_1 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5 # number of overall hits -system.cpu.l2cache.overall_hits_0 3 # number of overall hits -system.cpu.l2cache.overall_hits_1 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1968 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 994 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_1 974 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994856 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.993939 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 0.995807 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 967 # number of overall misses -system.cpu.l2cache.overall_misses_0 492 # number of overall misses -system.cpu.l2cache.overall_misses_1 475 # number of overall misses +system.cpu.l2cache.overall_hits 9 # number of overall hits +system.cpu.l2cache.overall_hits_0 9 # number of overall hits +system.cpu.l2cache.overall_hits_1 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1971 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 1971 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.990683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.990683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 957 # number of overall misses +system.cpu.l2cache.overall_misses_0 957 # number of overall misses +system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 953 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 478 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_1 475 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.980453 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.965657 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_1 0.995807 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 953 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 478 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_1 475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.990683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.990683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles @@ -733,31 +694,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 967 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 957 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 569.253381 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 558.911632 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 8430 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking +system.cpu.numCycles 8442 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 338 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 9956 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 693 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26837 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21059 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15731 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3562 # Number of cycles rename is running +system.cpu.rename.RENAME:IdleCycles 9965 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26913 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21123 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15786 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3571 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7629 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 556 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UnblockCycles 763 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7684 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 572 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1898 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 1900 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 29d3771fb..be25795fb 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:13 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:47 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Exiting @ tick 8429 because target called exit() +Exiting @ tick 8441 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 9a723049a..f8d2c4ea7 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 309857 # Simulator instruction rate (inst/s) -host_mem_usage 159252 # Number of bytes of host memory used -host_seconds 1.61 # Real time elapsed on the host -host_tick_rate 422749 # Simulator tick rate (ticks/s) +host_inst_rate 618043 # Simulator instruction rate (inst/s) +host_mem_usage 159232 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host +host_tick_rate 843177 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 682354 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2.987952 # average ReadReq miss latency +sim_ticks 682488 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 1.256024 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1161 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses -system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180727 # number of overall hits -system.cpu.dcache.overall_miss_latency 1161 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses -system.cpu.dcache.overall_misses 581 # number of overall misses +system.cpu.dcache.overall_hits 180321 # number of overall hits +system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use -system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use +system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) @@ -138,54 +138,56 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use +system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 165 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 165 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.192532 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.demand_accesses 1022 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 165 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.838552 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.838552 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.overall_accesses 1022 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 984 # number of overall misses +system.cpu.l2cache.overall_hits 165 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.838552 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.838552 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -198,10 +200,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use +system.cpu.l2cache.total_refs 165 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 91e0bd147..409068a91 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:19 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:52 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 682354 because a thread reached the max instruction count +Exiting @ tick 682488 because a thread reached the max instruction count -- cgit v1.2.3 From 8949d813ff6f9941faf1b173d408e13b0a2440a7 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 8 Oct 2006 01:12:42 -0400 Subject: Clean up configs. configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. --HG-- extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b --- tests/configs/o3-timing-mp.py | 3 +-- tests/configs/o3-timing.py | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 881c23156..09935d574 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -29,7 +29,6 @@ import m5 from m5.objects import * m5.AddToPath('../configs/common') -from FullO3Config import * # -------------------- # Base L1 Cache @@ -54,7 +53,7 @@ class L2(BaseCache): write_buffers = 8 nb_cores = 4 -cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ] +cpus = [ DerivO3CPU() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, physmem = PhysicalMemory(), membus = diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 227e1ba21..0dd7be506 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -29,7 +29,6 @@ import m5 from m5.objects import * m5.AddToPath('../configs/common') -from FullO3Config import * class MyCache(BaseCache): assoc = 2 @@ -38,7 +37,7 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 -cpu = DetailedO3CPU() +cpu = DerivO3CPU() cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) cpu.mem = cpu.dcache -- cgit v1.2.3 From d3fba5aa30adfb006b99895e869ed175213d0134 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 8 Oct 2006 10:53:24 -0700 Subject: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be --- tests/configs/simple-atomic.py | 2 +- tests/configs/simple-timing.py | 2 +- tests/configs/tsunami-simple-atomic-dual.py | 2 +- tests/configs/tsunami-simple-atomic.py | 2 +- tests/configs/tsunami-simple-timing-dual.py | 2 +- tests/configs/tsunami-simple-timing.py | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index 2bf67f3b1..d35ac4ae0 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -29,7 +29,7 @@ import m5 from m5.objects import * -system = System(cpu = AtomicSimpleCPU(), +system = System(cpu = AtomicSimpleCPU(cpu_id=0), physmem = PhysicalMemory(), membus = Bus()) system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 7bb76db0e..60190b47c 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -36,7 +36,7 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 -cpu = TimingSimpleCPU() +cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) cpu.mem = cpu.dcache diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index e3945f7dc..f798213db 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -34,7 +34,7 @@ import FSConfig AlphaConsole.cpu = Parent.cpu[0] IntrControl.cpu = Parent.cpu[0] -cpus = [ AtomicSimpleCPU() for i in xrange(2) ] +cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpus for c in cpus: diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index ca1dd5c77..623d285e4 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,7 +31,7 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig -cpu = AtomicSimpleCPU() +cpu = AtomicSimpleCPU(cpu_id=0) system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpu cpu.connectMemPorts(system.membus) diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 967d6a2d2..bf94214fd 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -34,7 +34,7 @@ import FSConfig AlphaConsole.cpu = Parent.cpu[0] IntrControl.cpu = Parent.cpu[0] -cpus = [ TimingSimpleCPU() for i in xrange(2) ] +cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus for c in cpus: diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index b3fc9d105..2edf5ac32 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,7 +31,7 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig -cpu = TimingSimpleCPU() +cpu = TimingSimpleCPU(cpu_id=0) system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu cpu.connectMemPorts(system.membus) -- cgit v1.2.3 From 911381321b294fa5a8d2dd77eaabc7473ffe5e6f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 8 Oct 2006 17:07:23 -0400 Subject: Update ref stats: ll/sc, cpu_id, new kernel (?) --HG-- extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8 --- .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/linux/o3-timing/stdout | 4 +- .../ref/alpha/linux/simple-atomic/config.ini | 1 + .../ref/alpha/linux/simple-atomic/config.out | 1 + .../ref/alpha/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/alpha/linux/simple-atomic/stdout | 4 +- .../ref/alpha/linux/simple-timing/config.ini | 1 + .../ref/alpha/linux/simple-timing/config.out | 1 + .../ref/alpha/linux/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/linux/simple-timing/stdout | 4 +- .../00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 4 +- .../ref/alpha/tru64/simple-atomic/config.ini | 1 + .../ref/alpha/tru64/simple-atomic/config.out | 1 + .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-atomic/stdout | 4 +- .../ref/alpha/tru64/simple-timing/config.ini | 1 + .../ref/alpha/tru64/simple-timing/config.out | 1 + .../ref/alpha/tru64/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 4 +- .../ref/mips/linux/simple-atomic/config.ini | 9 + .../ref/mips/linux/simple-atomic/config.out | 12 + .../ref/mips/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/mips/linux/simple-atomic/stdout | 4 +- .../ref/mips/linux/simple-timing/config.ini | 9 + .../ref/mips/linux/simple-timing/config.out | 12 + .../ref/mips/linux/simple-timing/m5stats.txt | 8 +- .../00.hello/ref/mips/linux/simple-timing/stdout | 4 +- .../ref/sparc/linux/simple-atomic/config.ini | 9 + .../ref/sparc/linux/simple-atomic/config.out | 12 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../00.hello/ref/sparc/linux/simple-atomic/stdout | 4 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 44 +-- .../ref/alpha/linux/o3-timing/stdout | 4 +- .../linux/tsunami-simple-atomic-dual/config.ini | 4 +- .../linux/tsunami-simple-atomic-dual/config.out | 4 +- .../console.system.sim_console | 54 +-- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 407 ++++++++++---------- .../alpha/linux/tsunami-simple-atomic-dual/stderr | 8 +- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-atomic/config.ini | 2 +- .../alpha/linux/tsunami-simple-atomic/config.out | 2 +- .../console.system.sim_console | 54 +-- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 140 +++---- .../ref/alpha/linux/tsunami-simple-atomic/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 6 +- .../linux/tsunami-simple-timing-dual/config.ini | 4 +- .../linux/tsunami-simple-timing-dual/config.out | 4 +- .../console.system.sim_console | 54 +-- .../linux/tsunami-simple-timing-dual/m5stats.txt | 409 ++++++++++----------- .../alpha/linux/tsunami-simple-timing-dual/stderr | 8 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-timing/config.ini | 2 +- .../alpha/linux/tsunami-simple-timing/config.out | 2 +- .../console.system.sim_console | 54 +-- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 146 ++++---- .../ref/alpha/linux/tsunami-simple-timing/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 6 +- .../ref/alpha/eio/simple-atomic/config.ini | 1 + .../ref/alpha/eio/simple-atomic/config.out | 1 + .../ref/alpha/eio/simple-atomic/m5stats.txt | 6 +- .../ref/alpha/eio/simple-atomic/stdout | 4 +- .../ref/alpha/eio/simple-timing/config.ini | 1 + .../ref/alpha/eio/simple-timing/config.out | 1 + .../ref/alpha/eio/simple-timing/m5stats.txt | 10 +- .../ref/alpha/eio/simple-timing/stdout | 4 +- 66 files changed, 864 insertions(+), 781 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index c2c9affca..b8dbf28af 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted global.BPredUnit.lookups 2254 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 47059 # Simulator instruction rate (inst/s) -host_mem_usage 160380 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 57322 # Simulator tick rate (ticks/s) +host_inst_rate 1748 # Simulator instruction rate (inst/s) +host_mem_usage 160364 # Number of bytes of host memory used +host_seconds 3.22 # Real time elapsed on the host +host_tick_rate 2135 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 14ef519e9..718827a30 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:34 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:45 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Exiting @ tick 6868 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index f7e73950d..7340cc079 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 198d7df5e..73f91ff61 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -44,6 +44,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index e3cd05fb0..875e55644 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 74000 # Simulator instruction rate (inst/s) -host_mem_usage 148088 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 73591 # Simulator tick rate (ticks/s) +host_inst_rate 172802 # Simulator instruction rate (inst/s) +host_mem_usage 148116 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 170614 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index e26480539..59f571aaf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:02 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:50 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 5641 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index cefcf7f11..7b517abc8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 1ed18ff71..5c4c7fb14 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -83,6 +83,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 97d39456e..757bbb920 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 286207 # Simulator instruction rate (inst/s) -host_mem_usage 159648 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 413300 # Simulator tick rate (ticks/s) +host_inst_rate 98835 # Simulator instruction rate (inst/s) +host_mem_usage 159632 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 144603 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a9c37a14d..be8eccb38 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:38 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:50 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Exiting @ tick 8316 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 53d94a43f..41348bbfb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 45832 # Simulator instruction rate (inst/s) -host_mem_usage 159900 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 55090 # Simulator tick rate (ticks/s) +host_inst_rate 26386 # Simulator instruction rate (inst/s) +host_mem_usage 159884 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 31792 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index fa94f7eb9..c51631489 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:40 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:52 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 34f5c0b32..f248945b1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index a474765ae..58ae0d9df 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -44,6 +44,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index b120e12b9..e3f845135 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 548861 # Simulator instruction rate (inst/s) -host_mem_usage 147820 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 504404 # Simulator tick rate (ticks/s) +host_inst_rate 60702 # Simulator instruction rate (inst/s) +host_mem_usage 147692 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 60102 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 0c9b00960..2ee4e0a08 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:09 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:54 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 0d7d34e64..5616cf909 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 9b44f8ddd..c76e14e2c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -83,6 +83,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 916f9dad8..39ef8ead8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 196989 # Simulator instruction rate (inst/s) -host_mem_usage 159172 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 279840 # Simulator tick rate (ticks/s) +host_inst_rate 69262 # Simulator instruction rate (inst/s) +host_mem_usage 159156 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 100319 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d152dc89c..27e317357 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:45 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:54 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 2c82b8c1a..fa3ccdf1c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +76,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +102,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 8678c0d97..6ab9c098e 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +41,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +56,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +100,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index b70a6ee17..f358a8e52 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 90956 # Simulator instruction rate (inst/s) -host_mem_usage 147380 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 90353 # Simulator tick rate (ticks/s) +host_inst_rate 2733 # Simulator instruction rate (inst/s) +host_mem_usage 147536 # Number of bytes of host memory used +host_seconds 2.07 # Real time elapsed on the host +host_tick_rate 2732 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index f5b9c8fd7..4056e38ec 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:37:09 -M5 started Tue Sep 5 15:46:32 2006 +M5 compiled Oct 8 2006 14:15:37 +M5 started Sun Oct 8 14:15:41 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 040735f2c..af7a1c895 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +199,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +225,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index a7270a97e..ead34bf39 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -67,6 +67,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,8 +80,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -169,6 +177,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +221,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index bc5ad3cca..ef08c56cd 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 273933 # Simulator instruction rate (inst/s) -host_mem_usage 159012 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 403699 # Simulator tick rate (ticks/s) +host_inst_rate 116093 # Simulator instruction rate (inst/s) +host_mem_usage 158992 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 174583 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 954193ee0..97b24e1ad 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:52:26 -M5 started Sat Oct 7 12:52:42 2006 +M5 compiled Oct 8 2006 14:15:37 +M5 started Sun Oct 8 14:15:43 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Exiting @ tick 8579 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 082415a7f..21028fa63 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +76,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/sparc/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +102,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 45412a511..f5be4e3bd 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +41,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +56,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +100,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 9bfb2fec9..e87e77b8f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 61348 # Simulator instruction rate (inst/s) -host_mem_usage 147288 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 60991 # Simulator tick rate (ticks/s) +host_inst_rate 2175 # Simulator instruction rate (inst/s) +host_mem_usage 147292 # Number of bytes of host memory used +host_seconds 2.06 # Real time elapsed on the host +host_tick_rate 2174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4483 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 38eb82c8b..c9df3a17c 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:39:50 -M5 started Tue Sep 5 15:49:24 2006 +M5 compiled Oct 8 2006 14:19:59 +M5 started Sun Oct 8 14:20:03 2006 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Exiting @ tick 4482 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index a249947ca..15172b43c 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1081 # Nu global.BPredUnit.condPredicted 2449 # Number of conditional branches predicted global.BPredUnit.lookups 4173 # Number of BP lookups global.BPredUnit.usedRAS 551 # Number of times the RAS was used to get a target. -host_inst_rate 50082 # Simulator instruction rate (inst/s) -host_mem_usage 161260 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 37535 # Simulator tick rate (ticks/s) +host_inst_rate 40630 # Simulator instruction rate (inst/s) +host_mem_usage 161244 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host +host_tick_rate 30458 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. @@ -115,7 +115,7 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # m system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.088670 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.670554 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked @@ -476,20 +476,20 @@ system.cpu.ipc_1 0.666272 # IP system.cpu.ipc_total 1.332425 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8158 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5514 67.59% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1662 20.37% # Type of FU issued - MemWrite 977 11.98% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued +(null) 2 0.02% # Type of FU issued +IntAlu 5514 67.59% # Type of FU issued +IntMult 1 0.01% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 2 0.02% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 1662 20.37% # Type of FU issued +MemWrite 977 11.98% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist @@ -610,7 +610,7 @@ system.cpu.l2cache.demand_avg_miss_latency_0 2.059561 system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 no value # average overall mshr miss latency system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 9 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits @@ -619,7 +619,7 @@ system.cpu.l2cache.demand_miss_latency_0 1971 # nu system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.990683 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_0 0.990683 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 957 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 957 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses @@ -631,7 +631,7 @@ system.cpu.l2cache.demand_mshr_miss_latency_0 957 system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.990683 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_0 0.990683 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 957 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 957 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index be25795fb..6b640d359 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:47 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:56 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Exiting @ tick 8441 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 3d719c501..401611d58 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -75,7 +75,7 @@ side_b=system.membus.port[0] type=AtomicSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false dtb=system.cpu0.dtb function_trace=false @@ -106,7 +106,7 @@ size=48 type=AtomicSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=1 defer_registration=false dtb=system.cpu1.dtb function_trace=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index b8290213e..1d4d50845 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -90,9 +90,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 itb=system.cpu0.itb dtb=system.cpu0.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false @@ -118,9 +118,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=1 itb=system.cpu1.itb dtb=system.cpu1.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console index 4a397ddbf..57a610390 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 2 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -16,29 +16,27 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Bootstraping CPU 1 with sp=0xFFFFFC0000076000 unix_boot_mem ends at FFFFFC0000078000 k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028) - CallbackFixup 0 18000, t7=FFFFFC0000700000 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 memcluster 0, usage 1, start 0, end 392 memcluster 1, usage 0, start 392, end 16384 - freeing pages 1030:16384 - reserving pages 1030:1031 + freeing pages 1069:16384 + reserving pages 1069:1070 SMP: 2 CPUs probed -- cpu_present_mask = 3 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order 10: 16384 bytes) + PID hash table entries: 1024 (order: 10, 32768 bytes) Using epoch = 1900 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init) - Mount-cache hash table entries: 512 (order: 0, 8192 bytes) - per-CPU timeslice cutoff: 374.49 usecs. - task migration cache decay timeout: 0 msecs. + Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 SMP starting up secondaries. Slave CPU 1 console command START SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 @@ -53,16 +51,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb Initializing Cryptographic API rtc: Standard PC (1900) epoch (1900) detected Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered loop: loaded (max 8 devices) - Using anticipatory io scheduler nbd: registered device at major 43 sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + ns83820: irq bound to CPU 1 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver - eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX4: IDE controller at PCI slot 0000:00:00.0 @@ -75,24 +80,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) + hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported hdb: unknown partition table - scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0 - Vendor: Linux Model: scsi_m5 Li Rev: 0004 - Type: Direct-Access ANSI SCSI revision: 03 - SCSI device sda: 16384 512-byte hdwr sectors (8 MB) - SCSI device sda: drive cache: write back - sda: unknown partition table - Attached scsi disk sda at scsi0, channel 0, id 0, lun 0 mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 - IP: routing cache hash table of 1024 buckets, 16Kbytes - TCP: Hash tables configured (established 8192 bind 8192) - ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack ip_tables: (C) 2000-2002 Netfilter core team arp_tables: (C) 2002 David S. Miller + TCP bic registered Initializing IPsec netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 @@ -101,7 +105,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb 802.1Q VLAN Support v1.8 Ben Greear All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 480k freed + Freeing unused kernel memory: 224k freed init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 376929ebb..537721d92 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,232 +1,225 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1361363 # Simulator instruction rate (inst/s) -host_mem_usage 194440 # Number of bytes of host memory used -host_seconds 45.04 # Real time elapsed on the host -host_tick_rate 78691874 # Simulator tick rate (ticks/s) +host_inst_rate 1292093 # Simulator instruction rate (inst/s) +host_mem_usage 197872 # Number of bytes of host memory used +host_seconds 51.53 # Real time elapsed on the host +host_tick_rate 72118724 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61314617 # Number of instructions simulated -sim_seconds 1.772124 # Number of seconds simulated -sim_ticks 3544247159 # Number of ticks simulated -system.cpu0.dtb.accesses 1850344 # DTB accesses -system.cpu0.dtb.acv 301 # DTB access violations -system.cpu0.dtb.hits 12691711 # DTB hits -system.cpu0.dtb.misses 8349 # DTB misses -system.cpu0.dtb.read_accesses 509385 # DTB read accesses -system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7018751 # DTB read hits -system.cpu0.dtb.read_misses 6579 # DTB read misses -system.cpu0.dtb.write_accesses 1340959 # DTB write accesses -system.cpu0.dtb.write_acv 117 # DTB write access violations -system.cpu0.dtb.write_hits 5672960 # DTB write hits -system.cpu0.dtb.write_misses 1770 # DTB write misses -system.cpu0.idle_fraction 0.984893 # Percentage of idle cycles -system.cpu0.itb.accesses 1981604 # ITB accesses -system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 1978255 # ITB hits -system.cpu0.itb.misses 3349 # ITB misses -system.cpu0.kern.callpal 176688 # number of callpals executed +sim_insts 66579941 # Number of instructions simulated +sim_seconds 1.858108 # Number of seconds simulated +sim_ticks 3716216351 # Number of ticks simulated +system.cpu0.dtb.accesses 604194 # DTB accesses +system.cpu0.dtb.acv 337 # DTB access violations +system.cpu0.dtb.hits 12597930 # DTB hits +system.cpu0.dtb.misses 7857 # DTB misses +system.cpu0.dtb.read_accesses 426113 # DTB read accesses +system.cpu0.dtb.read_acv 210 # DTB read access violations +system.cpu0.dtb.read_hits 7793080 # DTB read hits +system.cpu0.dtb.read_misses 7107 # DTB read misses +system.cpu0.dtb.write_accesses 178081 # DTB write accesses +system.cpu0.dtb.write_acv 127 # DTB write access violations +system.cpu0.dtb.write_hits 4804850 # DTB write hits +system.cpu0.dtb.write_misses 750 # DTB write misses +system.cpu0.idle_fraction 0.986701 # Percentage of idle cycles +system.cpu0.itb.accesses 1567177 # ITB accesses +system.cpu0.itb.acv 184 # ITB acv +system.cpu0.itb.hits 1563535 # ITB hits +system.cpu0.itb.misses 3642 # ITB misses +system.cpu0.kern.callpal 140535 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 97 0.05% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1117 0.63% 0.69% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 0.71% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.72% # number of callpals executed -system.cpu0.kern.callpal_swpipl 166811 94.41% 95.13% # number of callpals executed -system.cpu0.kern.callpal_rdps 4911 2.78% 97.91% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.91% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 97.91% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.01% 97.91% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.92% # number of callpals executed -system.cpu0.kern.callpal_rti 3236 1.83% 99.75% # number of callpals executed -system.cpu0.kern.callpal_callsys 325 0.18% 99.93% # number of callpals executed -system.cpu0.kern.callpal_imb 121 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 567 0.40% 0.40% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.41% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.41% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2926 2.08% 2.49% # number of callpals executed +system.cpu0.kern.callpal_tbi 49 0.03% 2.52% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.53% # number of callpals executed +system.cpu0.kern.callpal_swpipl 126411 89.95% 92.48% # number of callpals executed +system.cpu0.kern.callpal_rdps 5784 4.12% 96.59% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.59% # number of callpals executed +system.cpu0.kern.callpal_wrusp 2 0.00% 96.60% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 96.60% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.60% # number of callpals executed +system.cpu0.kern.callpal_rti 4273 3.04% 99.64% # number of callpals executed +system.cpu0.kern.callpal_callsys 366 0.26% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 134 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 190918 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 155157 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1922 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 172116 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72060 41.87% 41.87% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 251 0.15% 42.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5518 3.21% 45.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 7 0.00% 45.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 94280 54.78% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 153515 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 72019 46.91% 46.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 251 0.16% 47.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5518 3.59% 50.67% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 7 0.00% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 75720 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3543835079 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3521923327 99.38% 99.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 39982 0.00% 99.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1005040 0.03% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1756 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 20864974 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.891928 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999431 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6712 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 133285 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 53228 39.94% 39.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 245 0.18% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1895 1.42% 41.54% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 460 0.35% 41.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 77457 58.11% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 107676 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 52768 49.01% 49.01% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 245 0.23% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1895 1.76% 50.99% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 460 0.43% 51.42% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 52308 48.58% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3716215936 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3683825506 99.13% 99.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 162970 0.00% 99.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 103364 0.00% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 32083622 0.86% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.807863 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.991358 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.803140 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1277 -system.cpu0.kern.mode_good_user 1129 -system.cpu0.kern.mode_good_idle 148 -system.cpu0.kern.mode_switch_kernel 2253 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1129 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2074 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.468109 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.566800 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.675317 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1221 +system.cpu0.kern.mode_good_user 1222 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 6758 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1222 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.306140 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.180675 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.071360 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 28710240 0.81% 0.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2184201 0.06% 0.87% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3512891779 99.13% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1118 # number of times the context was actually changed -system.cpu0.kern.syscall 192 # number of syscalls executed -system.cpu0.kern.syscall_fork 7 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall_read 13 6.77% 10.42% # number of syscalls executed -system.cpu0.kern.syscall_write 4 2.08% 12.50% # number of syscalls executed -system.cpu0.kern.syscall_close 28 14.58% 27.08% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.52% 27.60% # number of syscalls executed -system.cpu0.kern.syscall_obreak 7 3.65% 31.25% # number of syscalls executed -system.cpu0.kern.syscall_lseek 6 3.12% 34.37% # number of syscalls executed -system.cpu0.kern.syscall_getpid 4 2.08% 36.46% # number of syscalls executed -system.cpu0.kern.syscall_setuid 1 0.52% 36.98% # number of syscalls executed -system.cpu0.kern.syscall_getuid 3 1.56% 38.54% # number of syscalls executed -system.cpu0.kern.syscall_access 7 3.65% 42.19% # number of syscalls executed -system.cpu0.kern.syscall_dup 2 1.04% 43.23% # number of syscalls executed -system.cpu0.kern.syscall_open 34 17.71% 60.94% # number of syscalls executed -system.cpu0.kern.syscall_getgid 3 1.56% 62.50% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 8 4.17% 66.67% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 9 4.69% 71.35% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.52% 71.87% # number of syscalls executed -system.cpu0.kern.syscall_execve 5 2.60% 74.48% # number of syscalls executed -system.cpu0.kern.syscall_mmap 22 11.46% 85.94% # number of syscalls executed -system.cpu0.kern.syscall_munmap 2 1.04% 86.98% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 6 3.12% 90.10% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.52% 90.62% # number of syscalls executed -system.cpu0.kern.syscall_dup2 2 1.04% 91.67% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 8 4.17% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_socket 2 1.04% 96.87% # number of syscalls executed -system.cpu0.kern.syscall_connect 2 1.04% 97.92% # number of syscalls executed -system.cpu0.kern.syscall_setgid 1 0.52% 98.44% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 1 0.52% 98.96% # number of syscalls executed -system.cpu0.kern.syscall_setsid 2 1.04% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015107 # Percentage of non-idle cycles -system.cpu0.numCycles 53543489 # number of cpu cycles simulated -system.cpu0.num_insts 53539979 # Number of instructions executed -system.cpu0.num_refs 12727196 # Number of memory references -system.cpu1.dtb.accesses 460215 # DTB accesses -system.cpu1.dtb.acv 72 # DTB access violations -system.cpu1.dtb.hits 2012555 # DTB hits -system.cpu1.dtb.misses 4236 # DTB misses -system.cpu1.dtb.read_accesses 319867 # DTB read accesses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 1276251 # DTB read hits -system.cpu1.dtb.read_misses 3800 # DTB read misses -system.cpu1.dtb.write_accesses 140348 # DTB write accesses -system.cpu1.dtb.write_acv 46 # DTB write access violations -system.cpu1.dtb.write_hits 736304 # DTB write hits -system.cpu1.dtb.write_misses 436 # DTB write misses -system.cpu1.idle_fraction 0.997806 # Percentage of idle cycles -system.cpu1.itb.accesses 1302484 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 1300768 # ITB hits -system.cpu1.itb.misses 1716 # ITB misses -system.cpu1.kern.callpal 27118 # number of callpals executed +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 3714429703 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 1786231 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2927 # number of times the context was actually changed +system.cpu0.kern.syscall 217 # number of syscalls executed +system.cpu0.kern.syscall_fork 8 3.69% 3.69% # number of syscalls executed +system.cpu0.kern.syscall_read 19 8.76% 12.44% # number of syscalls executed +system.cpu0.kern.syscall_write 3 1.38% 13.82% # number of syscalls executed +system.cpu0.kern.syscall_close 31 14.29% 28.11% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.46% 28.57% # number of syscalls executed +system.cpu0.kern.syscall_obreak 6 2.76% 31.34% # number of syscalls executed +system.cpu0.kern.syscall_lseek 10 4.61% 35.94% # number of syscalls executed +system.cpu0.kern.syscall_getpid 6 2.76% 38.71% # number of syscalls executed +system.cpu0.kern.syscall_setuid 2 0.92% 39.63% # number of syscalls executed +system.cpu0.kern.syscall_getuid 4 1.84% 41.47% # number of syscalls executed +system.cpu0.kern.syscall_access 6 2.76% 44.24% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 0.92% 45.16% # number of syscalls executed +system.cpu0.kern.syscall_open 33 15.21% 60.37% # number of syscalls executed +system.cpu0.kern.syscall_getgid 4 1.84% 62.21% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 10 4.61% 66.82% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 4.15% 70.97% # number of syscalls executed +system.cpu0.kern.syscall_execve 6 2.76% 73.73% # number of syscalls executed +system.cpu0.kern.syscall_mmap 25 11.52% 85.25% # number of syscalls executed +system.cpu0.kern.syscall_munmap 3 1.38% 86.64% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 7 3.23% 89.86% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.46% 90.32% # number of syscalls executed +system.cpu0.kern.syscall_dup2 3 1.38% 91.71% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 3.69% 95.39% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 0.92% 96.31% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 0.92% 97.24% # number of syscalls executed +system.cpu0.kern.syscall_setgid 2 0.92% 98.16% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 2 0.92% 99.08% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 0.92% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.013299 # Percentage of non-idle cycles +system.cpu0.numCycles 49421041 # number of cpu cycles simulated +system.cpu0.num_insts 49417215 # Number of instructions executed +system.cpu0.num_refs 12829669 # Number of memory references +system.cpu1.dtb.accesses 701326 # DTB accesses +system.cpu1.dtb.acv 30 # DTB access violations +system.cpu1.dtb.hits 5286923 # DTB hits +system.cpu1.dtb.misses 3658 # DTB misses +system.cpu1.dtb.read_accesses 474933 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 3100008 # DTB read hits +system.cpu1.dtb.read_misses 3260 # DTB read misses +system.cpu1.dtb.write_accesses 226393 # DTB write accesses +system.cpu1.dtb.write_acv 30 # DTB write access violations +system.cpu1.dtb.write_hits 2186915 # DTB write hits +system.cpu1.dtb.write_misses 398 # DTB write misses +system.cpu1.idle_fraction 0.995381 # Percentage of idle cycles +system.cpu1.itb.accesses 1714255 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 1712856 # ITB hits +system.cpu1.itb.misses 1399 # ITB misses +system.cpu1.kern.callpal 81795 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 7 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal_swpctx 515 1.90% 1.94% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.04% 1.97% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.03% 2.00% # number of callpals executed -system.cpu1.kern.callpal_swpipl 23496 86.64% 88.64% # number of callpals executed -system.cpu1.kern.callpal_rdps 251 0.93% 89.57% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 89.57% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 89.59% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 89.59% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 89.60% # number of callpals executed -system.cpu1.kern.callpal_rti 2552 9.41% 99.01% # number of callpals executed -system.cpu1.kern.callpal_callsys 208 0.77% 99.78% # number of callpals executed -system.cpu1.kern.callpal_imb 59 0.22% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 460 0.56% 0.56% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.56% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.57% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2245 2.74% 3.31% # number of callpals executed +system.cpu1.kern.callpal_tbi 4 0.00% 3.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.32% # number of callpals executed +system.cpu1.kern.callpal_swpipl 71908 87.91% 91.24% # number of callpals executed +system.cpu1.kern.callpal_rdps 3034 3.71% 94.95% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.95% # number of callpals executed +system.cpu1.kern.callpal_wrusp 5 0.01% 94.95% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.96% # number of callpals executed +system.cpu1.kern.callpal_rti 3913 4.78% 99.74% # number of callpals executed +system.cpu1.kern.callpal_callsys 165 0.20% 99.94% # number of callpals executed +system.cpu1.kern.callpal_imb 46 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 35069 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 89345 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1947 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 27951 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10084 36.08% 36.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5485 19.62% 55.70% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 97 0.35% 56.05% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 12285 43.95% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 27484 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10061 36.61% 36.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5485 19.96% 56.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 97 0.35% 56.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11841 43.08% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3544246744 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3521927913 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1037048 0.03% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 25211 0.00% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21256572 0.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.983292 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.997719 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2592 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 78283 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 30809 39.36% 39.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1894 2.42% 41.78% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 567 0.72% 42.50% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 45013 57.50% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 61674 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 29890 48.46% 48.46% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1894 3.07% 51.54% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 567 0.92% 52.45% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 29323 47.55% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3715795413 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3690163762 99.31% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 162884 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 130370 0.00% 99.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 25338397 0.68% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.787834 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.970171 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.963858 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 636 -system.cpu1.kern.mode_good_user 637 -system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 3063 # number of protection mode switches -system.cpu1.kern.mode_switch_user 637 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.344054 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.207640 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.651434 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 1028 +system.cpu1.kern.mode_good_user 535 +system.cpu1.kern.mode_good_idle 493 +system.cpu1.kern.mode_switch_kernel 2307 # number of protection mode switches +system.cpu1.kern.mode_switch_user 535 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2948 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.355095 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.445600 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3542834137 99.96% 99.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1412605 0.04% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 516 # number of times the context was actually changed -system.cpu1.kern.syscall 137 # number of syscalls executed -system.cpu1.kern.syscall_fork 1 0.73% 0.73% # number of syscalls executed -system.cpu1.kern.syscall_read 17 12.41% 13.14% # number of syscalls executed -system.cpu1.kern.syscall_close 15 10.95% 24.09% # number of syscalls executed -system.cpu1.kern.syscall_chmod 1 0.73% 24.82% # number of syscalls executed -system.cpu1.kern.syscall_obreak 8 5.84% 30.66% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 2.92% 33.58% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 1.46% 35.04% # number of syscalls executed -system.cpu1.kern.syscall_setuid 3 2.19% 37.23% # number of syscalls executed -system.cpu1.kern.syscall_getuid 3 2.19% 39.42% # number of syscalls executed -system.cpu1.kern.syscall_access 4 2.92% 42.34% # number of syscalls executed -system.cpu1.kern.syscall_open 21 15.33% 57.66% # number of syscalls executed -system.cpu1.kern.syscall_getgid 3 2.19% 59.85% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 2 1.46% 61.31% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 1 0.73% 62.04% # number of syscalls executed -system.cpu1.kern.syscall_execve 2 1.46% 63.50% # number of syscalls executed -system.cpu1.kern.syscall_mmap 32 23.36% 86.86% # number of syscalls executed -system.cpu1.kern.syscall_munmap 1 0.73% 87.59% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 10 7.30% 94.89% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 0.73% 95.62% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 2 1.46% 97.08% # number of syscalls executed -system.cpu1.kern.syscall_setgid 3 2.19% 99.27% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 0.73% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002194 # Percentage of non-idle cycles -system.cpu1.numCycles 7776377 # number of cpu cycles simulated -system.cpu1.num_insts 7774638 # Number of instructions executed -system.cpu1.num_refs 2025195 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.167232 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 12634755 0.34% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1807179 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3700889452 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2246 # number of times the context was actually changed +system.cpu1.kern.syscall 112 # number of syscalls executed +system.cpu1.kern.syscall_read 11 9.82% 9.82% # number of syscalls executed +system.cpu1.kern.syscall_write 1 0.89% 10.71% # number of syscalls executed +system.cpu1.kern.syscall_close 12 10.71% 21.43% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 0.89% 22.32% # number of syscalls executed +system.cpu1.kern.syscall_obreak 9 8.04% 30.36% # number of syscalls executed +system.cpu1.kern.syscall_setuid 2 1.79% 32.14% # number of syscalls executed +system.cpu1.kern.syscall_getuid 2 1.79% 33.93% # number of syscalls executed +system.cpu1.kern.syscall_access 5 4.46% 38.39% # number of syscalls executed +system.cpu1.kern.syscall_open 22 19.64% 58.04% # number of syscalls executed +system.cpu1.kern.syscall_getgid 2 1.79% 59.82% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 0.89% 60.71% # number of syscalls executed +system.cpu1.kern.syscall_readlink 1 0.89% 61.61% # number of syscalls executed +system.cpu1.kern.syscall_execve 1 0.89% 62.50% # number of syscalls executed +system.cpu1.kern.syscall_mmap 29 25.89% 88.39% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 9 8.04% 96.43% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 1.79% 98.21% # number of syscalls executed +system.cpu1.kern.syscall_setgid 2 1.79% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.004619 # Percentage of non-idle cycles +system.cpu1.numCycles 17164125 # number of cpu cycles simulated +system.cpu1.num_insts 17162726 # Number of instructions executed +system.cpu1.num_refs 5316705 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. -system.disk0.dma_write_txs 412 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. +system.disk0.dma_write_txs 408 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index fe3ad68ab..d55b33424 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,6 +1,6 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 195722: Trying to launch CPU number 1! +warn: 195723: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 039088577..76bd8d3c2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 5 2006 22:13:02 -M5 started Fri Oct 6 00:24:12 2006 +M5 compiled Oct 8 2006 14:07:02 +M5 started Sun Oct 8 14:07:57 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3544247159 because m5_exit instruction encountered +Exiting @ tick 3716216351 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index e30428078..bdd7566bc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -75,7 +75,7 @@ side_b=system.membus.port[0] type=AtomicSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false dtb=system.cpu.dtb function_trace=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index ea63dce8b..bc2f45a5e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -90,9 +90,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 itb=system.cpu.itb dtb=system.cpu.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console index d6e3955cc..1d150a047 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 1 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -14,28 +14,26 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 unix_boot_mem ends at FFFFFC0000076000 k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028) - CallbackFixup 0 18000, t7=FFFFFC0000700000 - Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 memcluster 0, usage 1, start 0, end 392 memcluster 1, usage 0, start 392, end 16384 - freeing pages 1030:16384 - reserving pages 1030:1031 + freeing pages 1069:16384 + reserving pages 1069:1070 SMP: 1 CPUs probed -- cpu_present_mask = 1 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order 10: 16384 bytes) + PID hash table entries: 1024 (order: 10, 32768 bytes) Using epoch = 1900 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init) - Mount-cache hash table entries: 512 (order: 0, 8192 bytes) - per-CPU timeslice cutoff: 374.49 usecs. - task migration cache decay timeout: 0 msecs. + Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 SMP mode deactivated. Brought up 1 CPUs SMP: Total of 1 processors activated (4002.20 BogoMIPS). @@ -48,16 +46,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Initializing Cryptographic API rtc: Standard PC (1900) epoch (1900) detected Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered loop: loaded (max 8 devices) - Using anticipatory io scheduler nbd: registered device at major 43 sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + ns83820: irq bound to CPU 0 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver - eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX4: IDE controller at PCI slot 0000:00:00.0 @@ -70,24 +75,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) + hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported hdb: unknown partition table - scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0 - Vendor: Linux Model: scsi_m5 Li Rev: 0004 - Type: Direct-Access ANSI SCSI revision: 03 - SCSI device sda: 16384 512-byte hdwr sectors (8 MB) - SCSI device sda: drive cache: write back - sda: unknown partition table - Attached scsi disk sda at scsi0, channel 0, id 0, lun 0 mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 - IP: routing cache hash table of 1024 buckets, 16Kbytes - TCP: Hash tables configured (established 8192 bind 8192) - ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack ip_tables: (C) 2000-2002 Netfilter core team arp_tables: (C) 2002 David S. Miller + TCP bic registered Initializing IPsec netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 @@ -96,7 +100,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 802.1Q VLAN Support v1.8 Ben Greear All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 480k freed + Freeing unused kernel memory: 224k freed init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 5c403c0a9..c9661f182 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1121378 # Simulator instruction rate (inst/s) -host_mem_usage 194272 # Number of bytes of host memory used -host_seconds 51.72 # Real time elapsed on the host -host_tick_rate 67313414 # Simulator tick rate (ticks/s) +host_inst_rate 1269893 # Simulator instruction rate (inst/s) +host_mem_usage 197712 # Number of bytes of host memory used +host_seconds 48.70 # Real time elapsed on the host +host_tick_rate 74667785 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 58001813 # Number of instructions simulated -sim_seconds 1.740863 # Number of seconds simulated -sim_ticks 3481726167 # Number of ticks simulated -system.cpu.dtb.accesses 2309470 # DTB accesses +sim_insts 61839827 # Number of instructions simulated +sim_seconds 1.818060 # Number of seconds simulated +sim_ticks 3636120569 # Number of ticks simulated +system.cpu.dtb.accesses 1304498 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 13711941 # DTB hits -system.cpu.dtb.misses 12493 # DTB misses -system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.hits 16565944 # DTB hits +system.cpu.dtb.misses 11425 # DTB misses +system.cpu.dtb.read_accesses 900427 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 7597829 # DTB read hits -system.cpu.dtb.read_misses 10298 # DTB read misses -system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.read_hits 10044011 # DTB read hits +system.cpu.dtb.read_misses 10280 # DTB read misses +system.cpu.dtb.write_accesses 404071 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6114112 # DTB write hits -system.cpu.dtb.write_misses 2195 # DTB write misses -system.cpu.idle_fraction 0.983340 # Percentage of idle cycles -system.cpu.itb.accesses 3281346 # ITB accesses +system.cpu.dtb.write_hits 6521933 # DTB write hits +system.cpu.dtb.write_misses 1145 # DTB write misses +system.cpu.idle_fraction 0.982991 # Percentage of idle cycles +system.cpu.itb.accesses 3281310 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 3276356 # ITB hits +system.cpu.itb.hits 3276320 # ITB hits system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 182718 # number of callpals executed +system.cpu.kern.callpal 193942 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1574 0.86% 0.86% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed -system.cpu.kern.callpal_swpipl 171359 93.78% 94.68% # number of callpals executed -system.cpu.kern.callpal_rdps 5159 2.82% 97.50% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 97.51% # number of callpals executed -system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed -system.cpu.kern.callpal_rti 3829 2.10% 99.61% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4207 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 176844 91.18% 93.39% # number of callpals executed +system.cpu.kern.callpal_rdps 6881 3.55% 96.93% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_rti 5214 2.69% 99.63% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 202783 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 213009 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1877 # number of quiesce instructions executed -system.cpu.kern.ipl_count 177218 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74624 42.11% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 251 0.14% 42.25% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5425 3.06% 45.31% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 96918 54.69% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 158463 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74570 47.06% 47.06% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 251 0.16% 47.22% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5425 3.42% 50.64% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 78217 49.36% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3481725752 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3459659082 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 39982 0.00% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 930159 0.03% 99.39% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 21096529 0.61% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.894170 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999276 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6282 # number of quiesce instructions executed +system.cpu.kern.ipl_count 184158 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75390 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 245 0.13% 41.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1854 1.01% 42.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106669 57.92% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 150141 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74021 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1854 1.23% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 74021 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3636120154 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3601418096 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 40474 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 159444 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 34502140 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.815284 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981841 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.807043 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1939 +system.cpu.kern.ipl_used_31 0.693932 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1937 system.cpu.kern.mode_good_user 1757 -system.cpu.kern.mode_good_idle 182 -system.cpu.kern.mode_switch_kernel 3320 # number of protection mode switches +system.cpu.kern.mode_good_idle 180 +system.cpu.kern.mode_switch_kernel 5982 # number of protection mode switches system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2061 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.543289 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.584036 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_idle 2103 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.393619 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.323805 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.088307 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31887159 0.92% 0.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3591270 0.10% 1.02% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3446247321 98.98% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1575 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.085592 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 54647278 1.50% 1.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3591234 0.10% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3577881640 98.40% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4208 # number of times the context was actually changed system.cpu.kern.syscall 329 # number of syscalls executed system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed @@ -112,16 +112,16 @@ system.cpu.kern.syscall_connect 2 0.61% 97.57% # nu system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016660 # Percentage of non-idle cycles -system.cpu.numCycles 58006987 # number of cpu cycles simulated -system.cpu.num_insts 58001813 # Number of instructions executed -system.cpu.num_refs 13757191 # Number of memory references +system.cpu.not_idle_fraction 0.017009 # Percentage of non-idle cycles +system.cpu.numCycles 61845001 # number of cpu cycles simulated +system.cpu.num_insts 61839827 # Number of instructions executed +system.cpu.num_refs 16814484 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. -system.disk0.dma_write_txs 412 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. +system.disk0.dma_write_txs 408 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 6204251a5..4741dd710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index b3b3e8704..f7fe15009 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 5 2006 22:13:02 -M5 started Fri Oct 6 00:23:19 2006 +M5 compiled Oct 8 2006 14:07:02 +M5 started Sun Oct 8 14:07:07 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3481726167 because m5_exit instruction encountered +Exiting @ tick 3636120569 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 65401b549..8f75c9525 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -75,7 +75,7 @@ side_b=system.membus.port[0] type=TimingSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false dtb=system.cpu0.dtb function_trace=false @@ -104,7 +104,7 @@ size=48 type=TimingSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=1 defer_registration=false dtb=system.cpu1.dtb function_trace=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index ed03e445d..9e0948f1e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -90,9 +90,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 itb=system.cpu0.itb dtb=system.cpu0.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false @@ -118,9 +118,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=1 itb=system.cpu1.itb dtb=system.cpu1.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console index 4a397ddbf..57a610390 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 2 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -16,29 +16,27 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Bootstraping CPU 1 with sp=0xFFFFFC0000076000 unix_boot_mem ends at FFFFFC0000078000 k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028) - CallbackFixup 0 18000, t7=FFFFFC0000700000 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 memcluster 0, usage 1, start 0, end 392 memcluster 1, usage 0, start 392, end 16384 - freeing pages 1030:16384 - reserving pages 1030:1031 + freeing pages 1069:16384 + reserving pages 1069:1070 SMP: 2 CPUs probed -- cpu_present_mask = 3 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order 10: 16384 bytes) + PID hash table entries: 1024 (order: 10, 32768 bytes) Using epoch = 1900 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init) - Mount-cache hash table entries: 512 (order: 0, 8192 bytes) - per-CPU timeslice cutoff: 374.49 usecs. - task migration cache decay timeout: 0 msecs. + Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 SMP starting up secondaries. Slave CPU 1 console command START SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 @@ -53,16 +51,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb Initializing Cryptographic API rtc: Standard PC (1900) epoch (1900) detected Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered loop: loaded (max 8 devices) - Using anticipatory io scheduler nbd: registered device at major 43 sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + ns83820: irq bound to CPU 1 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver - eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX4: IDE controller at PCI slot 0000:00:00.0 @@ -75,24 +80,23 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) + hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported hdb: unknown partition table - scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0 - Vendor: Linux Model: scsi_m5 Li Rev: 0004 - Type: Direct-Access ANSI SCSI revision: 03 - SCSI device sda: 16384 512-byte hdwr sectors (8 MB) - SCSI device sda: drive cache: write back - sda: unknown partition table - Attached scsi disk sda at scsi0, channel 0, id 0, lun 0 mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 - IP: routing cache hash table of 1024 buckets, 16Kbytes - TCP: Hash tables configured (established 8192 bind 8192) - ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack ip_tables: (C) 2000-2002 Netfilter core team arp_tables: (C) 2002 David S. Miller + TCP bic registered Initializing IPsec netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 @@ -101,7 +105,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb 802.1Q VLAN Support v1.8 Ben Greear All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 480k freed + Freeing unused kernel memory: 224k freed init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index bf7320067..4f8408501 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,232 +1,231 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 825990 # Simulator instruction rate (inst/s) -host_mem_usage 193572 # Number of bytes of host memory used -host_seconds 74.01 # Real time elapsed on the host -host_tick_rate 47654938 # Simulator tick rate (ticks/s) +host_inst_rate 779301 # Simulator instruction rate (inst/s) +host_mem_usage 197344 # Number of bytes of host memory used +host_seconds 85.22 # Real time elapsed on the host +host_tick_rate 43826709 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61131962 # Number of instructions simulated -sim_seconds 1.763494 # Number of seconds simulated -sim_ticks 3526987181 # Number of ticks simulated -system.cpu0.dtb.accesses 1987164 # DTB accesses -system.cpu0.dtb.acv 291 # DTB access violations -system.cpu0.dtb.hits 10431590 # DTB hits -system.cpu0.dtb.misses 9590 # DTB misses -system.cpu0.dtb.read_accesses 606328 # DTB read accesses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 5831565 # DTB read hits -system.cpu0.dtb.read_misses 7663 # DTB read misses -system.cpu0.dtb.write_accesses 1380836 # DTB write accesses -system.cpu0.dtb.write_acv 117 # DTB write access violations -system.cpu0.dtb.write_hits 4600025 # DTB write hits -system.cpu0.dtb.write_misses 1927 # DTB write misses -system.cpu0.idle_fraction 0.984514 # Percentage of idle cycles -system.cpu0.itb.accesses 2372045 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 2368331 # ITB hits -system.cpu0.itb.misses 3714 # ITB misses -system.cpu0.kern.callpal 145084 # number of callpals executed +sim_insts 66411500 # Number of instructions simulated +sim_seconds 1.867451 # Number of seconds simulated +sim_ticks 3734901822 # Number of ticks simulated +system.cpu0.dtb.accesses 828318 # DTB accesses +system.cpu0.dtb.acv 315 # DTB access violations +system.cpu0.dtb.hits 13279471 # DTB hits +system.cpu0.dtb.misses 7094 # DTB misses +system.cpu0.dtb.read_accesses 572336 # DTB read accesses +system.cpu0.dtb.read_acv 200 # DTB read access violations +system.cpu0.dtb.read_hits 8207004 # DTB read hits +system.cpu0.dtb.read_misses 6394 # DTB read misses +system.cpu0.dtb.write_accesses 255982 # DTB write accesses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_hits 5072467 # DTB write hits +system.cpu0.dtb.write_misses 700 # DTB write misses +system.cpu0.idle_fraction 0.982495 # Percentage of idle cycles +system.cpu0.itb.accesses 1888651 # ITB accesses +system.cpu0.itb.acv 166 # ITB acv +system.cpu0.itb.hits 1885318 # ITB hits +system.cpu0.itb.misses 3333 # ITB misses +system.cpu0.kern.callpal 146866 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 54 0.04% 0.04% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.04% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1182 0.81% 0.85% # number of callpals executed -system.cpu0.kern.callpal_tbi 42 0.03% 0.88% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.89% # number of callpals executed -system.cpu0.kern.callpal_swpipl 135050 93.08% 93.97% # number of callpals executed -system.cpu0.kern.callpal_rdps 4795 3.30% 97.28% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal_wrusp 5 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal_rdusp 8 0.01% 97.29% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.29% # number of callpals executed -system.cpu0.kern.callpal_rti 3431 2.36% 99.65% # number of callpals executed -system.cpu0.kern.callpal_callsys 364 0.25% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 139 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 507 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2966 2.02% 2.37% # number of callpals executed +system.cpu0.kern.callpal_tbi 47 0.03% 2.40% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.40% # number of callpals executed +system.cpu0.kern.callpal_swpipl 132441 90.18% 92.58% # number of callpals executed +system.cpu0.kern.callpal_rdps 6235 4.25% 96.83% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal_wrusp 2 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 96.84% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal_rti 4201 2.86% 99.70% # number of callpals executed +system.cpu0.kern.callpal_callsys 317 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal_imb 128 0.09% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 160926 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 160336 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1958 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 140584 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 56549 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 251 0.18% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5487 3.90% 44.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 51 0.04% 44.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78246 55.66% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 122461 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 56518 46.15% 46.15% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 251 0.20% 46.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5487 4.48% 50.84% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 51 0.04% 50.88% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 60154 49.12% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3526986735 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3501352281 99.27% 99.27% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 53019 0.00% 99.27% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1348211 0.04% 99.31% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 18326 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 24214898 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.871088 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999452 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6712 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 139203 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 55746 40.05% 40.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 245 0.18% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1904 1.37% 41.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 411 0.30% 41.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 80897 58.11% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 112531 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 55191 49.05% 49.05% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 245 0.22% 49.26% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1904 1.69% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 411 0.37% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 54780 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3734378988 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3696129107 98.98% 98.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 53683 0.00% 98.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 224672 0.01% 98.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 128598 0.00% 98.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 37842928 1.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808395 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.990044 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.768781 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1448 -system.cpu0.kern.mode_good_user 1300 -system.cpu0.kern.mode_good_idle 148 -system.cpu0.kern.mode_switch_kernel 2490 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1300 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2110 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.490847 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.581526 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.677157 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1095 +system.cpu0.kern.mode_good_user 1095 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 6633 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1095 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.283385 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.165084 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.070142 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 23256451 0.66% 0.66% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3397192 0.10% 0.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3500333090 99.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1183 # number of times the context was actually changed -system.cpu0.kern.syscall 231 # number of syscalls executed -system.cpu0.kern.syscall_fork 6 2.60% 2.60% # number of syscalls executed -system.cpu0.kern.syscall_read 17 7.36% 9.96% # number of syscalls executed -system.cpu0.kern.syscall_write 4 1.73% 11.69% # number of syscalls executed -system.cpu0.kern.syscall_close 31 13.42% 25.11% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.43% 25.54% # number of syscalls executed -system.cpu0.kern.syscall_obreak 11 4.76% 30.30% # number of syscalls executed -system.cpu0.kern.syscall_lseek 6 2.60% 32.90% # number of syscalls executed -system.cpu0.kern.syscall_getpid 4 1.73% 34.63% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.87% 35.50% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.73% 37.23% # number of syscalls executed -system.cpu0.kern.syscall_access 9 3.90% 41.13% # number of syscalls executed -system.cpu0.kern.syscall_dup 2 0.87% 41.99% # number of syscalls executed -system.cpu0.kern.syscall_open 42 18.18% 60.17% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.73% 61.90% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 7 3.03% 64.94% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 9 3.90% 68.83% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.43% 69.26% # number of syscalls executed -system.cpu0.kern.syscall_execve 4 1.73% 71.00% # number of syscalls executed -system.cpu0.kern.syscall_mmap 35 15.15% 86.15% # number of syscalls executed -system.cpu0.kern.syscall_munmap 2 0.87% 87.01% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 10 4.33% 91.34% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.43% 91.77% # number of syscalls executed -system.cpu0.kern.syscall_dup2 2 0.87% 92.64% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 8 3.46% 96.10% # number of syscalls executed -system.cpu0.kern.syscall_socket 2 0.87% 96.97% # number of syscalls executed -system.cpu0.kern.syscall_connect 2 0.87% 97.84% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.87% 98.70% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 1 0.43% 99.13% # number of syscalls executed -system.cpu0.kern.syscall_setsid 2 0.87% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015486 # Percentage of non-idle cycles +system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 3730045371 99.93% 99.93% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2718822 0.07% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2967 # number of times the context was actually changed +system.cpu0.kern.syscall 179 # number of syscalls executed +system.cpu0.kern.syscall_fork 7 3.91% 3.91% # number of syscalls executed +system.cpu0.kern.syscall_read 14 7.82% 11.73% # number of syscalls executed +system.cpu0.kern.syscall_write 4 2.23% 13.97% # number of syscalls executed +system.cpu0.kern.syscall_close 27 15.08% 29.05% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.56% 29.61% # number of syscalls executed +system.cpu0.kern.syscall_obreak 6 3.35% 32.96% # number of syscalls executed +system.cpu0.kern.syscall_lseek 7 3.91% 36.87% # number of syscalls executed +system.cpu0.kern.syscall_getpid 4 2.23% 39.11% # number of syscalls executed +system.cpu0.kern.syscall_setuid 1 0.56% 39.66% # number of syscalls executed +system.cpu0.kern.syscall_getuid 3 1.68% 41.34% # number of syscalls executed +system.cpu0.kern.syscall_access 6 3.35% 44.69% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 1.12% 45.81% # number of syscalls executed +system.cpu0.kern.syscall_open 30 16.76% 62.57% # number of syscalls executed +system.cpu0.kern.syscall_getgid 3 1.68% 64.25% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 8 4.47% 68.72% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 8 4.47% 73.18% # number of syscalls executed +system.cpu0.kern.syscall_execve 5 2.79% 75.98% # number of syscalls executed +system.cpu0.kern.syscall_mmap 17 9.50% 85.47% # number of syscalls executed +system.cpu0.kern.syscall_munmap 3 1.68% 87.15% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 4 2.23% 89.39% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.56% 89.94% # number of syscalls executed +system.cpu0.kern.syscall_dup2 2 1.12% 91.06% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 4.47% 95.53% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 1.12% 96.65% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 1.12% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_setgid 1 0.56% 98.32% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 1.12% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.017505 # Percentage of non-idle cycles system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 44155958 # Number of instructions executed -system.cpu0.num_refs 10463340 # Number of memory references -system.cpu1.dtb.accesses 323344 # DTB accesses -system.cpu1.dtb.acv 82 # DTB access violations -system.cpu1.dtb.hits 4234985 # DTB hits -system.cpu1.dtb.misses 2977 # DTB misses -system.cpu1.dtb.read_accesses 222873 # DTB read accesses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 2431648 # DTB read hits -system.cpu1.dtb.read_misses 2698 # DTB read misses -system.cpu1.dtb.write_accesses 100471 # DTB write accesses -system.cpu1.dtb.write_acv 46 # DTB write access violations -system.cpu1.dtb.write_hits 1803337 # DTB write hits -system.cpu1.dtb.write_misses 279 # DTB write misses -system.cpu1.idle_fraction 0.993979 # Percentage of idle cycles -system.cpu1.itb.accesses 912010 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 910678 # ITB hits -system.cpu1.itb.misses 1332 # ITB misses -system.cpu1.kern.callpal 57529 # number of callpals executed +system.cpu0.num_insts 52039310 # Number of instructions executed +system.cpu0.num_refs 13510641 # Number of memory references +system.cpu1.dtb.accesses 477045 # DTB accesses +system.cpu1.dtb.acv 52 # DTB access violations +system.cpu1.dtb.hits 4567143 # DTB hits +system.cpu1.dtb.misses 4359 # DTB misses +system.cpu1.dtb.read_accesses 328553 # DTB read accesses +system.cpu1.dtb.read_acv 10 # DTB read access violations +system.cpu1.dtb.read_hits 2660612 # DTB read hits +system.cpu1.dtb.read_misses 3911 # DTB read misses +system.cpu1.dtb.write_accesses 148492 # DTB write accesses +system.cpu1.dtb.write_acv 42 # DTB write access violations +system.cpu1.dtb.write_hits 1906531 # DTB write hits +system.cpu1.dtb.write_misses 448 # DTB write misses +system.cpu1.idle_fraction 0.994923 # Percentage of idle cycles +system.cpu1.itb.accesses 1392687 # ITB accesses +system.cpu1.itb.acv 18 # ITB acv +system.cpu1.itb.hits 1391015 # ITB hits +system.cpu1.itb.misses 1672 # ITB misses +system.cpu1.kern.callpal 74475 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 51 0.09% 0.09% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.09% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu1.kern.callpal_swpctx 451 0.78% 0.88% # number of callpals executed -system.cpu1.kern.callpal_tbi 12 0.02% 0.90% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 0.91% # number of callpals executed -system.cpu1.kern.callpal_swpipl 54081 94.01% 94.92% # number of callpals executed -system.cpu1.kern.callpal_rdps 368 0.64% 95.56% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 95.56% # number of callpals executed -system.cpu1.kern.callpal_wrusp 2 0.00% 95.56% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.00% 95.57% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 95.57% # number of callpals executed -system.cpu1.kern.callpal_rti 2337 4.06% 99.63% # number of callpals executed -system.cpu1.kern.callpal_callsys 169 0.29% 99.93% # number of callpals executed -system.cpu1.kern.callpal_imb 41 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 411 0.55% 0.55% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.55% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.56% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2106 2.83% 3.38% # number of callpals executed +system.cpu1.kern.callpal_tbi 6 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal_swpipl 65169 87.50% 90.91% # number of callpals executed +system.cpu1.kern.callpal_rdps 2603 3.50% 94.40% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.40% # number of callpals executed +system.cpu1.kern.callpal_wrusp 5 0.01% 94.41% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 94.41% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.41% # number of callpals executed +system.cpu1.kern.callpal_rti 3893 5.23% 99.64% # number of callpals executed +system.cpu1.kern.callpal_callsys 214 0.29% 99.93% # number of callpals executed +system.cpu1.kern.callpal_imb 52 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 63811 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 82987 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1898 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 58267 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 25040 42.97% 42.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5452 9.36% 52.33% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 54 0.09% 52.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 27721 47.58% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 57331 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 25007 43.62% 43.62% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5452 9.51% 53.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 54 0.09% 53.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 26818 46.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3526422675 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3497592433 99.18% 99.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1410084 0.04% 99.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 19740 0.00% 99.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 27400418 0.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.983936 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998682 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2512 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 71472 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 27792 38.89% 38.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1902 2.66% 41.55% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 507 0.71% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 41271 57.74% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 55838 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 26968 48.30% 48.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1902 3.41% 51.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 507 0.91% 52.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 26461 47.39% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3734901376 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3704875983 99.20% 99.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 224436 0.01% 99.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 162794 0.00% 99.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 29638163 0.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.781257 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.970351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.967425 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 465 -system.cpu1.kern.mode_good_user 465 -system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 2771 # number of protection mode switches -system.cpu1.kern.mode_switch_user 465 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.287392 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.167809 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.641152 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 1094 +system.cpu1.kern.mode_good_user 662 +system.cpu1.kern.mode_good_idle 432 +system.cpu1.kern.mode_switch_kernel 2358 # number of protection mode switches +system.cpu1.kern.mode_switch_user 662 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2831 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.373953 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.463953 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle no value # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3525066043 99.96% 99.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1294184 0.04% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 452 # number of times the context was actually changed -system.cpu1.kern.syscall 98 # number of syscalls executed -system.cpu1.kern.syscall_fork 2 2.04% 2.04% # number of syscalls executed -system.cpu1.kern.syscall_read 13 13.27% 15.31% # number of syscalls executed -system.cpu1.kern.syscall_close 12 12.24% 27.55% # number of syscalls executed -system.cpu1.kern.syscall_chmod 1 1.02% 28.57% # number of syscalls executed -system.cpu1.kern.syscall_obreak 4 4.08% 32.65% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 4.08% 36.73% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 2.04% 38.78% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 2.04% 40.82% # number of syscalls executed -system.cpu1.kern.syscall_getuid 2 2.04% 42.86% # number of syscalls executed -system.cpu1.kern.syscall_access 2 2.04% 44.90% # number of syscalls executed -system.cpu1.kern.syscall_open 13 13.27% 58.16% # number of syscalls executed -system.cpu1.kern.syscall_getgid 2 2.04% 60.20% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 3 3.06% 63.27% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 1 1.02% 64.29% # number of syscalls executed -system.cpu1.kern.syscall_execve 3 3.06% 67.35% # number of syscalls executed -system.cpu1.kern.syscall_mmap 19 19.39% 86.73% # number of syscalls executed -system.cpu1.kern.syscall_munmap 1 1.02% 87.76% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 6 6.12% 93.88% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 1.02% 94.90% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 2 2.04% 96.94% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 2.04% 98.98% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 1.02% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.006021 # Percentage of non-idle cycles +system.cpu1.kern.mode_switch_good_idle 0.152596 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 13374855 0.36% 0.36% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1967356 0.05% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3719559163 99.59% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2107 # number of times the context was actually changed +system.cpu1.kern.syscall 150 # number of syscalls executed +system.cpu1.kern.syscall_fork 1 0.67% 0.67% # number of syscalls executed +system.cpu1.kern.syscall_read 16 10.67% 11.33% # number of syscalls executed +system.cpu1.kern.syscall_close 16 10.67% 22.00% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 0.67% 22.67% # number of syscalls executed +system.cpu1.kern.syscall_obreak 9 6.00% 28.67% # number of syscalls executed +system.cpu1.kern.syscall_lseek 3 2.00% 30.67% # number of syscalls executed +system.cpu1.kern.syscall_getpid 2 1.33% 32.00% # number of syscalls executed +system.cpu1.kern.syscall_setuid 3 2.00% 34.00% # number of syscalls executed +system.cpu1.kern.syscall_getuid 3 2.00% 36.00% # number of syscalls executed +system.cpu1.kern.syscall_access 5 3.33% 39.33% # number of syscalls executed +system.cpu1.kern.syscall_open 25 16.67% 56.00% # number of syscalls executed +system.cpu1.kern.syscall_getgid 3 2.00% 58.00% # number of syscalls executed +system.cpu1.kern.syscall_sigprocmask 2 1.33% 59.33% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 2 1.33% 60.67% # number of syscalls executed +system.cpu1.kern.syscall_readlink 1 0.67% 61.33% # number of syscalls executed +system.cpu1.kern.syscall_execve 2 1.33% 62.67% # number of syscalls executed +system.cpu1.kern.syscall_mmap 37 24.67% 87.33% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 12 8.00% 95.33% # number of syscalls executed +system.cpu1.kern.syscall_dup2 1 0.67% 96.00% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 1.33% 97.33% # number of syscalls executed +system.cpu1.kern.syscall_setgid 3 2.00% 99.33% # number of syscalls executed +system.cpu1.kern.syscall_getrlimit 1 0.67% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.005077 # Percentage of non-idle cycles system.cpu1.numCycles 0 # number of cpu cycles simulated -system.cpu1.num_insts 16976004 # Number of instructions executed -system.cpu1.num_refs 4251312 # Number of memory references +system.cpu1.num_insts 14372190 # Number of instructions executed +system.cpu1.num_refs 4596339 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. -system.disk0.dma_write_txs 412 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. +system.disk0.dma_write_txs 408 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 2191bd088..64d80c0d2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 271342: Trying to launch CPU number 1! +warn: 271343: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 2c496b914..3b92a25f9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 5 2006 22:13:02 -M5 started Fri Oct 6 00:26:09 2006 +M5 compiled Oct 8 2006 14:07:02 +M5 started Sun Oct 8 14:10:09 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3526987181 because m5_exit instruction encountered +Exiting @ tick 3734901822 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 7f27ca121..21d606051 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -75,7 +75,7 @@ side_b=system.membus.port[0] type=TimingSimpleCPU children=dtb itb clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false dtb=system.cpu.dtb function_trace=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index deba80368..73f9edaea 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -90,9 +90,9 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 itb=system.cpu.itb dtb=system.cpu.dtb -cpu_id=-1 profile=0 clock=1 defer_registration=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console index d6e3955cc..1d150a047 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC00008064E8, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 1 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -14,28 +14,26 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 unix_boot_mem ends at FFFFFC0000076000 k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1028) - CallbackFixup 0 18000, t7=FFFFFC0000700000 - Linux version 2.6.8.1 (binkertn@ziff.eecs.umich.edu) (gcc version 3.4.3) #36 SMP Mon May 2 19:50:53 EDT 2005 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 memcluster 0, usage 1, start 0, end 392 memcluster 1, usage 0, start 392, end 16384 - freeing pages 1030:16384 - reserving pages 1030:1031 + freeing pages 1069:16384 + reserving pages 1069:1070 SMP: 1 CPUs probed -- cpu_present_mask = 1 Built 1 zonelists Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order 10: 16384 bytes) + PID hash table entries: 1024 (order: 10, 32768 bytes) Using epoch = 1900 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 119072k/131072k available (3058k kernel code, 8680k reserved, 695k data, 480k init) - Mount-cache hash table entries: 512 (order: 0, 8192 bytes) - per-CPU timeslice cutoff: 374.49 usecs. - task migration cache decay timeout: 0 msecs. + Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 SMP mode deactivated. Brought up 1 CPUs SMP: Total of 1 processors activated (4002.20 BogoMIPS). @@ -48,16 +46,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Initializing Cryptographic API rtc: Standard PC (1900) epoch (1900) detected Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing disabled + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered loop: loaded (max 8 devices) - Using anticipatory io scheduler nbd: registered device at major 43 sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + ns83820: irq bound to CPU 0 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver - eth0: ns83820 v0.20: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=sg + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX4: IDE controller at PCI slot 0000:00:00.0 @@ -70,24 +75,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) + hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported hdb: unknown partition table - scsi0 : scsi_m5, version 1.73 [20040518], dev_size_mb=8, opts=0x0 - Vendor: Linux Model: scsi_m5 Li Rev: 0004 - Type: Direct-Access ANSI SCSI revision: 03 - SCSI device sda: 16384 512-byte hdwr sectors (8 MB) - SCSI device sda: drive cache: write back - sda: unknown partition table - Attached scsi disk sda at scsi0, channel 0, id 0, lun 0 mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 - IP: routing cache hash table of 1024 buckets, 16Kbytes - TCP: Hash tables configured (established 8192 bind 8192) - ip_conntrack version 2.1 (512 buckets, 4096 max) - 440 bytes per conntrack + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack ip_tables: (C) 2000-2002 Netfilter core team arp_tables: (C) 2002 David S. Miller + TCP bic registered Initializing IPsec netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 @@ -96,7 +100,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 802.1Q VLAN Support v1.8 Ben Greear All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 480k freed + Freeing unused kernel memory: 224k freed init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 1d45d41a9..8b1a2f192 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 820839 # Simulator instruction rate (inst/s) -host_mem_usage 193264 # Number of bytes of host memory used -host_seconds 70.65 # Real time elapsed on the host -host_tick_rate 49454399 # Simulator tick rate (ticks/s) +host_inst_rate 778282 # Simulator instruction rate (inst/s) +host_mem_usage 196900 # Number of bytes of host memory used +host_seconds 79.42 # Real time elapsed on the host +host_tick_rate 45984556 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 57989043 # Number of instructions simulated -sim_seconds 1.746889 # Number of seconds simulated -sim_ticks 3493777466 # Number of ticks simulated -system.cpu.dtb.accesses 2309470 # DTB accesses +sim_insts 61806956 # Number of instructions simulated +sim_seconds 1.825933 # Number of seconds simulated +sim_ticks 3651865694 # Number of ticks simulated +system.cpu.dtb.accesses 1304498 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 13707871 # DTB hits -system.cpu.dtb.misses 12493 # DTB misses -system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.hits 16557993 # DTB hits +system.cpu.dtb.misses 11425 # DTB misses +system.cpu.dtb.read_accesses 900427 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 7595606 # DTB read hits -system.cpu.dtb.read_misses 10298 # DTB read misses -system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.read_hits 10039007 # DTB read hits +system.cpu.dtb.read_misses 10280 # DTB read misses +system.cpu.dtb.write_accesses 404071 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6112265 # DTB write hits -system.cpu.dtb.write_misses 2195 # DTB write misses -system.cpu.idle_fraction 0.979465 # Percentage of idle cycles -system.cpu.itb.accesses 3281347 # ITB accesses +system.cpu.dtb.write_hits 6518986 # DTB write hits +system.cpu.dtb.write_misses 1145 # DTB write misses +system.cpu.idle_fraction 0.978522 # Percentage of idle cycles +system.cpu.itb.accesses 3281311 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 3276357 # ITB hits +system.cpu.itb.hits 3276321 # ITB hits system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 182454 # number of callpals executed +system.cpu.kern.callpal 194059 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1571 0.86% 0.86% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed -system.cpu.kern.callpal_swpipl 171092 93.77% 94.67% # number of callpals executed -system.cpu.kern.callpal_rdps 5160 2.83% 97.50% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 97.50% # number of callpals executed -system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed -system.cpu.kern.callpal_rti 3834 2.10% 99.61% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4207 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 176948 91.18% 93.38% # number of callpals executed +system.cpu.kern.callpal_rdps 6887 3.55% 96.93% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_rti 5221 2.69% 99.63% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 202524 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 213133 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1876 # number of quiesce instructions executed -system.cpu.kern.ipl_count 176961 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74471 42.08% 42.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 251 0.14% 42.23% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5439 3.07% 45.30% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 96800 54.70% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 158180 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74417 47.05% 47.05% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 251 0.16% 47.20% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5439 3.44% 50.64% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 78073 49.36% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3493777020 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3466334940 99.21% 99.21% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 53019 0.00% 99.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 1268195 0.04% 99.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 26120866 0.75% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.893869 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999275 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6280 # number of quiesce instructions executed +system.cpu.kern.ipl_count 184276 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75422 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 245 0.13% 41.06% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1861 1.01% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106748 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 150212 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74053 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1861 1.24% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 74053 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3651865248 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3611061665 98.88% 98.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 53683 0.00% 98.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 219598 0.01% 98.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 40530302 1.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.815147 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981849 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.806539 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1938 -system.cpu.kern.mode_good_user 1757 -system.cpu.kern.mode_good_idle 181 -system.cpu.kern.mode_switch_kernel 3323 # number of protection mode switches -system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2060 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.542857 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.583208 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.693718 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1935 +system.cpu.kern.mode_good_user 1755 +system.cpu.kern.mode_good_idle 180 +system.cpu.kern.mode_switch_kernel 5988 # number of protection mode switches +system.cpu.kern.mode_switch_user 1755 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2104 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.393013 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.323146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.087864 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 39254786 1.12% 1.12% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 4685669 0.13% 1.26% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3449836563 98.74% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1572 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.085551 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 58882589 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4685612 0.13% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3588297045 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4208 # number of times the context was actually changed system.cpu.kern.syscall 329 # number of syscalls executed system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed @@ -112,16 +112,16 @@ system.cpu.kern.syscall_connect 2 0.61% 97.57% # nu system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.020535 # Percentage of non-idle cycles +system.cpu.not_idle_fraction 0.021478 # Percentage of non-idle cycles system.cpu.numCycles 0 # number of cpu cycles simulated -system.cpu.num_insts 57989043 # Number of instructions executed -system.cpu.num_refs 13753099 # Number of memory references +system.cpu.num_insts 61806956 # Number of instructions executed +system.cpu.num_refs 16806539 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. -system.disk0.dma_write_txs 412 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. +system.disk0.dma_write_txs 408 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -130,9 +130,9 @@ system.disk2.dma_write_full_pages 1 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no value # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedSwi no value # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 6204251a5..4741dd710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 88e69a41f..8c667881d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 5 2006 22:13:02 -M5 started Fri Oct 6 00:24:58 2006 +M5 compiled Oct 8 2006 14:07:02 +M5 started Sun Oct 8 14:08:49 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3493777466 because m5_exit instruction encountered +Exiting @ tick 3651865694 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 8722c1b67..95cccfbf2 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 6ae80aecf..1138f2dbe 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -36,6 +36,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 9fdf1d513..bbc6e55b5 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1393697 # Simulator instruction rate (inst/s) +host_inst_rate 1432213 # Simulator instruction rate (inst/s) host_mem_usage 147652 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 1391995 # Simulator tick rate (ticks/s) +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 1430432 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 207a0046c..de2559c1c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 11:12:49 -M5 started Sat Oct 7 11:13:17 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:58 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index f4bdc8171..72ea32994 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index 71a6d33c4..14eb07351 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -75,6 +75,7 @@ max_loads_all_threads=0 progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index f8d2c4ea7..2a6a055ab 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 618043 # Simulator instruction rate (inst/s) -host_mem_usage 159232 # Number of bytes of host memory used -host_seconds 0.81 # Real time elapsed on the host -host_tick_rate 843177 # Simulator tick rate (ticks/s) +host_inst_rate 598582 # Simulator instruction rate (inst/s) +host_mem_usage 159216 # Number of bytes of host memory used +host_seconds 0.84 # Real time elapsed on the host +host_tick_rate 816632 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 409068a91..70c3f2454 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 7 2006 12:38:12 -M5 started Sat Oct 7 12:38:52 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:59 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Exiting @ tick 682488 because a thread reached the max instruction count -- cgit v1.2.3 From 0a3e4d56e5d7d9aad4a34dc561a5b4fa84337c5f Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 8 Oct 2006 21:08:27 -0400 Subject: Update stats for functional path fix --HG-- extra : convert_revision : 0f38abab28e7e44f1dc748c25938185651dd1b7d --- .../00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 30 ++++---- .../00.hello/ref/alpha/linux/o3-timing/stderr | 9 +++ .../00.hello/ref/alpha/linux/o3-timing/stdout | 4 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 30 ++++---- .../ref/alpha/linux/o3-timing/m5stats.txt | 84 +++++++++++----------- .../ref/alpha/linux/o3-timing/stderr | 18 +++++ .../ref/alpha/linux/o3-timing/stdout | 4 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 32 ++++----- .../ref/alpha/eio/simple-timing/stdout | 4 +- 9 files changed, 116 insertions(+), 99 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index b8dbf28af..59cda42d9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted global.BPredUnit.lookups 2254 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 1748 # Simulator instruction rate (inst/s) -host_mem_usage 160364 # Number of bytes of host memory used -host_seconds 3.22 # Real time elapsed on the host -host_tick_rate 2135 # Simulator tick rate (ticks/s) +host_inst_rate 46995 # Simulator instruction rate (inst/s) +host_mem_usage 160420 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 57256 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. @@ -334,41 +334,39 @@ system.cpu.l2cache.ReadReq_misses 492 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.008130 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.991935 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.991935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 496 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 4 # number of overall hits +system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.991935 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses system.cpu.l2cache.overall_misses 492 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.991935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -385,7 +383,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 6869 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8893caac8..558105896 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,12 @@ warn: Entering event queue @ 0. Starting simulation... warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 718827a30..f2a1151c4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:45 2006 +M5 compiled Oct 8 2006 20:54:51 +M5 started Sun Oct 8 20:55:10 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Exiting @ tick 6868 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 757bbb920..2ee3181d8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 98835 # Simulator instruction rate (inst/s) -host_mem_usage 159632 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 144603 # Simulator tick rate (ticks/s) +host_inst_rate 292635 # Simulator instruction rate (inst/s) +host_mem_usage 159688 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 422303 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -153,41 +153,39 @@ system.cpu.l2cache.ReadReq_misses 441 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006803 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002268 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.993243 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.993243 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.993243 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.993243 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -204,7 +202,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 15172b43c..9871af3ab 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1081 # Nu global.BPredUnit.condPredicted 2449 # Number of conditional branches predicted global.BPredUnit.lookups 4173 # Number of BP lookups global.BPredUnit.usedRAS 551 # Number of times the RAS was used to get a target. -host_inst_rate 40630 # Simulator instruction rate (inst/s) -host_mem_usage 161244 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 30458 # Simulator tick rate (ticks/s) +host_inst_rate 48339 # Simulator instruction rate (inst/s) +host_mem_usage 161300 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 36232 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. @@ -193,7 +193,7 @@ system.cpu.dcache.overall_mshr_miss_latency_0 741 system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.075551 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_0 0.075551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_0 343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses @@ -476,20 +476,20 @@ system.cpu.ipc_1 0.666272 # IP system.cpu.ipc_total 1.332425 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8158 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist -(null) 2 0.02% # Type of FU issued -IntAlu 5514 67.59% # Type of FU issued -IntMult 1 0.01% # Type of FU issued -IntDiv 0 0.00% # Type of FU issued -FloatAdd 2 0.02% # Type of FU issued -FloatCmp 0 0.00% # Type of FU issued -FloatCvt 0 0.00% # Type of FU issued -FloatMult 0 0.00% # Type of FU issued -FloatDiv 0 0.00% # Type of FU issued -FloatSqrt 0 0.00% # Type of FU issued -MemRead 1662 20.37% # Type of FU issued -MemWrite 977 11.98% # Type of FU issued -IprAccess 0 0.00% # Type of FU issued -InstPrefetch 0 0.00% # Type of FU issued + (null) 2 0.02% # Type of FU issued + IntAlu 5514 67.59% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1662 20.37% # Type of FU issued + MemWrite 977 11.98% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist @@ -590,35 +590,31 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994802 # m system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994802 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 957 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses_0 957 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReq_accesses 4 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_accesses_0 4 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_hits 4 # number of WriteReq hits -system.cpu.l2cache.WriteReq_hits_0 4 # number of WriteReq hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009404 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005225 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2.059561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_0 2.059561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 no value # average overall mshr miss latency -system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 5 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1971 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_0 1971 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.990683 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.990683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.994802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.994802 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 957 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 957 # number of demand (read+write) misses @@ -629,8 +625,8 @@ system.cpu.l2cache.demand_mshr_hits_1 0 # nu system.cpu.l2cache.demand_mshr_miss_latency 957 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_0 957 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.990683 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.990683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.994802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.994802 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 957 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 957 # number of demand (read+write) MSHR misses @@ -640,8 +636,8 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2.059561 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_0 2.059561 # average overall miss latency @@ -652,14 +648,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency_1 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9 # number of overall hits -system.cpu.l2cache.overall_hits_0 9 # number of overall hits +system.cpu.l2cache.overall_hits 5 # number of overall hits +system.cpu.l2cache.overall_hits_0 5 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1971 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_0 1971 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.990683 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.990683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.994802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.994802 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 957 # number of overall misses system.cpu.l2cache.overall_misses_0 957 # number of overall misses @@ -670,8 +666,8 @@ system.cpu.l2cache.overall_mshr_hits_1 0 # nu system.cpu.l2cache.overall_mshr_miss_latency 957 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_0 957 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.990683 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.990683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.994802 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.994802 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 957 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_0 957 # number of overall MSHR misses @@ -699,7 +695,7 @@ system.cpu.l2cache.soft_prefetch_mshr_full 0 # system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 558.911632 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 890488cd2..48d711163 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -2,3 +2,21 @@ warn: Entering event queue @ 0. Starting simulation... warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 6b640d359..41cca6f14 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:56 2006 +M5 compiled Oct 8 2006 20:54:51 +M5 started Sun Oct 8 20:55:24 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Exiting @ tick 8441 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 2a6a055ab..ebc70e1f0 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 598582 # Simulator instruction rate (inst/s) -host_mem_usage 159216 # Number of bytes of host memory used -host_seconds 0.84 # Real time elapsed on the host -host_tick_rate 816632 # Simulator tick rate (ticks/s) +host_inst_rate 620088 # Simulator instruction rate (inst/s) +host_mem_usage 159272 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host +host_tick_rate 845969 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses @@ -152,41 +152,39 @@ system.cpu.l2cache.ReadReq_misses 857 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReq_accesses 165 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_hits 165 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.192532 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1022 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 165 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.838552 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.838552 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 1022 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 165 # number of overall hits +system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.838552 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.838552 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -203,7 +201,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use -system.cpu.l2cache.total_refs 165 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 70c3f2454..076cf0a5a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:59 2006 +M5 compiled Oct 8 2006 20:54:51 +M5 started Sun Oct 8 20:55:29 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Exiting @ tick 682488 because a thread reached the max instruction count -- cgit v1.2.3 From ce6c752ede773388da21dd05f6eff20398a1f447 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sun, 8 Oct 2006 22:05:34 -0400 Subject: update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it). tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: update for m5 base linux. --HG-- extra : convert_revision : c78a1748bf8a0950450c29a7b96bb8735c1bb3d2 --- .../console.system.sim_console | 8 +- .../linux/tsunami-simple-atomic-dual/m5stats.txt | 377 ++++++++++----------- .../alpha/linux/tsunami-simple-atomic-dual/stderr | 6 +- .../alpha/linux/tsunami-simple-atomic-dual/stdout | 8 +- .../console.system.sim_console | 8 +- .../alpha/linux/tsunami-simple-atomic/m5stats.txt | 102 +++--- .../ref/alpha/linux/tsunami-simple-atomic/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-atomic/stdout | 8 +- .../console.system.sim_console | 8 +- .../linux/tsunami-simple-timing-dual/m5stats.txt | 168 ++++----- .../alpha/linux/tsunami-simple-timing-dual/stderr | 6 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 8 +- .../console.system.sim_console | 8 +- .../alpha/linux/tsunami-simple-timing/m5stats.txt | 98 +++--- .../ref/alpha/linux/tsunami-simple-timing/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 8 +- 16 files changed, 410 insertions(+), 419 deletions(-) (limited to 'tests') diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console index 57a610390..27adebb82 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 2 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -19,7 +19,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) CallbackFixup 0 18000, t7=FFFFFC000070C000 Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 @@ -35,7 +35,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) Mount-cache hash table entries: 512 SMP starting up secondaries. Slave CPU 1 console command START @@ -59,9 +59,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb io scheduler cfq registered loop: loaded (max 8 devices) nbd: registered device at major 43 - sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - ns83820: irq bound to CPU 1 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 537721d92..e76c1d683 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,219 +1,218 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1292093 # Simulator instruction rate (inst/s) -host_mem_usage 197872 # Number of bytes of host memory used -host_seconds 51.53 # Real time elapsed on the host -host_tick_rate 72118724 # Simulator tick rate (ticks/s) +host_inst_rate 1270607 # Simulator instruction rate (inst/s) +host_mem_usage 197696 # Number of bytes of host memory used +host_seconds 51.09 # Real time elapsed on the host +host_tick_rate 72782461 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 66579941 # Number of instructions simulated -sim_seconds 1.858108 # Number of seconds simulated -sim_ticks 3716216351 # Number of ticks simulated -system.cpu0.dtb.accesses 604194 # DTB accesses -system.cpu0.dtb.acv 337 # DTB access violations -system.cpu0.dtb.hits 12597930 # DTB hits -system.cpu0.dtb.misses 7857 # DTB misses -system.cpu0.dtb.read_accesses 426113 # DTB read accesses +sim_insts 64909600 # Number of instructions simulated +sim_seconds 1.859078 # Number of seconds simulated +sim_ticks 3718155709 # Number of ticks simulated +system.cpu0.dtb.accesses 544556 # DTB accesses +system.cpu0.dtb.acv 335 # DTB access violations +system.cpu0.dtb.hits 14841931 # DTB hits +system.cpu0.dtb.misses 7356 # DTB misses +system.cpu0.dtb.read_accesses 377530 # DTB read accesses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_hits 7793080 # DTB read hits -system.cpu0.dtb.read_misses 7107 # DTB read misses -system.cpu0.dtb.write_accesses 178081 # DTB write accesses -system.cpu0.dtb.write_acv 127 # DTB write access violations -system.cpu0.dtb.write_hits 4804850 # DTB write hits -system.cpu0.dtb.write_misses 750 # DTB write misses -system.cpu0.idle_fraction 0.986701 # Percentage of idle cycles -system.cpu0.itb.accesses 1567177 # ITB accesses +system.cpu0.dtb.read_hits 8970576 # DTB read hits +system.cpu0.dtb.read_misses 6581 # DTB read misses +system.cpu0.dtb.write_accesses 167026 # DTB write accesses +system.cpu0.dtb.write_acv 125 # DTB write access violations +system.cpu0.dtb.write_hits 5871355 # DTB write hits +system.cpu0.dtb.write_misses 775 # DTB write misses +system.cpu0.idle_fraction 0.984943 # Percentage of idle cycles +system.cpu0.itb.accesses 1436270 # ITB accesses system.cpu0.itb.acv 184 # ITB acv -system.cpu0.itb.hits 1563535 # ITB hits -system.cpu0.itb.misses 3642 # ITB misses -system.cpu0.kern.callpal 140535 # number of callpals executed +system.cpu0.itb.hits 1432801 # ITB hits +system.cpu0.itb.misses 3469 # ITB misses +system.cpu0.kern.callpal 182754 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 567 0.40% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.41% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.41% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2926 2.08% 2.49% # number of callpals executed -system.cpu0.kern.callpal_tbi 49 0.03% 2.52% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.53% # number of callpals executed -system.cpu0.kern.callpal_swpipl 126411 89.95% 92.48% # number of callpals executed -system.cpu0.kern.callpal_rdps 5784 4.12% 96.59% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.59% # number of callpals executed -system.cpu0.kern.callpal_wrusp 2 0.00% 96.60% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.01% 96.60% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.60% # number of callpals executed -system.cpu0.kern.callpal_rti 4273 3.04% 99.64% # number of callpals executed -system.cpu0.kern.callpal_callsys 366 0.26% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 134 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 115 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3791 2.07% 2.14% # number of callpals executed +system.cpu0.kern.callpal_tbi 49 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal_swpipl 167832 91.83% 94.01% # number of callpals executed +system.cpu0.kern.callpal_rdps 5780 3.16% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrusp 2 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal_rti 4696 2.57% 99.75% # number of callpals executed +system.cpu0.kern.callpal_callsys 344 0.19% 99.93% # number of callpals executed +system.cpu0.kern.callpal_imb 122 0.07% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 155157 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 196249 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 6712 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 133285 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53228 39.94% 39.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 245 0.18% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1895 1.42% 41.54% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 460 0.35% 41.89% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 77457 58.11% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 107676 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 52768 49.01% 49.01% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 245 0.23% 49.23% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1895 1.76% 50.99% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 460 0.43% 51.42% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52308 48.58% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3716215936 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3683825506 99.13% 99.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 162970 0.00% 99.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 103364 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 32083622 0.86% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.807863 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.991358 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6184 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174678 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70736 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 245 0.14% 40.64% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1896 1.09% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101793 58.27% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 140889 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69374 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 245 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1896 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69366 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3718155294 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3683661066 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 163056 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 2026 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 34288672 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.806564 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675317 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1221 -system.cpu0.kern.mode_good_user 1222 +system.cpu0.kern.ipl_used_31 0.681442 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1192 +system.cpu0.kern.mode_good_user 1193 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6758 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1222 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7143 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.306140 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.180675 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.286108 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.166877 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3714429703 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1786231 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3716512331 99.96% 99.96% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 1642961 0.04% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2927 # number of times the context was actually changed -system.cpu0.kern.syscall 217 # number of syscalls executed -system.cpu0.kern.syscall_fork 8 3.69% 3.69% # number of syscalls executed -system.cpu0.kern.syscall_read 19 8.76% 12.44% # number of syscalls executed -system.cpu0.kern.syscall_write 3 1.38% 13.82% # number of syscalls executed -system.cpu0.kern.syscall_close 31 14.29% 28.11% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.46% 28.57% # number of syscalls executed -system.cpu0.kern.syscall_obreak 6 2.76% 31.34% # number of syscalls executed -system.cpu0.kern.syscall_lseek 10 4.61% 35.94% # number of syscalls executed -system.cpu0.kern.syscall_getpid 6 2.76% 38.71% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.92% 39.63% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.84% 41.47% # number of syscalls executed -system.cpu0.kern.syscall_access 6 2.76% 44.24% # number of syscalls executed -system.cpu0.kern.syscall_dup 2 0.92% 45.16% # number of syscalls executed -system.cpu0.kern.syscall_open 33 15.21% 60.37% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.84% 62.21% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 10 4.61% 66.82% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 9 4.15% 70.97% # number of syscalls executed -system.cpu0.kern.syscall_execve 6 2.76% 73.73% # number of syscalls executed -system.cpu0.kern.syscall_mmap 25 11.52% 85.25% # number of syscalls executed -system.cpu0.kern.syscall_munmap 3 1.38% 86.64% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 7 3.23% 89.86% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.46% 90.32% # number of syscalls executed -system.cpu0.kern.syscall_dup2 3 1.38% 91.71% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 8 3.69% 95.39% # number of syscalls executed -system.cpu0.kern.syscall_socket 2 0.92% 96.31% # number of syscalls executed -system.cpu0.kern.syscall_connect 2 0.92% 97.24% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.92% 98.16% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 2 0.92% 99.08% # number of syscalls executed -system.cpu0.kern.syscall_setsid 2 0.92% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.013299 # Percentage of non-idle cycles -system.cpu0.numCycles 49421041 # number of cpu cycles simulated -system.cpu0.num_insts 49417215 # Number of instructions executed -system.cpu0.num_refs 12829669 # Number of memory references -system.cpu1.dtb.accesses 701326 # DTB accesses -system.cpu1.dtb.acv 30 # DTB access violations -system.cpu1.dtb.hits 5286923 # DTB hits -system.cpu1.dtb.misses 3658 # DTB misses -system.cpu1.dtb.read_accesses 474933 # DTB read accesses +system.cpu0.kern.swap_context 3792 # number of times the context was actually changed +system.cpu0.kern.syscall 199 # number of syscalls executed +system.cpu0.kern.syscall_fork 8 4.02% 4.02% # number of syscalls executed +system.cpu0.kern.syscall_read 17 8.54% 12.56% # number of syscalls executed +system.cpu0.kern.syscall_write 4 2.01% 14.57% # number of syscalls executed +system.cpu0.kern.syscall_close 29 14.57% 29.15% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.50% 29.65% # number of syscalls executed +system.cpu0.kern.syscall_obreak 4 2.01% 31.66% # number of syscalls executed +system.cpu0.kern.syscall_lseek 10 5.03% 36.68% # number of syscalls executed +system.cpu0.kern.syscall_getpid 6 3.02% 39.70% # number of syscalls executed +system.cpu0.kern.syscall_setuid 1 0.50% 40.20% # number of syscalls executed +system.cpu0.kern.syscall_getuid 3 1.51% 41.71% # number of syscalls executed +system.cpu0.kern.syscall_access 6 3.02% 44.72% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 1.01% 45.73% # number of syscalls executed +system.cpu0.kern.syscall_open 31 15.58% 61.31% # number of syscalls executed +system.cpu0.kern.syscall_getgid 3 1.51% 62.81% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 10 5.03% 67.84% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 4.52% 72.36% # number of syscalls executed +system.cpu0.kern.syscall_execve 6 3.02% 75.38% # number of syscalls executed +system.cpu0.kern.syscall_mmap 20 10.05% 85.43% # number of syscalls executed +system.cpu0.kern.syscall_munmap 3 1.51% 86.93% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 5 2.51% 89.45% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.50% 89.95% # number of syscalls executed +system.cpu0.kern.syscall_dup2 3 1.51% 91.46% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 4.02% 95.48% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 1.01% 96.48% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 1.01% 97.49% # number of syscalls executed +system.cpu0.kern.syscall_setgid 1 0.50% 97.99% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 2 1.01% 98.99% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 1.01% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015057 # Percentage of non-idle cycles +system.cpu0.numCycles 55984201 # number of cpu cycles simulated +system.cpu0.num_insts 55980548 # Number of instructions executed +system.cpu0.num_refs 15081320 # Number of memory references +system.cpu1.dtb.accesses 761000 # DTB accesses +system.cpu1.dtb.acv 32 # DTB access violations +system.cpu1.dtb.hits 2653187 # DTB hits +system.cpu1.dtb.misses 4173 # DTB misses +system.cpu1.dtb.read_accesses 523552 # DTB read accesses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 3100008 # DTB read hits -system.cpu1.dtb.read_misses 3260 # DTB read misses -system.cpu1.dtb.write_accesses 226393 # DTB write accesses -system.cpu1.dtb.write_acv 30 # DTB write access violations -system.cpu1.dtb.write_hits 2186915 # DTB write hits -system.cpu1.dtb.write_misses 398 # DTB write misses -system.cpu1.idle_fraction 0.995381 # Percentage of idle cycles -system.cpu1.itb.accesses 1714255 # ITB accesses +system.cpu1.dtb.read_hits 1675663 # DTB read hits +system.cpu1.dtb.read_misses 3798 # DTB read misses +system.cpu1.dtb.write_accesses 237448 # DTB write accesses +system.cpu1.dtb.write_acv 32 # DTB write access violations +system.cpu1.dtb.write_hits 977524 # DTB write hits +system.cpu1.dtb.write_misses 375 # DTB write misses +system.cpu1.idle_fraction 0.997598 # Percentage of idle cycles +system.cpu1.itb.accesses 1845187 # ITB accesses system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 1712856 # ITB hits -system.cpu1.itb.misses 1399 # ITB misses -system.cpu1.kern.callpal 81795 # number of callpals executed +system.cpu1.itb.hits 1843600 # ITB hits +system.cpu1.itb.misses 1587 # ITB misses +system.cpu1.kern.callpal 34405 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 460 0.56% 0.56% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.57% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2245 2.74% 3.31% # number of callpals executed -system.cpu1.kern.callpal_tbi 4 0.00% 3.32% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.32% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71908 87.91% 91.24% # number of callpals executed -system.cpu1.kern.callpal_rdps 3034 3.71% 94.95% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.95% # number of callpals executed -system.cpu1.kern.callpal_wrusp 5 0.01% 94.95% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.96% # number of callpals executed -system.cpu1.kern.callpal_rti 3913 4.78% 99.74% # number of callpals executed -system.cpu1.kern.callpal_callsys 165 0.20% 99.94% # number of callpals executed -system.cpu1.kern.callpal_imb 46 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 468 1.36% 1.39% # number of callpals executed +system.cpu1.kern.callpal_tbi 5 0.01% 1.41% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.43% # number of callpals executed +system.cpu1.kern.callpal_swpipl 28030 81.47% 82.90% # number of callpals executed +system.cpu1.kern.callpal_rdps 3042 8.84% 91.74% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.74% # number of callpals executed +system.cpu1.kern.callpal_wrusp 5 0.01% 91.76% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.77% # number of callpals executed +system.cpu1.kern.callpal_rti 2586 7.52% 99.28% # number of callpals executed +system.cpu1.kern.callpal_callsys 187 0.54% 99.83% # number of callpals executed +system.cpu1.kern.callpal_imb 59 0.17% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 89345 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 42209 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 2592 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78283 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30809 39.36% 39.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1894 2.42% 41.78% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 567 0.72% 42.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45013 57.50% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61674 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29890 48.46% 48.46% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1894 3.07% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 567 0.92% 52.45% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 29323 47.55% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3715795413 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3690163762 99.31% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 162884 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 130370 0.00% 99.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 25338397 0.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.787834 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.970171 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2146 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 32627 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 11165 34.22% 34.22% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1895 5.81% 40.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 115 0.35% 40.38% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 19452 59.62% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 24195 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 11150 46.08% 46.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1895 7.83% 53.92% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 115 0.48% 54.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 11035 45.61% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3717733449 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3695802393 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 162970 0.00% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 29122 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 21738964 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.741564 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.998657 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.651434 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1028 -system.cpu1.kern.mode_good_user 535 -system.cpu1.kern.mode_good_idle 493 -system.cpu1.kern.mode_switch_kernel 2307 # number of protection mode switches -system.cpu1.kern.mode_switch_user 535 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2948 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.355095 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.445600 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.567294 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 602 +system.cpu1.kern.mode_good_user 563 +system.cpu1.kern.mode_good_idle 39 +system.cpu1.kern.mode_switch_kernel 1011 # number of protection mode switches +system.cpu1.kern.mode_switch_user 563 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2045 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.332689 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.595450 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.167232 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 12634755 0.34% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1807179 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3700889452 99.61% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2246 # number of times the context was actually changed -system.cpu1.kern.syscall 112 # number of syscalls executed -system.cpu1.kern.syscall_read 11 9.82% 9.82% # number of syscalls executed -system.cpu1.kern.syscall_write 1 0.89% 10.71% # number of syscalls executed -system.cpu1.kern.syscall_close 12 10.71% 21.43% # number of syscalls executed -system.cpu1.kern.syscall_chmod 1 0.89% 22.32% # number of syscalls executed -system.cpu1.kern.syscall_obreak 9 8.04% 30.36% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 1.79% 32.14% # number of syscalls executed -system.cpu1.kern.syscall_getuid 2 1.79% 33.93% # number of syscalls executed -system.cpu1.kern.syscall_access 5 4.46% 38.39% # number of syscalls executed -system.cpu1.kern.syscall_open 22 19.64% 58.04% # number of syscalls executed -system.cpu1.kern.syscall_getgid 2 1.79% 59.82% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 1 0.89% 60.71% # number of syscalls executed -system.cpu1.kern.syscall_readlink 1 0.89% 61.61% # number of syscalls executed -system.cpu1.kern.syscall_execve 1 0.89% 62.50% # number of syscalls executed -system.cpu1.kern.syscall_mmap 29 25.89% 88.39% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 9 8.04% 96.43% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 2 1.79% 98.21% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 1.79% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.004619 # Percentage of non-idle cycles -system.cpu1.numCycles 17164125 # number of cpu cycles simulated -system.cpu1.num_insts 17162726 # Number of instructions executed -system.cpu1.num_refs 5316705 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.019071 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 4713507 0.13% 0.13% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1950903 0.05% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3710606044 99.82% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 469 # number of times the context was actually changed +system.cpu1.kern.syscall 130 # number of syscalls executed +system.cpu1.kern.syscall_read 13 10.00% 10.00% # number of syscalls executed +system.cpu1.kern.syscall_close 14 10.77% 20.77% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 0.77% 21.54% # number of syscalls executed +system.cpu1.kern.syscall_obreak 11 8.46% 30.00% # number of syscalls executed +system.cpu1.kern.syscall_setuid 3 2.31% 32.31% # number of syscalls executed +system.cpu1.kern.syscall_getuid 3 2.31% 34.62% # number of syscalls executed +system.cpu1.kern.syscall_access 5 3.85% 38.46% # number of syscalls executed +system.cpu1.kern.syscall_open 24 18.46% 56.92% # number of syscalls executed +system.cpu1.kern.syscall_getgid 3 2.31% 59.23% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 0.77% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_readlink 1 0.77% 60.77% # number of syscalls executed +system.cpu1.kern.syscall_execve 1 0.77% 61.54% # number of syscalls executed +system.cpu1.kern.syscall_mmap 34 26.15% 87.69% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 11 8.46% 96.15% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 1.54% 97.69% # number of syscalls executed +system.cpu1.kern.syscall_setgid 3 2.31% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.002402 # Percentage of non-idle cycles +system.cpu1.numCycles 8930639 # number of cpu cycles simulated +system.cpu1.num_insts 8929052 # Number of instructions executed +system.cpu1.num_refs 2665347 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index d55b33424..14aa2c9ff 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,6 +1,6 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 195723: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 76bd8d3c2..18365db1c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:07:02 -M5 started Sun Oct 8 14:07:57 2006 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Oct 8 2006 21:57:24 +M5 started Sun Oct 8 21:58:13 2006 +M5 executing on zed.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3716216351 because m5_exit instruction encountered +Exiting @ tick 3718155709 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console index 1d150a047..5461cc4ab 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 1 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -16,7 +16,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 k_argc = 0 jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 @@ -32,7 +32,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) Mount-cache hash table entries: 512 SMP mode deactivated. Brought up 1 CPUs @@ -54,9 +54,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 io scheduler cfq registered loop: loaded (max 8 devices) nbd: registered device at major 43 - sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - ns83820: irq bound to CPU 0 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index c9661f182..e276e91a7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1269893 # Simulator instruction rate (inst/s) -host_mem_usage 197712 # Number of bytes of host memory used -host_seconds 48.70 # Real time elapsed on the host -host_tick_rate 74667785 # Simulator tick rate (ticks/s) +host_inst_rate 1389289 # Simulator instruction rate (inst/s) +host_mem_usage 197652 # Number of bytes of host memory used +host_seconds 44.48 # Real time elapsed on the host +host_tick_rate 81712411 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61839827 # Number of instructions simulated -sim_seconds 1.818060 # Number of seconds simulated -sim_ticks 3636120569 # Number of ticks simulated -system.cpu.dtb.accesses 1304498 # DTB accesses +sim_insts 61788439 # Number of instructions simulated +sim_seconds 1.817090 # Number of seconds simulated +sim_ticks 3634179176 # Number of ticks simulated +system.cpu.dtb.accesses 1304494 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16565944 # DTB hits +system.cpu.dtb.hits 16552094 # DTB hits system.cpu.dtb.misses 11425 # DTB misses -system.cpu.dtb.read_accesses 900427 # DTB read accesses +system.cpu.dtb.read_accesses 900425 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10044011 # DTB read hits +system.cpu.dtb.read_hits 10038384 # DTB read hits system.cpu.dtb.read_misses 10280 # DTB read misses -system.cpu.dtb.write_accesses 404071 # DTB write accesses +system.cpu.dtb.write_accesses 404069 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6521933 # DTB write hits +system.cpu.dtb.write_hits 6513710 # DTB write hits system.cpu.dtb.write_misses 1145 # DTB write misses -system.cpu.idle_fraction 0.982991 # Percentage of idle cycles +system.cpu.idle_fraction 0.982997 # Percentage of idle cycles system.cpu.itb.accesses 3281310 # ITB accesses system.cpu.itb.acv 184 # ITB acv system.cpu.itb.hits 3276320 # ITB hits system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 193942 # number of callpals executed +system.cpu.kern.callpal 193842 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4207 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 176844 91.18% 93.39% # number of callpals executed +system.cpu.kern.callpal_swpipl 176751 91.18% 93.38% # number of callpals executed system.cpu.kern.callpal_rdps 6881 3.55% 96.93% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5214 2.69% 99.63% # number of callpals executed +system.cpu.kern.callpal_rti 5211 2.69% 99.63% # number of callpals executed system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 213009 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 212908 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 6282 # number of quiesce instructions executed -system.cpu.kern.ipl_count 184158 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75390 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6207 # number of quiesce instructions executed +system.cpu.kern.ipl_count 184061 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75348 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 245 0.13% 41.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1854 1.01% 42.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106669 57.92% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150141 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74021 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1853 1.01% 42.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106615 57.92% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 150060 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73981 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1854 1.23% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 74021 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3636120154 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3601418096 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_22 1853 1.23% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73981 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3634178761 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3599646819 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 40474 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 159444 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34502140 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.815284 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981841 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_22 159358 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 34332110 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.815273 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981858 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.693932 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1937 -system.cpu.kern.mode_good_user 1757 +system.cpu.kern.ipl_used_31 0.693908 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1938 +system.cpu.kern.mode_good_user 1758 system.cpu.kern.mode_good_idle 180 -system.cpu.kern.mode_switch_kernel 5982 # number of protection mode switches -system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2103 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.393619 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.323805 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_kernel 5978 # number of protection mode switches +system.cpu.kern.mode_switch_user 1758 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2102 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.393983 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324189 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.085592 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 54647278 1.50% 1.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3591234 0.10% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3577881640 98.40% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4208 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.085633 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 54682435 1.50% 1.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3591244 0.10% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3575905080 98.40% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4204 # number of times the context was actually changed system.cpu.kern.syscall 329 # number of syscalls executed system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed @@ -112,10 +112,10 @@ system.cpu.kern.syscall_connect 2 0.61% 97.57% # nu system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017009 # Percentage of non-idle cycles -system.cpu.numCycles 61845001 # number of cpu cycles simulated -system.cpu.num_insts 61839827 # Number of instructions executed -system.cpu.num_refs 16814484 # Number of memory references +system.cpu.not_idle_fraction 0.017003 # Percentage of non-idle cycles +system.cpu.numCycles 61793613 # number of cpu cycles simulated +system.cpu.num_insts 61788439 # Number of instructions executed +system.cpu.num_refs 16800623 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 4741dd710..6204251a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index f7fe15009..bb7f4ca1e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:07:02 -M5 started Sun Oct 8 14:07:07 2006 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Oct 8 2006 21:57:24 +M5 started Sun Oct 8 21:57:28 2006 +M5 executing on zed.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3636120569 because m5_exit instruction encountered +Exiting @ tick 3634179176 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console index 57a610390..27adebb82 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 2 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -19,7 +19,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) CallbackFixup 0 18000, t7=FFFFFC000070C000 Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 @@ -35,7 +35,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) Mount-cache hash table entries: 512 SMP starting up secondaries. Slave CPU 1 console command START @@ -59,9 +59,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb io scheduler cfq registered loop: loaded (max 8 devices) nbd: registered device at major 43 - sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - ns83820: irq bound to CPU 1 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 4f8408501..ff9a06cc7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 779301 # Simulator instruction rate (inst/s) -host_mem_usage 197344 # Number of bytes of host memory used -host_seconds 85.22 # Real time elapsed on the host -host_tick_rate 43826709 # Simulator tick rate (ticks/s) +host_inst_rate 719379 # Simulator instruction rate (inst/s) +host_mem_usage 197268 # Number of bytes of host memory used +host_seconds 92.21 # Real time elapsed on the host +host_tick_rate 40502079 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 66411500 # Number of instructions simulated -sim_seconds 1.867451 # Number of seconds simulated -sim_ticks 3734901822 # Number of ticks simulated +sim_insts 66337257 # Number of instructions simulated +sim_seconds 1.867449 # Number of seconds simulated +sim_ticks 3734898877 # Number of ticks simulated system.cpu0.dtb.accesses 828318 # DTB accesses system.cpu0.dtb.acv 315 # DTB access violations -system.cpu0.dtb.hits 13279471 # DTB hits +system.cpu0.dtb.hits 13264910 # DTB hits system.cpu0.dtb.misses 7094 # DTB misses system.cpu0.dtb.read_accesses 572336 # DTB read accesses system.cpu0.dtb.read_acv 200 # DTB read access violations -system.cpu0.dtb.read_hits 8207004 # DTB read hits +system.cpu0.dtb.read_hits 8201218 # DTB read hits system.cpu0.dtb.read_misses 6394 # DTB read misses system.cpu0.dtb.write_accesses 255982 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 5072467 # DTB write hits +system.cpu0.dtb.write_hits 5063692 # DTB write hits system.cpu0.dtb.write_misses 700 # DTB write misses -system.cpu0.idle_fraction 0.982495 # Percentage of idle cycles +system.cpu0.idle_fraction 0.982517 # Percentage of idle cycles system.cpu0.itb.accesses 1888651 # ITB accesses system.cpu0.itb.acv 166 # ITB acv system.cpu0.itb.hits 1885318 # ITB hits system.cpu0.itb.misses 3333 # ITB misses -system.cpu0.kern.callpal 146866 # number of callpals executed +system.cpu0.kern.callpal 146863 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 507 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal_wripir 506 0.34% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2966 2.02% 2.37% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2962 2.02% 2.36% # number of callpals executed system.cpu0.kern.callpal_tbi 47 0.03% 2.40% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal_swpipl 132441 90.18% 92.58% # number of callpals executed -system.cpu0.kern.callpal_rdps 6235 4.25% 96.83% # number of callpals executed +system.cpu0.kern.callpal_swpipl 132443 90.18% 92.58% # number of callpals executed +system.cpu0.kern.callpal_rdps 6236 4.25% 96.83% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.83% # number of callpals executed system.cpu0.kern.callpal_wrusp 2 0.00% 96.83% # number of callpals executed system.cpu0.kern.callpal_rdusp 8 0.01% 96.84% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal_rti 4201 2.86% 99.70% # number of callpals executed +system.cpu0.kern.callpal_rti 4200 2.86% 99.70% # number of callpals executed system.cpu0.kern.callpal_callsys 317 0.22% 99.91% # number of callpals executed system.cpu0.kern.callpal_imb 128 0.09% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 160336 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 160332 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 6712 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 6637 # number of quiesce instructions executed system.cpu0.kern.ipl_count 139203 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 55746 40.05% 40.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 55744 40.05% 40.05% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 245 0.18% 40.22% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1904 1.37% 41.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 411 0.30% 41.89% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 80897 58.11% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 112531 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 55191 49.05% 49.05% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_30 410 0.29% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 80900 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 112527 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 55189 49.05% 49.05% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 245 0.22% 49.26% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1904 1.69% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 411 0.37% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 54780 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 410 0.36% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 54779 48.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 3734378988 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3696129107 98.98% 98.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3696326531 98.98% 98.98% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 53683 0.00% 98.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 224672 0.01% 98.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 128598 0.00% 98.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 37842928 1.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808395 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_22 224672 0.01% 98.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 128286 0.00% 98.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 37645816 1.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808366 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_0 0.990044 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.677157 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.677120 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1095 system.cpu0.kern.mode_good_user 1095 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6633 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 6628 # number of protection mode switches system.cpu0.kern.mode_switch_user 1095 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.283385 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.165084 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.283569 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.165208 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3730045371 99.93% 99.93% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3730042316 99.93% 99.93% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_user 2718822 0.07% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2967 # number of times the context was actually changed +system.cpu0.kern.swap_context 2963 # number of times the context was actually changed system.cpu0.kern.syscall 179 # number of syscalls executed system.cpu0.kern.syscall_fork 7 3.91% 3.91% # number of syscalls executed system.cpu0.kern.syscall_read 14 7.82% 11.73% # number of syscalls executed @@ -115,84 +115,84 @@ system.cpu0.kern.syscall_connect 2 1.12% 97.77% # nu system.cpu0.kern.syscall_setgid 1 0.56% 98.32% # number of syscalls executed system.cpu0.kern.syscall_getrlimit 1 0.56% 98.88% # number of syscalls executed system.cpu0.kern.syscall_setsid 2 1.12% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.017505 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.017483 # Percentage of non-idle cycles system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 52039310 # Number of instructions executed -system.cpu0.num_refs 13510641 # Number of memory references -system.cpu1.dtb.accesses 477045 # DTB accesses +system.cpu0.num_insts 51973218 # Number of instructions executed +system.cpu0.num_refs 13496062 # Number of memory references +system.cpu1.dtb.accesses 477041 # DTB accesses system.cpu1.dtb.acv 52 # DTB access violations -system.cpu1.dtb.hits 4567143 # DTB hits +system.cpu1.dtb.hits 4561390 # DTB hits system.cpu1.dtb.misses 4359 # DTB misses -system.cpu1.dtb.read_accesses 328553 # DTB read accesses +system.cpu1.dtb.read_accesses 328551 # DTB read accesses system.cpu1.dtb.read_acv 10 # DTB read access violations -system.cpu1.dtb.read_hits 2660612 # DTB read hits +system.cpu1.dtb.read_hits 2657400 # DTB read hits system.cpu1.dtb.read_misses 3911 # DTB read misses -system.cpu1.dtb.write_accesses 148492 # DTB write accesses +system.cpu1.dtb.write_accesses 148490 # DTB write accesses system.cpu1.dtb.write_acv 42 # DTB write access violations -system.cpu1.dtb.write_hits 1906531 # DTB write hits +system.cpu1.dtb.write_hits 1903990 # DTB write hits system.cpu1.dtb.write_misses 448 # DTB write misses -system.cpu1.idle_fraction 0.994923 # Percentage of idle cycles +system.cpu1.idle_fraction 0.994927 # Percentage of idle cycles system.cpu1.itb.accesses 1392687 # ITB accesses system.cpu1.itb.acv 18 # ITB acv system.cpu1.itb.hits 1391015 # ITB hits system.cpu1.itb.misses 1672 # ITB misses -system.cpu1.kern.callpal 74475 # number of callpals executed +system.cpu1.kern.callpal 74370 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 411 0.55% 0.55% # number of callpals executed +system.cpu1.kern.callpal_wripir 410 0.55% 0.55% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.55% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2106 2.83% 3.38% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2102 2.83% 3.38% # number of callpals executed system.cpu1.kern.callpal_tbi 6 0.01% 3.39% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal_swpipl 65169 87.50% 90.91% # number of callpals executed +system.cpu1.kern.callpal_swpipl 65072 87.50% 90.90% # number of callpals executed system.cpu1.kern.callpal_rdps 2603 3.50% 94.40% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 94.40% # number of callpals executed system.cpu1.kern.callpal_wrusp 5 0.01% 94.41% # number of callpals executed system.cpu1.kern.callpal_rdusp 1 0.00% 94.41% # number of callpals executed system.cpu1.kern.callpal_whami 3 0.00% 94.41% # number of callpals executed -system.cpu1.kern.callpal_rti 3893 5.23% 99.64% # number of callpals executed +system.cpu1.kern.callpal_rti 3890 5.23% 99.64% # number of callpals executed system.cpu1.kern.callpal_callsys 214 0.29% 99.93% # number of callpals executed system.cpu1.kern.callpal_imb 52 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 82987 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 82881 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 2512 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 71472 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 27792 38.89% 38.89% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2511 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 71371 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 27750 38.88% 38.88% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1902 2.66% 41.55% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 507 0.71% 42.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 41271 57.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 55838 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 26968 48.30% 48.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1902 3.41% 51.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 507 0.91% 52.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 26461 47.39% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3734901376 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3704875983 99.20% 99.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_count_30 506 0.71% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 41213 57.74% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 55758 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 26928 48.29% 48.29% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1902 3.41% 51.71% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 506 0.91% 52.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 26422 47.39% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3734898431 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3704872588 99.20% 99.20% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 224436 0.01% 99.20% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 162794 0.00% 99.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 29638163 0.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.781257 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.970351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks_30 162482 0.00% 99.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 29638925 0.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.781242 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.970378 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.641152 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1094 +system.cpu1.kern.ipl_used_31 0.641108 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 1093 system.cpu1.kern.mode_good_user 662 -system.cpu1.kern.mode_good_idle 432 -system.cpu1.kern.mode_switch_kernel 2358 # number of protection mode switches +system.cpu1.kern.mode_good_idle 431 +system.cpu1.kern.mode_switch_kernel 2354 # number of protection mode switches system.cpu1.kern.mode_switch_user 662 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2831 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.373953 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.463953 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_idle 2830 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.373931 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.464316 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.152596 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 13374855 0.36% 0.36% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good_idle 0.152297 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 13359666 0.36% 0.36% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 1967356 0.05% 0.41% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3719559163 99.59% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2107 # number of times the context was actually changed +system.cpu1.kern.mode_ticks_idle 3719571407 99.59% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2103 # number of times the context was actually changed system.cpu1.kern.syscall 150 # number of syscalls executed system.cpu1.kern.syscall_fork 1 0.67% 0.67% # number of syscalls executed system.cpu1.kern.syscall_read 16 10.67% 11.33% # number of syscalls executed @@ -216,10 +216,10 @@ system.cpu1.kern.syscall_dup2 1 0.67% 96.00% # nu system.cpu1.kern.syscall_fcntl 2 1.33% 97.33% # number of syscalls executed system.cpu1.kern.syscall_setgid 3 2.00% 99.33% # number of syscalls executed system.cpu1.kern.syscall_getrlimit 1 0.67% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.005077 # Percentage of non-idle cycles +system.cpu1.not_idle_fraction 0.005073 # Percentage of non-idle cycles system.cpu1.numCycles 0 # number of cpu cycles simulated -system.cpu1.num_insts 14372190 # Number of instructions executed -system.cpu1.num_refs 4596339 # Number of memory references +system.cpu1.num_insts 14364039 # Number of instructions executed +system.cpu1.num_refs 4590544 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -234,7 +234,7 @@ system.disk2.dma_write_full_pages 1 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no value # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 64d80c0d2..c8703fde1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 271343: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 3b92a25f9..498a94b6f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:07:02 -M5 started Sun Oct 8 14:10:09 2006 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Oct 8 2006 21:57:24 +M5 started Sun Oct 8 22:00:29 2006 +M5 executing on zed.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3734901822 because m5_exit instruction encountered +Exiting @ tick 3734898877 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console index 1d150a047..5461cc4ab 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console @@ -3,7 +3,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855718, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 1 processor(s) KSP: 0x20043FE8 PTBR 0x20 @@ -16,7 +16,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 k_argc = 0 jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #7 SMP Tue Aug 15 14:40:31 EDT 2006 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM Major Options: SMP LEGACY_START VERBOSE_MCHECK Command line: root=/dev/hda1 console=ttyS0 @@ -32,7 +32,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3316k kernel code, 8952k reserved, 983k data, 224k init) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) Mount-cache hash table entries: 512 SMP mode deactivated. Brought up 1 CPUs @@ -54,9 +54,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 io scheduler cfq registered loop: loaded (max 8 devices) nbd: registered device at major 43 - sinic.c: M5 Simple Integrated NIC driver ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - ns83820: irq bound to CPU 0 eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 8b1a2f192..ba645e5c7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 778282 # Simulator instruction rate (inst/s) -host_mem_usage 196900 # Number of bytes of host memory used -host_seconds 79.42 # Real time elapsed on the host -host_tick_rate 45984556 # Simulator tick rate (ticks/s) +host_inst_rate 740935 # Simulator instruction rate (inst/s) +host_mem_usage 196820 # Number of bytes of host memory used +host_seconds 83.36 # Real time elapsed on the host +host_tick_rate 43810981 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61806956 # Number of instructions simulated -sim_seconds 1.825933 # Number of seconds simulated -sim_ticks 3651865694 # Number of ticks simulated -system.cpu.dtb.accesses 1304498 # DTB accesses +sim_insts 61760478 # Number of instructions simulated +sim_seconds 1.825937 # Number of seconds simulated +sim_ticks 3651873858 # Number of ticks simulated +system.cpu.dtb.accesses 1304494 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16557993 # DTB hits +system.cpu.dtb.hits 16545335 # DTB hits system.cpu.dtb.misses 11425 # DTB misses -system.cpu.dtb.read_accesses 900427 # DTB read accesses +system.cpu.dtb.read_accesses 900425 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10039007 # DTB read hits +system.cpu.dtb.read_hits 10034117 # DTB read hits system.cpu.dtb.read_misses 10280 # DTB read misses -system.cpu.dtb.write_accesses 404071 # DTB write accesses +system.cpu.dtb.write_accesses 404069 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6518986 # DTB write hits +system.cpu.dtb.write_hits 6511218 # DTB write hits system.cpu.dtb.write_misses 1145 # DTB write misses -system.cpu.idle_fraction 0.978522 # Percentage of idle cycles +system.cpu.idle_fraction 0.978539 # Percentage of idle cycles system.cpu.itb.accesses 3281311 # ITB accesses system.cpu.itb.acv 184 # ITB acv system.cpu.itb.hits 3276321 # ITB hits system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 194059 # number of callpals executed +system.cpu.kern.callpal 193987 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4207 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 176948 91.18% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6887 3.55% 96.93% # number of callpals executed +system.cpu.kern.callpal_swpipl 176881 91.18% 93.38% # number of callpals executed +system.cpu.kern.callpal_rdps 6888 3.55% 96.93% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5221 2.69% 99.63% # number of callpals executed +system.cpu.kern.callpal_rti 5219 2.69% 99.63% # number of callpals executed system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 213133 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 213061 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 6280 # number of quiesce instructions executed -system.cpu.kern.ipl_count 184276 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75422 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6207 # number of quiesce instructions executed +system.cpu.kern.ipl_count 184207 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75390 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 245 0.13% 41.06% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1861 1.01% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106748 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150212 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74053 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 106711 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 150152 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74023 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1861 1.24% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 74053 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3651865248 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3611061665 98.88% 98.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 53683 0.00% 98.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_31 74023 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3651873412 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3611240657 98.89% 98.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 53683 0.00% 98.89% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 219598 0.01% 98.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 40530302 1.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.815147 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981849 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_31 40359474 1.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.815126 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981868 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.693718 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1935 -system.cpu.kern.mode_good_user 1755 +system.cpu.kern.ipl_used_31 0.693677 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1934 +system.cpu.kern.mode_good_user 1754 system.cpu.kern.mode_good_idle 180 -system.cpu.kern.mode_switch_kernel 5988 # number of protection mode switches -system.cpu.kern.mode_switch_user 1755 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5984 # number of protection mode switches +system.cpu.kern.mode_switch_user 1754 # number of protection mode switches system.cpu.kern.mode_switch_idle 2104 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.393013 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.323146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 0.393010 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.323195 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.085551 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 58882589 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 4685612 0.13% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3588297045 98.26% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4208 # number of times the context was actually changed +system.cpu.kern.mode_ticks_kernel 58926919 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4685602 0.13% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3588260889 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4204 # number of times the context was actually changed system.cpu.kern.syscall 329 # number of syscalls executed system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed @@ -112,10 +112,10 @@ system.cpu.kern.syscall_connect 2 0.61% 97.57% # nu system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.021478 # Percentage of non-idle cycles +system.cpu.not_idle_fraction 0.021461 # Percentage of non-idle cycles system.cpu.numCycles 0 # number of cpu cycles simulated -system.cpu.num_insts 61806956 # Number of instructions executed -system.cpu.num_refs 16806539 # Number of memory references +system.cpu.num_insts 61760478 # Number of instructions executed +system.cpu.num_refs 16793874 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -130,9 +130,9 @@ system.disk2.dma_write_full_pages 1 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 4741dd710..6204251a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 8c667881d..b54e58e73 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:07:02 -M5 started Sun Oct 8 14:08:49 2006 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Oct 8 2006 21:57:24 +M5 started Sun Oct 8 21:59:05 2006 +M5 executing on zed.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3651865694 because m5_exit instruction encountered +Exiting @ tick 3651873858 because m5_exit instruction encountered -- cgit v1.2.3 From 6c7ab02682aba37c173962ec907b97483625d18b Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 00:26:10 -0400 Subject: Update the Memtester, commit a config file/test for it. src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter. For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description --HG-- extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482 --- tests/configs/memtest.py | 88 ++++++++++++++++++++++++++++++++++++++++++ tests/quick/50.memtest/test.py | 28 ++++++++++++++ 2 files changed, 116 insertions(+) create mode 100644 tests/configs/memtest.py create mode 100644 tests/quick/50.memtest/test.py (limited to 'tests') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py new file mode 100644 index 000000000..cfcefbcb9 --- /dev/null +++ b/tests/configs/memtest.py @@ -0,0 +1,88 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 1 +cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, funcmem = PhysicalMemory(), + physmem = PhysicalMemory(), membus = Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.l1c = L1(size = '32kB', assoc = 4) + cpu.l1c.cpu_side = cpu.test + cpu.l1c.mem_side = system.toL2Bus.port + system.funcmem.port = cpu.functional + + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'timing' +#root.trace.flags="InstExec" +root.trace.flags="Bus" diff --git a/tests/quick/50.memtest/test.py b/tests/quick/50.memtest/test.py new file mode 100644 index 000000000..e894b8fb8 --- /dev/null +++ b/tests/quick/50.memtest/test.py @@ -0,0 +1,28 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + -- cgit v1.2.3 From b9fb4d4870dd45c552fd4cd5e531e9626754f19f Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 17:13:50 -0400 Subject: Make memtest work with 8 memtesters src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system --HG-- extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca --- tests/configs/memtest.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index cfcefbcb9..c5cd0246d 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -51,7 +51,8 @@ class L2(BaseCache): tgts_per_mshr = 16 write_buffers = 8 -nb_cores = 1 +#MAX CORES IS 8 with the fals sharing method +nb_cores = 8 cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] # system simulated @@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port +which_port = 0 # add L1 caches for cpu in cpus: cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.port - system.funcmem.port = cpu.functional + if which_port == 0: + system.funcmem.port = cpu.functional + which_port = 1 + else: + system.funcmem.functional = cpu.functional # connect memory to membus -- cgit v1.2.3 From 094c6de663c1203d3bc64f8d973daba1690e2d33 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 17:25:43 -0400 Subject: Multiprogrammed workload, need to generate ref's for it yet. But Nate wanted the config. Not sure on the naming convention for tests. --HG-- extra : convert_revision : 052c2fc95dc7e2bbd78d4a177600d7ec2a530a4c --- tests/quick/00.hello.mp/test.py | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 tests/quick/00.hello.mp/test.py (limited to 'tests') diff --git a/tests/quick/00.hello.mp/test.py b/tests/quick/00.hello.mp/test.py new file mode 100644 index 000000000..91fbfb7ed --- /dev/null +++ b/tests/quick/00.hello.mp/test.py @@ -0,0 +1,44 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +# workload +benchmarks = [ + "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'", + "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'", + "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'", + "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'", + ] + +for i, cpu in zip(range(len(cpus)), root.system.cpu): + p = LiveProcess() + p.executable = benchmarks[i*2] + p.cmd = benchmarks[(i*2)+1] + root.system.cpu[i].workload = p + root.system.cpu[i].max_insts_all_threads = 10000000 +#root.system.cpu.workload = LiveProcess(cmd = 'hello', + # executable = binpath('hello')) -- cgit v1.2.3 From 727dea78c4b603a63d6c8bee10d317cb2905ffd4 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 17:31:58 -0400 Subject: Update configs for cpu_id tests/configs/o3-timing-mp.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: Update config for cpu_id --HG-- extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac --- tests/configs/o3-timing-mp.py | 4 ++-- tests/configs/simple-atomic-mp.py | 4 ++-- tests/configs/simple-timing-mp.py | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 881c23156..55af8be0d 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -54,7 +54,7 @@ class L2(BaseCache): write_buffers = 8 nb_cores = 4 -cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ] +cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, physmem = PhysicalMemory(), membus = @@ -86,5 +86,5 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -root.trace.flags="Bus Cache" +#root.trace.flags="Bus Cache" #root.trace.flags = "BusAddrRanges" diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index cc1a36dda..eaa6ec66e 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -52,10 +52,10 @@ class L2(BaseCache): write_buffers = 8 nb_cores = 4 -cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] +cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus = Bus()) # l2cache & bus diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 9fc5f3874..8f9ab0dde 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -52,7 +52,7 @@ class L2(BaseCache): write_buffers = 8 nb_cores = 4 -cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ] +cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, physmem = PhysicalMemory(), membus = -- cgit v1.2.3 From 5448517da4cd13e3c8438850f04367d9614d686b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 9 Oct 2006 19:55:49 -0400 Subject: updated reference output --HG-- extra : convert_revision : daf11630290c7a84d63bf37cafa44210861c4bf2 --- .../ref/mips/linux/simple-atomic/config.ini | 2 ++ .../ref/mips/linux/simple-atomic/config.out | 2 ++ .../ref/mips/linux/simple-atomic/m5stats.txt | 8 ++--- .../00.hello/ref/mips/linux/simple-atomic/stdout | 6 ++-- .../ref/mips/linux/simple-timing/config.ini | 4 +++ .../ref/mips/linux/simple-timing/config.out | 4 +++ .../ref/mips/linux/simple-timing/m5stats.txt | 36 ++++++++++------------ .../00.hello/ref/mips/linux/simple-timing/stdout | 6 ++-- 8 files changed, 39 insertions(+), 29 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index fa3ccdf1c..59cadaa12 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -91,6 +91,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 6ab9c098e..064f467da 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index f358a8e52..3b2a2730b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2733 # Simulator instruction rate (inst/s) -host_mem_usage 147536 # Number of bytes of host memory used -host_seconds 2.07 # Real time elapsed on the host -host_tick_rate 2732 # Simulator tick rate (ticks/s) +host_inst_rate 52255 # Simulator instruction rate (inst/s) +host_mem_usage 148024 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 52038 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 4056e38ec..600b178b3 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:15:37 -M5 started Sun Oct 8 14:15:41 2006 +M5 compiled Oct 9 2006 19:28:25 +M5 started Mon Oct 9 19:28:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index af7a1c895..8e1bb0388 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -194,6 +194,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -214,6 +216,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index ead34bf39..d683d2355 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -95,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index ef08c56cd..ab86ba509 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 116093 # Simulator instruction rate (inst/s) -host_mem_usage 158992 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 174583 # Simulator tick rate (ticks/s) +host_inst_rate 68704 # Simulator instruction rate (inst/s) +host_mem_usage 166092 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 103651 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 2.993399 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits system.cpu.icache.overall_miss_latency 907 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses @@ -153,41 +153,39 @@ system.cpu.l2cache.ReadReq_misses 433 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReq_accesses 1 # number of WriteReq accesses(hits+misses) -system.cpu.l2cache.WriteReq_hits 1 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006928 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004619 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.993119 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.993119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.993119 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.993119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -204,7 +202,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 97b24e1ad..4acd2a2e5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:15:37 -M5 started Sun Oct 8 14:15:43 2006 +M5 compiled Oct 9 2006 19:28:25 +M5 started Mon Oct 9 19:28:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Exiting @ tick 8579 because target called exit() -- cgit v1.2.3 From cc78d86661dfccaca2f144d5bdcc75761bf52521 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Tue, 10 Oct 2006 01:32:18 -0400 Subject: Fix several bugs pertaining to upgrades/mem leaks. src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase --HG-- extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688 --- tests/configs/memtest.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index c5cd0246d..17992976c 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -36,7 +36,7 @@ from m5.objects import * class L1(BaseCache): latency = 1 block_size = 64 - mshrs = 4 + mshrs = 12 tgts_per_mshr = 8 protocol = CoherenceProtocol(protocol='moesi') @@ -46,14 +46,14 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = 10 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] +cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), @@ -61,7 +61,7 @@ system = System(cpu = cpus, funcmem = PhysicalMemory(), # l2cache & bus system.toL2Bus = Bus() -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus @@ -90,5 +90,4 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="InstExec" -root.trace.flags="Bus" +root.trace.flags="Cache" -- cgit v1.2.3 From f9284b111158275c5a0ef5043f5b8845dd729261 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 10 Oct 2006 11:04:05 -0400 Subject: Updates refs. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: Update refs. --HG-- extra : convert_revision : 5341341507ddbe1211992e5f72013d7be0000bae --- .../00.hello/ref/alpha/linux/o3-timing/config.ini | 4 + .../00.hello/ref/alpha/linux/o3-timing/config.out | 4 + .../ref/alpha/linux/simple-atomic/config.ini | 2 + .../ref/alpha/linux/simple-atomic/config.out | 2 + .../ref/alpha/linux/simple-timing/config.ini | 4 + .../ref/alpha/linux/simple-timing/config.out | 4 + .../ref/alpha/linux/simple-timing/m5stats.txt | 10 +- .../00.hello/ref/alpha/linux/simple-timing/stdout | 4 +- .../00.hello/ref/alpha/tru64/o3-timing/config.ini | 4 + .../00.hello/ref/alpha/tru64/o3-timing/config.out | 4 + .../ref/alpha/tru64/simple-atomic/config.ini | 2 + .../ref/alpha/tru64/simple-atomic/config.out | 2 + .../ref/alpha/tru64/simple-timing/config.ini | 4 + .../ref/alpha/tru64/simple-timing/config.out | 4 + .../ref/alpha/tru64/simple-timing/m5stats.txt | 10 +- .../00.hello/ref/alpha/tru64/simple-timing/stdout | 4 +- .../ref/alpha/linux/o3-timing/config.ini | 4 + .../ref/alpha/linux/o3-timing/config.out | 4 + .../ref/alpha/linux/o3-timing/m5stats.txt | 530 ++++++++++----------- .../ref/alpha/linux/o3-timing/stdout | 6 +- .../linux/tsunami-simple-atomic-dual/config.ini | 4 + .../linux/tsunami-simple-atomic-dual/config.out | 4 + .../alpha/linux/tsunami-simple-atomic/config.ini | 4 + .../alpha/linux/tsunami-simple-atomic/config.out | 4 + .../linux/tsunami-simple-timing-dual/config.ini | 4 + .../linux/tsunami-simple-timing-dual/config.out | 4 + .../linux/tsunami-simple-timing-dual/m5stats.txt | 14 +- .../alpha/linux/tsunami-simple-timing-dual/stderr | 6 +- .../alpha/linux/tsunami-simple-timing-dual/stdout | 6 +- .../alpha/linux/tsunami-simple-timing/config.ini | 4 + .../alpha/linux/tsunami-simple-timing/config.out | 4 + .../alpha/linux/tsunami-simple-timing/m5stats.txt | 10 +- .../ref/alpha/linux/tsunami-simple-timing/stderr | 4 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 6 +- 34 files changed, 385 insertions(+), 305 deletions(-) (limited to 'tests') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 903794729..86e688c3d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -385,6 +385,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -405,6 +407,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 2a9a97255..1b8e6d980 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -361,6 +363,8 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [trace] flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 7340cc079..b8aba735a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -91,6 +91,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 73f91ff61..71a43d484 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 7b517abc8..f8e1f1bb0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -194,6 +194,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -214,6 +216,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 5c4c7fb14..2ab7c0150 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -95,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 2ee3181d8..6914938e5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 292635 # Simulator instruction rate (inst/s) -host_mem_usage 159688 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 422303 # Simulator tick rate (ticks/s) +host_inst_rate 152920 # Simulator instruction rate (inst/s) +host_mem_usage 166272 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 221766 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -206,7 +206,7 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 8316 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index be8eccb38..423c0b115 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:50 2006 +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:04 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Exiting @ tick 8316 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 45904ca08..e15dd47b7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -385,6 +385,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -405,6 +407,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index c5cec4f22..a57dbacf3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -361,6 +363,8 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [trace] flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index f248945b1..60783267b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -91,6 +91,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index 58ae0d9df..c8733b8f7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 5616cf909..f32654f76 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -194,6 +194,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -214,6 +216,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index c76e14e2c..c45e587d9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -95,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 39ef8ead8..27b01a108 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 69262 # Simulator instruction rate (inst/s) -host_mem_usage 159156 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 100319 # Simulator tick rate (ticks/s) +host_inst_rate 120829 # Simulator instruction rate (inst/s) +host_mem_usage 165792 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 168699 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -205,7 +205,7 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 3777 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 27e317357..1beab6f4b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:54 2006 +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:11 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5b6a4c7ff..9dad57e13 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -385,6 +385,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload0] @@ -420,6 +422,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index bfdd7bcde..bb55a2b69 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload0] type=LiveProcess @@ -376,6 +378,8 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [trace] flags= diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 9871af3ab..e5fad9159 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,29 +1,29 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 642 # Number of BTB hits -global.BPredUnit.BTBLookups 3598 # Number of BTB lookups +global.BPredUnit.BTBHits 640 # Number of BTB hits +global.BPredUnit.BTBLookups 3595 # Number of BTB lookups global.BPredUnit.RASInCorrect 99 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 1081 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2449 # Number of conditional branches predicted -global.BPredUnit.lookups 4173 # Number of BP lookups -global.BPredUnit.usedRAS 551 # Number of times the RAS was used to get a target. -host_inst_rate 48339 # Simulator instruction rate (inst/s) -host_mem_usage 161300 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 36232 # Simulator tick rate (ticks/s) +global.BPredUnit.condPredicted 2447 # Number of conditional branches predicted +global.BPredUnit.lookups 4169 # Number of BP lookups +global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. +host_inst_rate 8624 # Simulator instruction rate (inst/s) +host_mem_usage 167824 # Number of bytes of host memory used +host_seconds 1.30 # Real time elapsed on the host +host_tick_rate 6469 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. memdepunit.memDep.insertedLoads 1868 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1109 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1106 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8441 # Number of ticks simulated +sim_ticks 8439 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed @@ -32,17 +32,17 @@ system.cpu.commit.COM:bw_limited 0 # nu system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8393 +system.cpu.commit.COM:committed_per_cycle.samples 8391 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3957 4714.64% - 1 1909 2274.51% - 2 919 1094.96% - 3 516 614.80% - 4 375 446.80% - 5 235 280.00% - 6 189 225.19% - 7 167 198.98% - 8 126 150.13% + 0 3954 4712.19% + 1 1909 2275.06% + 2 920 1096.41% + 3 516 614.94% + 4 376 448.10% + 5 235 280.06% + 6 188 224.05% + 7 167 199.02% + 8 126 150.16% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -64,35 +64,35 @@ system.cpu.commit.COM:swp_count_1 0 # Nu system.cpu.commit.branchMispredicts 832 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7525 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7510 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.501156 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.500889 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.750511 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.076923 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 3.076923 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.231156 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.231156 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2682 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 720 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 720 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.080247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 234 # number of ReadReq misses +system.cpu.cpi_0 1.500800 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.500533 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750333 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.077253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 3.077253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.232323 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.232323 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2678 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 717 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 717 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.080041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 233 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 233 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits_0 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 444 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 444 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency 442 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 442 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 2.762376 # average WriteReq miss latency @@ -117,85 +117,85 @@ system.cpu.dcache.WriteReq_mshr_misses 144 # nu system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.670554 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.692982 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4540 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4535 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.899441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 2.899254 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 2.899254 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3999 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1557 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 1557 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1554 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 1554 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.118282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.118192 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.118192 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 537 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 536 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_0 194 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 741 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 739 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075551 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075551 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.075413 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075413 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 343 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 342 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 342 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4540 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4535 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 2.899254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 2.899254 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4003 # number of overall hits -system.cpu.dcache.overall_hits_0 4003 # number of overall hits +system.cpu.dcache.overall_hits 3999 # number of overall hits +system.cpu.dcache.overall_hits_0 3999 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 1557 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 1557 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1554 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 1554 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.118282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.118192 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.118192 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 537 # number of overall misses -system.cpu.dcache.overall_misses_0 537 # number of overall misses +system.cpu.dcache.overall_misses 536 # number of overall misses +system.cpu.dcache.overall_misses_0 536 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_0 194 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 741 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 739 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 343 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate 0.075413 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075413 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 342 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 342 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,82 +215,82 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 343 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 226.419332 # Cycle average of tags in use -system.cpu.dcache.total_refs 4003 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 226.387441 # Cycle average of tags in use +system.cpu.dcache.total_refs 3999 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1682 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 270 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 368 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22713 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 9663 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3758 # Number of cycles decode is running +system.cpu.decode.DECODE:BlockedCycles 1691 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 271 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22675 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9659 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3750 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 233 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 106 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4173 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2872 # Number of cache lines fetched -system.cpu.fetch.Cycles 6967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 203 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25244 # Number of instructions fetch has processed +system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4169 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2866 # Number of cache lines fetched +system.cpu.fetch.Cycles 6955 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 25228 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1143 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.494314 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.990287 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.493957 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1190 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.989100 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 8442 +system.cpu.fetch.rateDist.samples 8440 system.cpu.fetch.rateDist.min_value 0 - 0 4348 5150.44% - 1 274 324.57% - 2 232 274.82% - 3 248 293.77% - 4 311 368.40% - 5 277 328.12% - 6 296 350.63% - 7 291 344.71% - 8 2165 2564.56% + 0 4352 5156.40% + 1 273 323.46% + 2 228 270.14% + 3 247 292.65% + 4 313 370.85% + 5 277 328.20% + 6 294 348.34% + 7 291 344.79% + 8 2165 2565.17% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 2866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2866 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency_0 2.982343 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.995153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 2243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2243 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency_0 1858 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.216922 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.216922 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.217376 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.217376 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits_0 4 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency_0 1235 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.215529 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215529 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.215980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215980 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.633279 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.623586 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2866 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_0 2.982343 # average overall miss latency @@ -298,14 +298,14 @@ system.cpu.icache.demand_avg_miss_latency_1 # system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2249 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2249 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2243 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2243 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_0 1858 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.216922 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.216922 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.217376 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.217376 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses system.cpu.icache.demand_misses 623 # number of demand (read+write) misses system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses @@ -316,8 +316,8 @@ system.cpu.icache.demand_mshr_hits_1 0 # nu system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_0 1235 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.215529 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.215529 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.215980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.215980 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses @@ -327,8 +327,8 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2866 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_0 2.982343 # average overall miss latency @@ -339,15 +339,15 @@ system.cpu.icache.overall_avg_mshr_miss_latency_1 system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2249 # number of overall hits -system.cpu.icache.overall_hits_0 2249 # number of overall hits +system.cpu.icache.overall_hits 2243 # number of overall hits +system.cpu.icache.overall_hits_0 2243 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles system.cpu.icache.overall_miss_latency_0 1858 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.216922 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.216922 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.217376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.217376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 no value # miss rate for overall accesses system.cpu.icache.overall_misses 623 # number of overall misses system.cpu.icache.overall_misses_0 623 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses @@ -357,8 +357,8 @@ system.cpu.icache.overall_mshr_hits_1 0 # nu system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_0 1235 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.215529 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.215529 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.215980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.215980 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses @@ -385,8 +385,8 @@ system.cpu.icache.sampled_refs 619 # Sa system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 332.429874 # Cycle average of tags in use -system.cpu.icache.total_refs 2249 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 332.363626 # Cycle average of tags in use +system.cpu.icache.total_refs 2243 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks @@ -397,24 +397,24 @@ system.cpu.iew.EXEC:branches_1 1158 # Nu system.cpu.iew.EXEC:nop 65 # number of nop insts executed system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.814854 # Inst execution rate -system.cpu.iew.EXEC:refs 4932 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2474 # number of memory reference insts executed +system.cpu.iew.EXEC:rate 1.813863 # Inst execution rate +system.cpu.iew.EXEC:refs 4922 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2464 # number of memory reference insts executed system.cpu.iew.EXEC:refs_1 2458 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1873 # Number of stores executed -system.cpu.iew.EXEC:stores_0 937 # Number of stores executed +system.cpu.iew.EXEC:stores 1868 # Number of stores executed +system.cpu.iew.EXEC:stores_0 932 # Number of stores executed system.cpu.iew.EXEC:stores_1 936 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10005 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5007 # num instructions consuming a value +system.cpu.iew.WB:consumers 10001 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5003 # num instructions consuming a value system.cpu.iew.WB:consumers_1 4998 # num instructions consuming a value -system.cpu.iew.WB:count 14809 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7412 # cumulative count of insts written-back +system.cpu.iew.WB:count 14799 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7402 # cumulative count of insts written-back system.cpu.iew.WB:count_1 7397 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.777111 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776113 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.777122 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776134 # average fanout of values written-back system.cpu.iew.WB:fanout_1 0.778111 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ @@ -422,27 +422,27 @@ system.cpu.iew.WB:penalized_1 0 # nu system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7775 # num instructions producing a value -system.cpu.iew.WB:producers_0 3886 # num instructions producing a value +system.cpu.iew.WB:producers 7772 # num instructions producing a value +system.cpu.iew.WB:producers_0 3883 # num instructions producing a value system.cpu.iew.WB:producers_1 3889 # num instructions producing a value -system.cpu.iew.WB:rate 1.754205 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.877991 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.876214 # insts written-back per cycle -system.cpu.iew.WB:sent 14942 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7477 # cumulative count of insts sent to commit +system.cpu.iew.WB:rate 1.753436 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.877014 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.876422 # insts written-back per cycle +system.cpu.iew.WB:sent 14932 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7467 # cumulative count of insts sent to commit system.cpu.iew.WB:sent_1 7465 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute +system.cpu.iew.branchMispredicts 926 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 3701 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 606 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2217 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18807 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3059 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1537 # Number of load instructions executed +system.cpu.iew.iewDispSquashedInsts 604 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2214 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18792 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3054 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1532 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts_1 1522 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 927 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15321 # Number of executed instructions +system.cpu.iew.iewExecSquashedInsts 916 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15309 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -457,7 +457,7 @@ system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Nu system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 889 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 297 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedStores 294 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores @@ -470,14 +470,14 @@ system.cpu.iew.lsq.thread.1.squashedLoads 854 # N system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 161 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.666153 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.666272 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.332425 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8158 # Type of FU issued +system.cpu.iew.predictedTakenIncorrect 162 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.666311 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.666430 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332741 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8135 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5514 67.59% # Type of FU issued + IntAlu 5505 67.67% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -486,8 +486,8 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1662 20.37% # Type of FU issued - MemWrite 977 11.98% # Type of FU issued + MemRead 1656 20.36% # Type of FU issued + MemWrite 969 11.91% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist @@ -508,10 +508,10 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16248 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16225 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 10995 67.67% # Type of FU issued + IntAlu 10986 67.71% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -520,17 +520,17 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3302 20.32% # Type of FU issued - MemWrite 1941 11.95% # Type of FU issued + MemRead 3296 20.31% # Type of FU issued + MemWrite 1933 11.91% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt_0 103 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011140 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.006339 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004801 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.011156 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.006348 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004807 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 10 5.52% # attempts to use FU when none available @@ -548,61 +548,61 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 8442 +system.cpu.iq.ISSUE:issued_per_cycle.samples 8440 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2688 3184.08% - 1 1455 1723.53% - 2 1431 1695.10% - 3 1111 1316.04% - 4 762 902.63% - 5 581 688.23% - 6 288 341.15% - 7 91 107.79% - 8 35 41.46% + 0 2689 3186.02% + 1 1457 1726.30% + 2 1432 1696.68% + 3 1110 1315.17% + 4 757 896.92% + 5 583 690.76% + 6 287 340.05% + 7 91 107.82% + 8 34 40.28% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.924662 # Inst issue rate -system.cpu.iq.iqInstsAdded 18702 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16248 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.922393 # Inst issue rate +system.cpu.iq.iqInstsAdded 18687 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16225 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 6645 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.059561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059561 # average ReadReq miss latency +system.cpu.iq.iqSquashedOperandsExamined 4127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 961 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 961 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.059623 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059623 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1971 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 1971 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.994802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 957 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 957 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 957 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 957 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994802 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994802 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 957 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 957 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005225 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_miss_latency 1969 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 1969 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994797 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.994797 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 956 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 956 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994797 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994797 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 956 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 956 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005230 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 961 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 961 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.059561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 2.059623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 2.059623 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency @@ -610,37 +610,37 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency_1 system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 5 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1971 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 1971 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1969 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 1969 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.994802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.994797 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.994797 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 957 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 957 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 956 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 956 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994802 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.994802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.994797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.994797 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 957 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 961 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 961 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.059561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 2.059623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 2.059623 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency @@ -651,26 +651,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 system.cpu.l2cache.overall_hits 5 # number of overall hits system.cpu.l2cache.overall_hits_0 5 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1971 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 1971 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1969 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 1969 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.994802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.994797 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.994797 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 957 # number of overall misses -system.cpu.l2cache.overall_misses_0 957 # number of overall misses +system.cpu.l2cache.overall_misses 956 # number of overall misses +system.cpu.l2cache.overall_misses_0 956 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 957 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 956 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 956 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994802 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.994802 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.994797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.994797 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 957 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -690,31 +690,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 956 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 558.911632 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 558.812441 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 8442 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 338 # Number of cycles rename is blocking +system.cpu.numCycles 8440 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 9965 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26913 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21123 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15786 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.RENAME:IdleCycles 9958 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 698 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26874 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21097 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15772 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3566 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 763 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7684 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7670 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 572 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1900 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 1906 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 41cca6f14..2b27a0049 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 20:54:51 -M5 started Sun Oct 8 20:55:24 2006 +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:16 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Exiting @ tick 8441 because target called exit() +Exiting @ tick 8439 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 401611d58..c45637b94 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -178,12 +178,16 @@ cpu=system.cpu0 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.membus] type=Bus bus_id=1 +clock=2 +width=64 port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port [system.physmem] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 1d4d50845..45cbbec9b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -29,6 +29,8 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 +clock=2 +width=64 [system.bridge] type=Bridge @@ -491,6 +493,8 @@ disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 [trace] flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index bdd7566bc..11b108837 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -147,12 +147,16 @@ cpu=system.cpu [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.membus] type=Bus bus_id=1 +clock=2 +width=64 port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index bc2f45a5e..e5c6e96f8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -29,6 +29,8 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 +clock=2 +width=64 [system.bridge] type=Bridge @@ -463,6 +465,8 @@ disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 [trace] flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 8f75c9525..9976e053a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -174,12 +174,16 @@ cpu=system.cpu0 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.membus] type=Bus bus_id=1 +clock=2 +width=64 port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port [system.physmem] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 9e0948f1e..9e4bfb566 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -29,6 +29,8 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 +clock=2 +width=64 [system.bridge] type=Bridge @@ -491,6 +493,8 @@ disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 [trace] flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index ff9a06cc7..3f540d0ea 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 719379 # Simulator instruction rate (inst/s) -host_mem_usage 197268 # Number of bytes of host memory used -host_seconds 92.21 # Real time elapsed on the host -host_tick_rate 40502079 # Simulator tick rate (ticks/s) +host_inst_rate 255147 # Simulator instruction rate (inst/s) +host_mem_usage 198260 # Number of bytes of host memory used +host_seconds 260.00 # Real time elapsed on the host +host_tick_rate 14365182 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 66337257 # Number of instructions simulated sim_seconds 1.867449 # Number of seconds simulated @@ -116,7 +116,7 @@ system.cpu0.kern.syscall_setgid 1 0.56% 98.32% # nu system.cpu0.kern.syscall_getrlimit 1 0.56% 98.88% # number of syscalls executed system.cpu0.kern.syscall_setsid 2 1.12% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.017483 # Percentage of non-idle cycles -system.cpu0.numCycles 0 # number of cpu cycles simulated +system.cpu0.numCycles 3734379018 # number of cpu cycles simulated system.cpu0.num_insts 51973218 # Number of instructions executed system.cpu0.num_refs 13496062 # Number of memory references system.cpu1.dtb.accesses 477041 # DTB accesses @@ -217,7 +217,7 @@ system.cpu1.kern.syscall_fcntl 2 1.33% 97.33% # nu system.cpu1.kern.syscall_setgid 3 2.00% 99.33% # number of syscalls executed system.cpu1.kern.syscall_getrlimit 1 0.67% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.005073 # Percentage of non-idle cycles -system.cpu1.numCycles 0 # number of cpu cycles simulated +system.cpu1.numCycles 3734898877 # number of cpu cycles simulated system.cpu1.num_insts 14364039 # Number of instructions executed system.cpu1.num_refs 4590544 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -234,7 +234,7 @@ system.disk2.dma_write_full_pages 1 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index c8703fde1..64d80c0d2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: 271343: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 498a94b6f..0e22ad636 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 21:57:24 -M5 started Sun Oct 8 22:00:29 2006 -M5 executing on zed.eecs.umich.edu +M5 compiled Oct 10 2006 01:59:16 +M5 started Tue Oct 10 02:09:13 2006 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Exiting @ tick 3734898877 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 21d606051..6514a6af7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -145,12 +145,16 @@ cpu=system.cpu [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.membus] type=Bus bus_id=1 +clock=2 +width=64 port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 73f9edaea..173819299 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -29,6 +29,8 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 +clock=2 +width=64 [system.bridge] type=Bridge @@ -463,6 +465,8 @@ disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 +clock=2 +width=64 [trace] flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index ba645e5c7..c126b03a3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 740935 # Simulator instruction rate (inst/s) -host_mem_usage 196820 # Number of bytes of host memory used -host_seconds 83.36 # Real time elapsed on the host -host_tick_rate 43810981 # Simulator tick rate (ticks/s) +host_inst_rate 244619 # Simulator instruction rate (inst/s) +host_mem_usage 197804 # Number of bytes of host memory used +host_seconds 252.48 # Real time elapsed on the host +host_tick_rate 14464234 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 61760478 # Number of instructions simulated sim_seconds 1.825937 # Number of seconds simulated @@ -113,7 +113,7 @@ system.cpu.kern.syscall_setgid 4 1.22% 98.78% # nu system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.021461 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 3651873858 # number of cpu cycles simulated system.cpu.num_insts 61760478 # Number of instructions executed system.cpu.num_refs 16793874 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 6204251a5..4741dd710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index b54e58e73..2ffd4c8b9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 21:57:24 -M5 started Sun Oct 8 21:59:05 2006 -M5 executing on zed.eecs.umich.edu +M5 compiled Oct 10 2006 01:59:16 +M5 started Tue Oct 10 02:04:59 2006 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Exiting @ tick 3651873858 because m5_exit instruction encountered -- cgit v1.2.3 From 60252f8e63dae98f2ee7b99336f567a99837edd4 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 11 Oct 2006 01:18:20 -0400 Subject: Interesting memtest finally. Get over 500,000 reads on each of 8 testers before memory leak becomes large. tests/configs/memtest.py: Update test to be more interesting --HG-- extra : convert_revision : 4258b798fbeeed2a376f1bfac100a109eb05620e --- tests/configs/memtest.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 17992976c..116e71af6 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -53,14 +53,14 @@ class L2(BaseCache): #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ] +cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(), membus = Bus()) + physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16)) # l2cache & bus -system.toL2Bus = Bus() +system.toL2Bus = Bus(clock="500GHz", width=16) system.l2c = L2(size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port @@ -90,4 +90,6 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -root.trace.flags="Cache" +#root.trace.flags="Cache CachePort Bus" +#root.trace.cycle=3810800 + -- cgit v1.2.3