From 89da836bcf7e6bd6bbc3a9c3b03c6a35f968f5e6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 11 Mar 2007 18:53:40 -0400 Subject: gzip is really a tru64 regression, not linux --HG-- rename : tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini => tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out => tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out rename : tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt rename : tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr rename : tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout rename : tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out rename : tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr rename : tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout rename : tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini => tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out => tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out rename : tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr rename : tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout extra : convert_revision : e38a226137968d0893e325c22489375ce4a691a2 --- .../00.gzip/ref/alpha/linux/o3-timing/config.ini | 419 --------------------- .../00.gzip/ref/alpha/linux/o3-timing/config.out | 405 -------------------- .../00.gzip/ref/alpha/linux/o3-timing/m5stats.txt | 413 -------------------- .../long/00.gzip/ref/alpha/linux/o3-timing/stderr | 2 - .../long/00.gzip/ref/alpha/linux/o3-timing/stdout | 31 -- .../ref/alpha/linux/simple-atomic/config.ini | 113 ------ .../ref/alpha/linux/simple-atomic/config.out | 107 ------ .../ref/alpha/linux/simple-atomic/m5stats.txt | 18 - .../00.gzip/ref/alpha/linux/simple-atomic/stderr | 1 - .../00.gzip/ref/alpha/linux/simple-atomic/stdout | 31 -- .../ref/alpha/linux/simple-timing/config.ini | 236 ------------ .../ref/alpha/linux/simple-timing/config.out | 228 ----------- .../ref/alpha/linux/simple-timing/m5stats.txt | 216 ----------- .../00.gzip/ref/alpha/linux/simple-timing/stderr | 1 - .../00.gzip/ref/alpha/linux/simple-timing/stdout | 31 -- .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 419 +++++++++++++++++++++ .../00.gzip/ref/alpha/tru64/o3-timing/config.out | 405 ++++++++++++++++++++ .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 413 ++++++++++++++++++++ .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 + .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 31 ++ .../ref/alpha/tru64/simple-atomic/config.ini | 113 ++++++ .../ref/alpha/tru64/simple-atomic/config.out | 107 ++++++ .../ref/alpha/tru64/simple-atomic/m5stats.txt | 18 + .../00.gzip/ref/alpha/tru64/simple-atomic/stderr | 1 + .../00.gzip/ref/alpha/tru64/simple-atomic/stdout | 31 ++ .../ref/alpha/tru64/simple-timing/config.ini | 236 ++++++++++++ .../ref/alpha/tru64/simple-timing/config.out | 228 +++++++++++ .../ref/alpha/tru64/simple-timing/m5stats.txt | 216 +++++++++++ .../00.gzip/ref/alpha/tru64/simple-timing/stderr | 1 + .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 31 ++ 30 files changed, 2252 insertions(+), 2252 deletions(-) delete mode 100644 tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini delete mode 100644 tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out delete mode 100644 tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt delete mode 100644 tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr delete mode 100644 tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr delete mode 100644 tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr create mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout (limited to 'tests') diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini deleted file mode 100644 index fa5ac1725..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini +++ /dev/null @@ -1,419 +0,0 @@ -[root] -type=Root -children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 -clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 -system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -responder_set=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing -egid=100 -env= -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -output=cout -pid=100 -ppid=99 -system=system -uid=100 - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -responder_set=false -width=64 -port=system.physmem.port system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=1 -range=0:134217727 -zero=false -port=system.membus.port[0] - diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out deleted file mode 100644 index 8744b6907..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out +++ /dev/null @@ -1,405 +0,0 @@ -[root] -type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout - -[system.physmem] -type=PhysicalMemory -file= -range=[0,134217727] -latency=1 -zero=false - -[system] -type=System -physmem=system.physmem -mem_mode=atomic - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -width=64 -responder_set=false - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -input=cin -output=cout -env= -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing -system=system -uid=100 -euid=100 -gid=100 -egid=100 -pid=100 -ppid=99 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -phase=0 -numThreads=1 -activity=0 -workload=system.cpu.workload -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -width=64 -responder_set=false - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt deleted file mode 100644 index 8303336ed..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,413 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 97621780 # Number of BTB hits -global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups -global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted -global.BPredUnit.lookups 108029652 # Number of BP lookups -global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. -host_inst_rate 64442 # Simulator instruction rate (inst/s) -host_mem_usage 296420 # Number of bytes of host memory used -host_seconds 8776.17 # Real time elapsed on the host -host_tick_rate 192322 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.001688 # Number of seconds simulated -sim_ticks 1687849017 # Number of ticks simulated -system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 701581491 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 480309675 6846.10% - 1 104094392 1483.71% - 2 40244499 573.63% - 3 11990473 170.91% - 4 15113210 215.42% - 5 17360338 247.45% - 6 10367558 147.77% - 7 4968492 70.82% - 8 17132854 244.20% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:loads 115049510 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 154862033 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit -system.cpu.committedInsts 565552443 # Number of Instructions Simulated -system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152421092 # number of overall hits -system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1949244 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 476534 # number of replacements -system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use -system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 337990 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched -system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 755178522 -system.cpu.fetch.rateDist.min_value 0 - 0 512314112 6784.01% - 1 11453310 151.66% - 2 16801464 222.48% - 3 16318450 216.09% - 4 18767749 248.52% - 5 15201778 201.30% - 6 32935567 436.13% - 7 7297838 96.64% - 8 124088254 1643.16% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency -system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 167526954 # number of overall hits -system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1230 # number of overall misses -system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 47 # number of replacements -system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use -system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 92484798 # Number of branches executed -system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate -system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 51400640 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value -system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 394011709 # num instructions producing a value -system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle -system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 496182294 65.92% # Type of FU issued - IntMult 8208 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 33 0.00% # Type of FU issued - FloatCmp 6 0.00% # Type of FU issued - FloatCvt 5 0.00% # Type of FU issued - FloatMult 5 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 204178453 27.13% # Type of FU issued - MemWrite 52346873 6.95% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 2723724 78.58% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 683243 19.71% # attempts to use FU when none available - MemWrite 59353 1.71% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 450030250 5959.26% - 1 91846319 1216.22% - 2 83470092 1105.30% - 3 53962116 714.56% - 4 57175468 757.11% - 5 10089384 133.60% - 6 7448894 98.64% - 7 1047122 13.87% - 8 108877 1.44% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate -system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 793226 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26319 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 934 # number of replacements -system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 907 # number of writebacks -system.cpu.numCycles 755178522 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr deleted file mode 100644 index eb1796ead..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini deleted file mode 100644 index 841e8766f..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini +++ /dev/null @@ -1,113 +0,0 @@ -[root] -type=Root -children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=AtomicSimpleCPU -children=workload -clock=1 -cpu_id=0 -defer_registration=false -function_trace=false -function_trace_start=0 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -phase=0 -progress_interval=0 -simulate_stalls=false -system=system -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic -egid=100 -env= -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -output=cout -pid=100 -ppid=99 -system=system -uid=100 - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -responder_set=false -width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=1 -range=0:134217727 -port=system.membus.port[0] - -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out deleted file mode 100644 index b5a24e5fb..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out +++ /dev/null @@ -1,107 +0,0 @@ -[root] -type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout - -[system.physmem] -type=PhysicalMemory -file= -range=[0,134217727] -latency=1 - -[system] -type=System -physmem=system.physmem -mem_mode=atomic - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -width=64 -responder_set=false - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -input=cin -output=cout -env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic -system=system -uid=100 -euid=100 -gid=100 -egid=100 -pid=100 -ppid=99 - -[system.cpu] -type=AtomicSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -workload=system.cpu.workload -clock=1 -phase=0 -defer_registration=false -width=1 -function_trace=false -function_trace_start=0 -simulate_stalls=false - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt deleted file mode 100644 index b8593d3a3..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 970342 # Simulator instruction rate (inst/s) -host_mem_usage 144620 # Number of bytes of host memory used -host_seconds 620.25 # Real time elapsed on the host -host_tick_rate 970342 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.000602 # Number of seconds simulated -sim_ticks 601856964 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 601856965 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini deleted file mode 100644 index 48a760b08..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini +++ /dev/null @@ -1,236 +0,0 @@ -[root] -type=Root -children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -physmem=system.physmem - -[system.cpu] -type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload -clock=1 -cpu_id=0 -defer_registration=false -function_trace=false -function_trace_start=0 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -phase=0 -progress_interval=0 -system=system -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -responder_set=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing -egid=100 -env= -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -output=cout -pid=100 -ppid=99 -system=system -uid=100 - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -responder_set=false -width=64 -port=system.physmem.port system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=1 -range=0:134217727 -port=system.membus.port[0] - -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out deleted file mode 100644 index eddb9ff53..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out +++ /dev/null @@ -1,228 +0,0 @@ -[root] -type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout - -[system.physmem] -type=PhysicalMemory -file= -range=[0,134217727] -latency=1 - -[system] -type=System -physmem=system.physmem -mem_mode=atomic - -[system.membus] -type=Bus -bus_id=0 -clock=1000 -width=64 -responder_set=false - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -input=cin -output=cout -env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing -system=system -uid=100 -euid=100 -gid=100 -egid=100 -pid=100 -ppid=99 - -[system.cpu] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -workload=system.cpu.workload -clock=1 -phase=0 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -width=64 -responder_set=false - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt deleted file mode 100644 index 5e7441c54..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,216 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 549029 # Simulator instruction rate (inst/s) -host_mem_usage 300652 # Number of bytes of host memory used -host_seconds 1096.22 # Real time elapsed on the host -host_tick_rate 1916109 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.002100 # Number of seconds simulated -sim_ticks 2100480012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses -system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses -system.cpu.dcache.overall_misses 455395 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use -system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325723 # number of writebacks -system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency -system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use -system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26098 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use -system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 883 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2100480012 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini new file mode 100644 index 000000000..fa5ac1725 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -0,0 +1,419 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out new file mode 100644 index 000000000..8744b6907 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -0,0 +1,405 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +input=cin +output=cout +env= +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +phase=0 +numThreads=1 +activity=0 +workload=system.cpu.workload +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt new file mode 100644 index 000000000..8303336ed --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -0,0 +1,413 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 97621780 # Number of BTB hits +global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups +global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted +global.BPredUnit.lookups 108029652 # Number of BP lookups +global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. +host_inst_rate 64442 # Simulator instruction rate (inst/s) +host_mem_usage 296420 # Number of bytes of host memory used +host_seconds 8776.17 # Real time elapsed on the host +host_tick_rate 192322 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 565552443 # Number of instructions simulated +sim_seconds 0.001688 # Number of seconds simulated +sim_ticks 1687849017 # Number of ticks simulated +system.cpu.commit.COM:branches 62547159 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 701581491 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 480309675 6846.10% + 1 104094392 1483.71% + 2 40244499 573.63% + 3 11990473 170.91% + 4 15113210 215.42% + 5 17360338 247.45% + 6 10367558 147.77% + 7 4968492 70.82% + 8 17132854 244.20% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:loads 115049510 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 154862033 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit +system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated +system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 152421092 # number of overall hits +system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1949244 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 476534 # number of replacements +system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use +system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 337990 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched +system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 755178522 +system.cpu.fetch.rateDist.min_value 0 + 0 512314112 6784.01% + 1 11453310 151.66% + 2 16801464 222.48% + 3 16318450 216.09% + 4 18767749 248.52% + 5 15201778 201.30% + 6 32935567 436.13% + 7 7297838 96.64% + 8 124088254 1643.16% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 167526954 # number of overall hits +system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_misses 1230 # number of overall misses +system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 47 # number of replacements +system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use +system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 92484798 # Number of branches executed +system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate +system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 51400640 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value +system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 394011709 # num instructions producing a value +system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle +system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 0 0.00% # Type of FU issued + IntAlu 496182294 65.92% # Type of FU issued + IntMult 8208 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 33 0.00% # Type of FU issued + FloatCmp 6 0.00% # Type of FU issued + FloatCvt 5 0.00% # Type of FU issued + FloatMult 5 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 204178453 27.13% # Type of FU issued + MemWrite 52346873 6.95% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 2723724 78.58% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 683243 19.71% # attempts to use FU when none available + MemWrite 59353 1.71% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 450030250 5959.26% + 1 91846319 1216.22% + 2 83470092 1105.30% + 3 53962116 714.56% + 4 57175468 757.11% + 5 10089384 133.60% + 6 7448894 98.64% + 7 1047122 13.87% + 8 108877 1.44% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate +system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 793226 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26319 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 934 # number of replacements +system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 907 # number of writebacks +system.cpu.numCycles 755178522 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout new file mode 100644 index 000000000..9aaca3eeb --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -0,0 +1,31 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..841e8766f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,113 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out new file mode 100644 index 000000000..b5a24e5fb --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -0,0 +1,107 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +input=cin +output=cout +env= +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt new file mode 100644 index 000000000..b8593d3a3 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 970342 # Simulator instruction rate (inst/s) +host_mem_usage 144620 # Number of bytes of host memory used +host_seconds 620.25 # Real time elapsed on the host +host_tick_rate 970342 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856965 # Number of instructions simulated +sim_seconds 0.000602 # Number of seconds simulated +sim_ticks 601856964 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 601856965 # number of cpu cycles simulated +system.cpu.num_insts 601856965 # Number of instructions executed +system.cpu.num_refs 154862034 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr new file mode 100644 index 000000000..87866a2a5 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr @@ -0,0 +1 @@ +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout new file mode 100644 index 000000000..9aaca3eeb --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -0,0 +1,31 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini new file mode 100644 index 000000000..48a760b08 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -0,0 +1,236 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out new file mode 100644 index 000000000..eddb9ff53 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -0,0 +1,228 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +input=cin +output=cout +env= +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt new file mode 100644 index 000000000..5e7441c54 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -0,0 +1,216 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 549029 # Simulator instruction rate (inst/s) +host_mem_usage 300652 # Number of bytes of host memory used +host_seconds 1096.22 # Real time elapsed on the host +host_tick_rate 1916109 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856965 # Number of instructions simulated +sim_seconds 0.002100 # Number of seconds simulated +sim_ticks 2100480012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 153509968 # number of overall hits +system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_misses 455395 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use +system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 795 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 601856171 # number of overall hits +system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 795 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use +system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 755815 # number of overall hits +system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26098 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 903 # number of replacements +system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use +system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 883 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2100480012 # number of cpu cycles simulated +system.cpu.num_insts 601856965 # Number of instructions executed +system.cpu.num_refs 154862034 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr new file mode 100644 index 000000000..87866a2a5 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -0,0 +1 @@ +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout new file mode 100644 index 000000000..9aaca3eeb --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -0,0 +1,31 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! -- cgit v1.2.3