From 99fb8f81407efa54008ddf443718e492f583b142 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 9 Mar 2015 09:39:09 -0500
Subject: stats: changes to due to recent set of patches

---
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt      |   2 -
 .../ref/alpha/linux/tsunami-o3/stats.txt           |   1 -
 .../alpha/linux/tsunami-switcheroo-full/stats.txt  |   1 -
 .../ref/arm/linux/realview-o3-checker/stats.txt    |   1 -
 .../ref/arm/linux/realview-o3-dual/stats.txt       |   2 -
 .../ref/arm/linux/realview-o3/stats.txt            |   1 -
 .../arm/linux/realview-switcheroo-full/stats.txt   |   1 -
 .../ref/arm/linux/realview-switcheroo-o3/stats.txt |   2 -
 .../ref/arm/linux/realview64-o3-checker/stats.txt  |   1 -
 .../ref/arm/linux/realview64-o3-dual/stats.txt     |   2 -
 .../ref/arm/linux/realview64-o3/stats.txt          |   1 -
 .../arm/linux/realview64-switcheroo-full/stats.txt |   1 -
 .../arm/linux/realview64-switcheroo-o3/stats.txt   |   2 -
 .../ref/x86/linux/pc-o3-timing/stats.txt           |   1 -
 .../ref/x86/linux/pc-switcheroo-full/stats.txt     |   1 -
 .../se/10.mcf/ref/arm/linux/o3-timing/stats.txt    |   1 -
 .../se/10.mcf/ref/x86/linux/o3-timing/stats.txt    |   1 -
 .../se/20.parser/ref/arm/linux/o3-timing/stats.txt |   1 -
 .../se/20.parser/ref/x86/linux/o3-timing/stats.txt |   1 -
 .../se/30.eon/ref/alpha/tru64/o3-timing/stats.txt  |   1 -
 .../se/30.eon/ref/arm/linux/o3-timing/stats.txt    |   1 -
 .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |   1 -
 .../40.perlbmk/ref/arm/linux/o3-timing/stats.txt   |   1 -
 .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt  |   1 -
 .../se/50.vortex/ref/arm/linux/o3-timing/stats.txt |   1 -
 .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt   |   1 -
 .../se/60.bzip2/ref/arm/linux/o3-timing/stats.txt  |   1 -
 .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt   |   1 -
 .../se/70.twolf/ref/arm/linux/o3-timing/stats.txt  |   1 -
 .../se/70.twolf/ref/x86/linux/o3-timing/stats.txt  |   1 -
 .../linux/tsunami-simple-atomic-dual/config.ini    |  21 ++-
 .../alpha/linux/tsunami-simple-atomic/config.ini   |  19 ++-
 .../linux/tsunami-simple-timing-dual/config.ini    |  23 ++-
 .../alpha/linux/tsunami-simple-timing/config.ini   |  21 ++-
 .../linux/realview-simple-atomic-dual/config.ini   |  43 +++--
 .../arm/linux/realview-simple-atomic/config.ini    |  25 ++-
 .../linux/realview-simple-timing-dual/config.ini   |  45 +++--
 .../arm/linux/realview-simple-timing/config.ini    |  27 ++-
 .../linux/realview-switcheroo-atomic/config.ini    |  29 +++-
 .../linux/realview64-simple-atomic-dual/config.ini |  43 +++--
 .../arm/linux/realview64-simple-atomic/config.ini  |  25 ++-
 .../linux/realview64-simple-timing-dual/config.ini |  45 +++--
 .../arm/linux/realview64-simple-timing/config.ini  |  27 ++-
 .../linux/realview64-switcheroo-atomic/config.ini  |  45 +++--
 .../ref/x86/linux/pc-simple-atomic/config.ini      |  27 ++-
 .../ref/x86/linux/pc-simple-timing/config.ini      |  29 ++--
 .../linux/twosys-tsunami-simple-atomic/config.ini  |  32 ++--
 .../ref/alpha/linux/minor-timing/config.ini        |  15 +-
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  |  15 +-
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   |   1 -
 .../ref/alpha/linux/simple-atomic/config.ini       |  10 +-
 .../simple-timing-ruby-MESI_Two_Level/config.ini   |   8 +-
 .../config.ini                                     |   8 +-
 .../simple-timing-ruby-MOESI_CMP_token/config.ini  |   8 +-
 .../simple-timing-ruby-MOESI_hammer/config.ini     |   8 +-
 .../ref/alpha/linux/simple-timing-ruby/config.ini  |   8 +-
 .../ref/alpha/linux/simple-timing/config.ini       |  13 +-
 .../ref/alpha/tru64/minor-timing/config.ini        |  15 +-
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  |  15 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   |   1 -
 .../ref/alpha/tru64/simple-atomic/config.ini       |  10 +-
 .../simple-timing-ruby-MESI_Two_Level/config.ini   |   8 +-
 .../config.ini                                     |   8 +-
 .../simple-timing-ruby-MOESI_CMP_token/config.ini  |   8 +-
 .../simple-timing-ruby-MOESI_hammer/config.ini     |   8 +-
 .../ref/alpha/tru64/simple-timing-ruby/config.ini  |   8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |  18 +-
 .../00.hello/ref/arm/linux/minor-timing/config.ini |  21 ++-
 .../ref/arm/linux/o3-timing-checker/config.ini     |  37 +++--
 .../ref/arm/linux/o3-timing-checker/stats.txt      |   1 -
 .../se/00.hello/ref/arm/linux/o3-timing/config.ini |  52 ++++--
 .../se/00.hello/ref/arm/linux/o3-timing/stats.txt  |   1 -
 .../linux/simple-atomic-dummychecker/config.ini    |  20 ++-
 .../ref/arm/linux/simple-atomic/config.ini         |  17 +-
 .../ref/arm/linux/simple-timing/config.ini         |  25 ++-
 .../00.hello/ref/mips/linux/o3-timing/config.ini   |  21 ++-
 .../se/00.hello/ref/mips/linux/o3-timing/stats.txt |   1 -
 .../ref/mips/linux/simple-atomic/config.ini        |  10 +-
 .../ref/mips/linux/simple-timing-ruby/config.ini   |   8 +-
 .../ref/mips/linux/simple-timing/config.ini        |  18 +-
 .../00.hello/ref/power/linux/o3-timing/config.ini  |  21 ++-
 .../00.hello/ref/power/linux/o3-timing/stats.txt   |   1 -
 .../ref/power/linux/simple-atomic/config.ini       |  10 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |  10 +-
 .../ref/sparc/linux/simple-timing-ruby/config.ini  |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  18 +-
 .../se/00.hello/ref/x86/linux/o3-timing/config.ini |  15 +-
 .../se/00.hello/ref/x86/linux/o3-timing/stats.txt  |   1 -
 .../ref/x86/linux/simple-atomic/config.ini         |   8 +-
 .../ref/x86/linux/simple-timing-ruby/config.ini    |   6 +-
 .../ref/x86/linux/simple-timing/config.ini         |  13 +-
 .../ref/alpha/linux/o3-timing/config.ini           |  23 ++-
 .../ref/alpha/linux/o3-timing/stats.txt            |   3 -
 .../ref/sparc/linux/o3-timing/config.ini           |  21 ++-
 .../ref/sparc/linux/o3-timing/stats.txt            |   1 -
 .../ref/sparc/linux/simple-atomic/config.ini       |  10 +-
 .../ref/sparc/linux/simple-timing/config.ini       |  18 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini        |  17 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt         |   4 -
 .../ref/sparc/linux/simple-atomic-mp/config.ini    |  26 ++-
 .../ref/sparc/linux/simple-timing-mp/config.ini    |  26 ++-
 .../linux/memtest-ruby-MESI_Two_Level/config.ini   | 168 ++++++-------------
 .../memtest-ruby-MOESI_CMP_directory/config.ini    | 168 ++++++-------------
 .../linux/memtest-ruby-MOESI_CMP_token/config.ini  | 168 ++++++-------------
 .../linux/memtest-ruby-MOESI_hammer/config.ini     | 168 ++++++-------------
 .../ref/alpha/linux/memtest-ruby/config.ini        | 168 ++++++-------------
 .../ref/null/none/memtest-filter/config.ini        | 181 ++++++++-------------
 .../se/50.memtest/ref/null/none/memtest/config.ini | 177 ++++++++------------
 .../linux/rubytest-ruby-MESI_Two_Level/config.ini  |   6 +-
 .../rubytest-ruby-MOESI_CMP_directory/config.ini   |   6 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/config.ini |   6 +-
 .../linux/rubytest-ruby-MOESI_hammer/config.ini    |   6 +-
 .../ref/alpha/linux/rubytest-ruby/config.ini       |   6 +-
 .../ref/null/none/tgen-dram-ctrl/config.ini        |   9 +-
 .../ref/null/none/tgen-simple-mem/config.ini       |  16 +-
 115 files changed, 1300 insertions(+), 1199 deletions(-)

(limited to 'tests')

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 24a65d69d..a1e1dce04 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -645,7 +645,6 @@ system.cpu0.commit.op_class_0::IprAccess       817865      1.59%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total         51332073                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events              1893392                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                   165216916                       # The number of ROB reads
 system.cpu0.rob.rob_writes                  117798939                       # The number of ROB writes
 system.cpu0.timesIdled                         506110                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1241,7 +1240,6 @@ system.cpu1.commit.op_class_0::IprAccess       257926      2.99%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total          8615735                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events               304379                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                    23176968                       # The number of ROB reads
 system.cpu1.rob.rob_writes                   20704388                       # The number of ROB writes
 system.cpu1.timesIdled                         112605                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 12a10aeec..7568645aa 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -633,7 +633,6 @@ system.cpu.commit.op_class_0::IprAccess        948942      1.69%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          56123349                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               2085445                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    177593269                       # The number of ROB reads
 system.cpu.rob.rob_writes                   130137832                       # The number of ROB writes
 system.cpu.timesIdled                          572499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 43a4f79aa..ff31246c1 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1317,7 +1317,6 @@ system.cpu2.commit.op_class_0::IprAccess       303954      0.94%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total         32325567                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events               870316                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                    62726939                       # The number of ROB reads
 system.cpu2.rob.rob_writes                   70507401                       # The number of ROB writes
 system.cpu2.timesIdled                         178497                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index b7b8c766f..40f18548e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -964,7 +964,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         137405868                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               1059409                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    375672050                       # The number of ROB reads
 system.cpu.rob.rob_writes                   292972268                       # The number of ROB writes
 system.cpu.timesIdled                          891577                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 3cbfaeabe..aadef3011 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -865,7 +865,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total        120715819                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events              1448193                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                   292184577                       # The number of ROB reads
 system.cpu0.rob.rob_writes                  263546817                       # The number of ROB writes
 system.cpu0.timesIdled                         122559                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -2077,7 +2076,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total         25443224                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events               442982                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                    68115809                       # The number of ROB reads
 system.cpu1.rob.rob_writes                   56808236                       # The number of ROB writes
 system.cpu1.timesIdled                          67589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index e4b623d06..c3d73effc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -825,7 +825,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         137405868                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               1059409                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    375672050                       # The number of ROB reads
 system.cpu.rob.rob_writes                   292972268                       # The number of ROB writes
 system.cpu.timesIdled                          891577                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 2b4d78664..0d34de931 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1725,7 +1725,6 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total         47174544                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events              1230130                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                   112818862                       # The number of ROB reads
 system.cpu2.rob.rob_writes                  112362949                       # The number of ROB writes
 system.cpu2.timesIdled                         279332                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index ec623239f..e32fa2c8d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -851,7 +851,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total         68988407                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events              1718944                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                   167372763                       # The number of ROB reads
 system.cpu0.rob.rob_writes                  163072923                       # The number of ROB writes
 system.cpu0.timesIdled                         393865                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1778,7 +1777,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total         73162446                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events              1807529                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                   173729023                       # The number of ROB reads
 system.cpu1.rob.rob_writes                  171875858                       # The number of ROB writes
 system.cpu1.timesIdled                         390006                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 5a693d4ac..efb9175e6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -975,7 +975,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1005211605                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              11866014                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   2555711925                       # The number of ROB reads
 system.cpu.rob.rob_writes                  2125474325                       # The number of ROB writes
 system.cpu.timesIdled                         8142220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index b1b40f923..8729ed0b6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -848,7 +848,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total        545285068                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events             13335148                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                  1272468420                       # The number of ROB reads
 system.cpu0.rob.rob_writes                 1194722923                       # The number of ROB writes
 system.cpu0.timesIdled                         998377                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -2097,7 +2096,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total        500362777                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events             12356672                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                  1162834468                       # The number of ROB reads
 system.cpu1.rob.rob_writes                 1096743807                       # The number of ROB writes
 system.cpu1.timesIdled                         924876                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 6f7d21c4e..e43ffb8c7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -836,7 +836,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1005211605                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              11866014                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   2555711925                       # The number of ROB reads
 system.cpu.rob.rob_writes                  2125474325                       # The number of ROB writes
 system.cpu.timesIdled                         8142220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index 8e7b17b1a..d441549f2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1816,7 +1816,6 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total        387615464                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events             16778864                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                   862595097                       # The number of ROB reads
 system.cpu2.rob.rob_writes                  905518660                       # The number of ROB writes
 system.cpu2.timesIdled                        2960768                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index 6fc6c48c5..02f99a8e5 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -873,7 +873,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total        532162399                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events             22726868                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                  1220262369                       # The number of ROB reads
 system.cpu0.rob.rob_writes                 1241914021                       # The number of ROB writes
 system.cpu0.timesIdled                        4040058                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1848,7 +1847,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total        535141123                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events             22907771                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                  1220174232                       # The number of ROB reads
 system.cpu1.rob.rob_writes                 1248183780                       # The number of ROB writes
 system.cpu1.timesIdled                        4134360                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index daa556624..ba0576175 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -597,7 +597,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         806389826                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               5444825                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1270729806                       # The number of ROB reads
 system.cpu.rob.rob_writes                  1664729387                       # The number of ROB writes
 system.cpu.timesIdled                          294275                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index fa561f06e..fbb8e7287 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1103,7 +1103,6 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total        270578300                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events              2129956                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                   431186663                       # The number of ROB reads
 system.cpu2.rob.rob_writes                  561693850                       # The number of ROB writes
 system.cpu2.timesIdled                         124283                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 8fe6f61b1..0eb73f5eb 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -676,7 +676,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053638                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               4111371                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    217986125                       # The number of ROB reads
 system.cpu.rob.rob_writes                   219581178                       # The number of ROB writes
 system.cpu.timesIdled                             584                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 22cc57507..3dba3eae0 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -557,7 +557,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              23473761                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    419820689                       # The number of ROB reads
 system.cpu.rob.rob_writes                   657620446                       # The number of ROB writes
 system.cpu.timesIdled                             598                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 17deb175b..f698c7645 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -686,7 +686,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548694828                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              13831485                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1093653497                       # The number of ROB reads
 system.cpu.rob.rob_writes                  1334601058                       # The number of ROB writes
 system.cpu.timesIdled                           13925                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index a1911a66a..83e6f9459 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -579,7 +579,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              76872227                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   2867051516                       # The number of ROB reads
 system.cpu.rob.rob_writes                  4304473794                       # The number of ROB writes
 system.cpu.timesIdled                            2567                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 7866e7931..52921a0e6 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -572,7 +572,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              29857166                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    543683043                       # The number of ROB reads
 system.cpu.rob.rob_writes                   885930772                       # The number of ROB writes
 system.cpu.timesIdled                            3165                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 869d3326a..44f85cf9d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -655,7 +655,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812213                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              10346735                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    561599370                       # The number of ROB reads
 system.cpu.rob.rob_writes                   705507733                       # The number of ROB writes
 system.cpu.timesIdled                           50679                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 492f134ce..362966e09 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -595,7 +595,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              50554341                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1905392712                       # The number of ROB reads
 system.cpu.rob.rob_writes                  3017093514                       # The number of ROB writes
 system.cpu.timesIdled                            3164                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index c41e8c5e9..a4b1f4996 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -692,7 +692,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730069                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              22360483                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   1891410858                       # The number of ROB reads
 system.cpu.rob.rob_writes                  2343104087                       # The number of ROB writes
 system.cpu.timesIdled                          647398                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index c7130e3ac..621cb9617 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -601,7 +601,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               5716148                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    133590014                       # The number of ROB reads
 system.cpu.rob.rob_writes                   196617452                       # The number of ROB writes
 system.cpu.timesIdled                           47547                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index c55c80533..ae7859585 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -687,7 +687,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688136                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               3769965                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    158240550                       # The number of ROB reads
 system.cpu.rob.rob_writes                   195514428                       # The number of ROB writes
 system.cpu.timesIdled                           23835                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 47b73b46e..0d7c52b8c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -621,7 +621,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
 system.cpu.commit.bw_lim_events             106281090                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   3840325519                       # The number of ROB reads
 system.cpu.rob.rob_writes                  5790523687                       # The number of ROB writes
 system.cpu.timesIdled                             690                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index d3007a8e0..da2c7807d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -703,7 +703,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032433                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              58069727                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                   3367926925                       # The number of ROB reads
 system.cpu.rob.rob_writes                  3883468057                       # The number of ROB writes
 system.cpu.timesIdled                             846                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 9c86c55d6..3087f396d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -572,7 +572,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               6204717                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    157112780                       # The number of ROB reads
 system.cpu.rob.rob_writes                   252206838                       # The number of ROB writes
 system.cpu.timesIdled                            4633                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index bc1d643b6..93505db81 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -656,7 +656,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650341                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               3352927                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    406304779                       # The number of ROB reads
 system.cpu.rob.rob_writes                   513839131                       # The number of ROB writes
 system.cpu.timesIdled                            3408                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index e5c937252..f61e2dda8 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -539,7 +539,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               6920063                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                    615300578                       # The number of ROB reads
 system.cpu.rob.rob_writes                   699132843                       # The number of ROB writes
 system.cpu.timesIdled                            3156                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 2a2f37965..78cb13dcc 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -25,6 +25,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
@@ -394,9 +395,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -478,11 +481,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -543,11 +549,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 22813f4db..0b689db35 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -25,6 +25,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
@@ -227,8 +228,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -310,9 +314,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -358,11 +364,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 9e0ef63d1..6dd8362e8 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -25,6 +25,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
@@ -386,9 +387,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -470,11 +473,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -524,7 +530,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -599,11 +605,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 3be47cc9f..586901b21 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -25,6 +25,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
@@ -223,8 +224,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -306,9 +310,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -354,11 +360,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -408,7 +417,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index dfefc0ae8..77c9ca9fd 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -177,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -194,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -288,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -305,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -389,13 +390,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -481,6 +485,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -498,7 +503,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -592,6 +596,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -609,7 +614,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -693,13 +697,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
 [system.cpu1.tracer]
 type=ExeTracer
@@ -730,9 +737,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -814,11 +823,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1515,11 +1527,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 214674a58..089dbf6ee 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -177,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -194,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -288,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -305,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -364,13 +365,16 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -401,9 +405,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -449,11 +455,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index ab3d1e239..bb8aa99f6 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM
 mem_mode=timing
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -173,6 +174,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -190,7 +192,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -284,6 +285,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -301,7 +303,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -385,13 +386,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -473,6 +477,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -490,7 +495,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -584,6 +588,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -601,7 +606,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -685,13 +689,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
 [system.cpu1.tracer]
 type=ExeTracer
@@ -722,9 +729,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -806,11 +815,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -860,7 +872,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -1571,11 +1583,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 8649cd2a1..3447337f9 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM
 mem_mode=timing
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -173,6 +174,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -190,7 +192,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -284,6 +285,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -301,7 +303,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -360,13 +361,16 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -397,9 +401,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -445,11 +451,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -499,7 +508,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index f413c6048..8c83d4cbb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -177,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -194,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -288,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -305,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -370,6 +371,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -439,6 +441,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -502,9 +505,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -586,11 +591,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1287,13 +1295,16 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.vncserver]
 type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 76a216752..6a2ebe226 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -177,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -194,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -288,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -305,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -389,13 +390,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -481,6 +485,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -498,7 +503,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -592,6 +596,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -609,7 +614,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -693,13 +697,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
 [system.cpu1.tracer]
 type=ExeTracer
@@ -730,9 +737,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -814,11 +823,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1515,11 +1527,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
index eb15ee6f5..f454bf736 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -177,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -194,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -288,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -305,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -364,13 +365,16 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -401,9 +405,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -449,11 +455,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 95d0c343b..1dec8a2fa 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
 mem_mode=timing
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -173,6 +174,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -190,7 +192,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -284,6 +285,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -301,7 +303,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -385,13 +386,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -473,6 +477,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -490,7 +495,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -584,6 +588,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -601,7 +606,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -685,13 +689,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
 [system.cpu1.tracer]
 type=ExeTracer
@@ -722,9 +729,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -806,11 +815,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -860,7 +872,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -1571,11 +1583,14 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index a676cb380..9587f8b73 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
 mem_mode=timing
 mem_ranges=2147483648:2415919103
 memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -173,6 +174,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -190,7 +192,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -284,6 +285,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -301,7 +303,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -360,13 +361,16 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -397,9 +401,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -445,11 +451,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -499,7 +508,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
index 65b142595..7b6dda94d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,21 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +87,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +143,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -176,6 +178,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -193,7 +196,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -218,6 +220,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -286,6 +289,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -303,7 +307,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -368,6 +371,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -437,6 +441,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -500,9 +505,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -513,6 +520,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -548,6 +556,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -582,11 +591,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1283,13 +1295,16 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.vncserver]
 type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index c9fbc7059..9f116c7eb 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -20,15 +20,16 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -362,8 +363,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -818,9 +822,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
-width=8
+width=16
 default=system.pc.pciconfig.pio
 master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
@@ -866,11 +872,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
@@ -1208,7 +1217,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1231,7 +1240,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 8b71c52a2..c5dd21d18 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,15 +20,16 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -358,8 +359,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -814,9 +818,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
-width=8
+width=16
 default=system.pc.pciconfig.pio
 master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
@@ -862,11 +868,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
@@ -1204,7 +1213,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1227,7 +1236,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1442,7 +1451,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index d12ae3672..ace958078 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -15,6 +15,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=drivesys.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
@@ -191,9 +192,11 @@ slave=drivesys.iobus.master[29]
 type=NoncoherentXBar
 clk_domain=drivesys.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=drivesys.tsunami.pciconfig.pio
 master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
 slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
@@ -203,11 +206,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=drivesys.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=drivesys
 use_default_range=false
-width=8
+width=16
 default=drivesys.membus.badaddr_responder.pio
 master=drivesys.bridge.slave drivesys.physmem.port
 slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
@@ -379,7 +385,7 @@ dma_read_factor=0
 dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
-hardware_address=00:90:00:00:00:02
+hardware_address=00:90:00:00:00:01
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
@@ -944,6 +950,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=testsys.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
@@ -1120,9 +1127,11 @@ slave=testsys.iobus.master[29]
 type=NoncoherentXBar
 clk_domain=testsys.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=testsys.tsunami.pciconfig.pio
 master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
 slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
@@ -1132,11 +1141,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=testsys.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=testsys
 use_default_range=false
-width=8
+width=16
 default=testsys.membus.badaddr_responder.pio
 master=testsys.bridge.slave testsys.physmem.port
 slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
@@ -1308,7 +1320,7 @@ dma_read_factor=0
 dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
-hardware_address=00:90:00:00:00:01
+hardware_address=00:90:00:00:00:02
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index 0f651c9f7..8776aa226 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -638,8 +639,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -693,11 +697,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -728,7 +735,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 9165579c2..2212e87d6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -587,8 +588,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -642,11 +646,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -677,7 +684,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index edf4ba710..d3a56e05c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -569,7 +569,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   190                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        25491                       # The number of ROB reads
 system.cpu.rob.rob_writes                       27316                       # The number of ROB writes
 system.cpu.timesIdled                             260                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 50fa51df7..f5748224b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -107,6 +108,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -115,6 +117,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -144,11 +147,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index 8f9379027..566450d05 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -336,7 +340,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -506,7 +509,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index f8cc14345..c453da7e6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -321,7 +325,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -490,7 +493,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index e68e0eb6b..c97f7f381 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -338,7 +342,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -510,7 +513,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 8473e2239..df9dcb459 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -360,7 +364,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -464,7 +467,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 791e6db74..a0fdb76c4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -305,7 +309,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -409,7 +412,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 8332a7a3a..4f89807d5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -207,8 +208,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -262,11 +266,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index 66098146a..b89f21c49 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -638,8 +639,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -693,11 +697,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -728,7 +735,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 19ac3530d..78a45bd07 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -587,8 +588,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -642,11 +646,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -677,7 +684,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 165a7d5f5..9e6af9059 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -569,7 +569,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                    69                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        11659                       # The number of ROB reads
 system.cpu.rob.rob_writes                       10686                       # The number of ROB writes
 system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index f69c898cb..b1961bd8d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -107,6 +108,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -115,6 +117,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -144,11 +147,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index cfffbc558..58df6e402 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -336,7 +340,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -506,7 +509,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 0dadccb22..7737f4b73 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -321,7 +325,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -490,7 +493,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index e1272a9ad..5ec342cb1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -338,7 +342,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -510,7 +513,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index aaffdb113..8f4fa29a5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -360,7 +364,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -464,7 +467,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 7b61f2363..a20d94574 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -111,6 +112,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -119,6 +121,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -163,7 +166,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -305,7 +309,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -409,7 +412,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 402442761..ea66af4ee 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,6 +83,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +124,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -171,6 +174,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -204,8 +208,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -220,6 +227,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -228,6 +236,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -257,11 +266,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index c7a245793..3d022001c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -167,6 +168,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -184,7 +186,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -661,6 +662,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -678,7 +680,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -737,13 +738,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -792,11 +796,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -827,7 +834,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 78a71faf3..c26f32538 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -191,6 +192,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.checker.dtb
 
 [system.cpu.checker.dstage2_mmu.stage2_tlb]
@@ -208,7 +210,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[9]
 
 [system.cpu.checker.dtb]
 type=ArmTLB
@@ -225,7 +226,7 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[7]
+port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.checker.isa]
 type=ArmISA
@@ -254,6 +255,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.checker.istage2_mmu]
@@ -261,6 +263,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.checker.itb
 
 [system.cpu.checker.istage2_mmu.stage2_tlb]
@@ -278,7 +281,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[8]
 
 [system.cpu.checker.itb]
 type=ArmTLB
@@ -295,7 +297,7 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[6]
+port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.checker.tracer]
 type=ExeTracer
@@ -307,6 +309,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -341,6 +344,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -358,7 +362,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -690,6 +693,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -750,6 +754,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -757,6 +762,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -774,7 +780,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -799,6 +804,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -832,13 +838,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -848,6 +857,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -856,6 +866,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -885,11 +896,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -920,7 +934,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -929,6 +943,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index eb7b98cb0..086544e33 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -773,7 +773,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   113                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        22770                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21679                       # The number of ROB writes
 system.cpu.timesIdled                             199                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index a1b6a8304..8f050d759 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -157,6 +158,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -191,6 +193,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -208,7 +211,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -498,6 +500,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -558,6 +561,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -565,6 +569,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -582,7 +587,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -607,6 +611,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -628,19 +633,27 @@ mem_side=system.membus.slave[1]
 
 [system.cpu.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu.l2cache.tags]
@@ -657,13 +670,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -673,6 +689,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -681,6 +698,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -710,11 +728,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -745,7 +766,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -754,6 +775,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 9add0d45b..1162c6d13 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -655,7 +655,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                    44                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        22696                       # The number of ROB reads
 system.cpu.rob.rob_writes                       16433                       # The number of ROB writes
 system.cpu.timesIdled                             211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 91da4c557..af3e16c1f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -122,6 +123,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.checker.dtb
 
 [system.cpu.checker.dstage2_mmu.stage2_tlb]
@@ -183,6 +185,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.checker.istage2_mmu]
@@ -190,6 +193,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.checker.itb
 
 [system.cpu.checker.istage2_mmu.stage2_tlb]
@@ -233,6 +237,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -250,7 +255,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -300,6 +304,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -307,6 +312,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -324,7 +330,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -351,6 +356,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -359,6 +365,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -388,13 +395,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index 2e24c6545..8f14d69f7 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -205,6 +207,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 54668155a..5fb17fcaa 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -84,6 +85,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -118,6 +120,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -135,7 +138,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -160,6 +162,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -220,6 +223,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -227,6 +231,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -244,7 +249,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -269,6 +273,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -302,13 +307,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -318,6 +326,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -326,6 +335,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -355,11 +365,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 946ab8388..e8f178a23 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -155,6 +156,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +504,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -553,6 +556,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -586,8 +590,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -602,6 +609,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -610,6 +618,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -639,11 +648,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -674,7 +686,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -683,6 +695,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index f65d4ed09..74a03945e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -555,7 +555,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5623                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   103                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        23990                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21831                       # The number of ROB writes
 system.cpu.timesIdled                             267                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 4e242dacc..3d063a0b8 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -109,6 +110,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -117,6 +119,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -146,11 +149,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 8604f5de4..68740c2e9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -113,6 +114,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -121,6 +123,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -165,7 +168,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -218,6 +221,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -307,7 +311,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -411,7 +414,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index e0e01d26c..01cbbe08b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,6 +83,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +124,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -173,6 +176,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -206,8 +210,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -222,6 +229,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -230,6 +238,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -259,11 +268,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 709f4f73b..e1985510b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -156,6 +157,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -503,6 +505,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -551,6 +554,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -584,8 +588,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -600,6 +607,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -608,6 +616,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -637,11 +646,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -672,7 +684,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -681,6 +693,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index c9ca56107..5e6b95b13 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -556,7 +556,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   110                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        22278                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21482                       # The number of ROB writes
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 00428c3e1..3bfe108d2 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -107,6 +108,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -115,6 +117,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -144,11 +147,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 10cf57bb4..4603bc218 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -106,6 +107,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -114,6 +116,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +146,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 8d6cf097f..2cde94243 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -110,6 +111,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -118,6 +120,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -162,7 +165,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -215,6 +218,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -304,7 +308,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -408,7 +411,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index e38847653..60f2b3295 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,6 +83,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +124,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -170,6 +173,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -203,8 +207,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -219,6 +226,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -227,6 +235,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -256,11 +265,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 64e1a1f99..3a8953fb2 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -620,8 +621,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -675,11 +679,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
@@ -710,7 +717,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 8ea066b3b..7e789d2c1 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -536,7 +536,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   259                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        43058                       # The number of ROB reads
 system.cpu.rob.rob_writes                       44876                       # The number of ROB writes
 system.cpu.timesIdled                             157                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 9ee52b54f..938ee4ed9 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -179,11 +180,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 9bc617783..5d12ba5c2 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -198,7 +199,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -251,6 +252,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -340,7 +342,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -445,7 +446,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 916d9b36b..001f21930 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -240,8 +241,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -295,11 +299,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index d358e4bd4..febd22775 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -155,6 +156,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +504,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -556,6 +559,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -589,8 +593,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -605,6 +612,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -613,6 +621,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -626,6 +635,7 @@ useArchPT=false
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -634,6 +644,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -663,11 +674,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -698,7 +712,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -707,6 +721,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 3794759d9..1a4bdd660 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -708,9 +708,6 @@ system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_1::total              6389                       # Class of committed instruction
 system.cpu.commit.op_class::total               12778      0.00%      0.00% # Class of committed instruction
 system.cpu.commit.bw_lim_events                   325                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
-system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
-system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                       130940                       # The number of ROB reads
 system.cpu.rob.rob_writes                       58397                       # The number of ROB writes
 system.cpu.timesIdled                             389                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 144f058d7..3156d1d19 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -155,6 +156,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +504,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -550,6 +553,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -583,8 +587,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -599,6 +606,7 @@ eventq_index=0
 type=LiveProcess
 cmd=insttest
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -607,6 +615,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -636,11 +645,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -671,7 +683,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -680,6 +692,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index fe03e9faf..6c1b2fdec 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -533,7 +533,6 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   272                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.rob.rob_reads                        54715                       # The number of ROB reads
 system.cpu.rob.rob_writes                       52974                       # The number of ROB writes
 system.cpu.timesIdled                             200                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index fc4381d3d..03bf761da 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -106,6 +107,7 @@ eventq_index=0
 type=LiveProcess
 cmd=insttest
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -114,6 +116,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +146,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 727287e35..5a5031a15 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,6 +83,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +124,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -170,6 +173,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -203,8 +207,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -219,6 +226,7 @@ eventq_index=0
 type=LiveProcess
 cmd=insttest
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -227,6 +235,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -256,11 +265,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 8f525a009..4a4cc509f 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -2150,11 +2151,14 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
@@ -2185,7 +2189,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -2239,11 +2243,14 @@ port=system.membus.master[0]
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 948908ba0..97adbdaa9 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -563,7 +563,6 @@ system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total           450384                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events                  494                       # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.rob.rob_reads                      649458                       # The number of ROB reads
 system.cpu0.rob.rob_writes                     931043                       # The number of ROB writes
 system.cpu0.timesIdled                            314                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1087,7 +1086,6 @@ system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::total           251602                       # Class of committed instruction
 system.cpu1.commit.bw_lim_events                 1312                       # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.rob.rob_reads                      417798                       # The number of ROB reads
 system.cpu1.rob.rob_writes                     534614                       # The number of ROB writes
 system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1607,7 +1605,6 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total           246921                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events                 1310                       # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.rob.rob_reads                      416888                       # The number of ROB reads
 system.cpu2.rob.rob_writes                     525783                       # The number of ROB writes
 system.cpu2.timesIdled                            205                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -2128,7 +2125,6 @@ system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::total           238347                       # Class of committed instruction
 system.cpu3.commit.bw_lim_events                 1300                       # number cycles where commit BW limit reached
-system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu3.rob.rob_reads                      408052                       # The number of ROB reads
 system.cpu3.rob.rob_writes                     507784                       # The number of ROB writes
 system.cpu3.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index dc830ef72..0b278b17c 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -86,6 +87,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -126,6 +128,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -176,6 +179,7 @@ eventq_index=0
 type=LiveProcess
 cmd=test_atomic 4
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -184,6 +188,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -236,6 +241,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -276,6 +282,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -365,6 +372,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -405,6 +413,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -494,6 +503,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -534,6 +544,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -602,6 +613,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -635,11 +647,14 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
@@ -660,11 +675,14 @@ port=system.membus.master[0]
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 2ad22e920..68e115348 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,6 +83,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +124,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -172,6 +175,7 @@ eventq_index=0
 type=LiveProcess
 cmd=test_atomic 4
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -180,6 +184,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -228,6 +233,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -268,6 +274,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -353,6 +360,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -393,6 +401,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -478,6 +487,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -518,6 +528,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -586,6 +597,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -619,11 +631,14 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.l2c.mem_side
 
@@ -644,11 +659,14 @@ port=system.membus.master[0]
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 2056212e7..5b3edc5fa 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -45,163 +46,131 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
@@ -219,29 +188,6 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.mem_ctrls]
 type=DRAMCtrl
 IDD0=0.075000
@@ -269,7 +215,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -322,6 +268,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -442,7 +389,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
@@ -456,7 +402,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
 
 [system.ruby.l1_cntrl1]
 type=L1Cache_Controller
@@ -531,7 +477,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
@@ -545,7 +490,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
 
 [system.ruby.l1_cntrl2]
 type=L1Cache_Controller
@@ -620,7 +565,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
@@ -634,7 +578,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
 
 [system.ruby.l1_cntrl3]
 type=L1Cache_Controller
@@ -709,7 +653,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
@@ -723,7 +666,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
 
 [system.ruby.l1_cntrl4]
 type=L1Cache_Controller
@@ -798,7 +741,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
@@ -812,7 +754,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
 
 [system.ruby.l1_cntrl5]
 type=L1Cache_Controller
@@ -887,7 +829,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
@@ -901,7 +842,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
 
 [system.ruby.l1_cntrl6]
 type=L1Cache_Controller
@@ -976,7 +917,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
@@ -990,7 +930,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
 
 [system.ruby.l1_cntrl7]
 type=L1Cache_Controller
@@ -1065,7 +1005,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
@@ -1079,7 +1018,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
 
 [system.ruby.l2_cntrl0]
 type=L2Cache_Controller
@@ -1424,7 +1363,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index 0c7adcd05..f3306cd28 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -45,163 +46,131 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
@@ -219,29 +188,6 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.mem_ctrls]
 type=DRAMCtrl
 IDD0=0.075000
@@ -269,7 +215,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -322,6 +268,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -427,7 +374,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
@@ -441,7 +387,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
 
 [system.ruby.l1_cntrl1]
 type=L1Cache_Controller
@@ -500,7 +446,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
@@ -514,7 +459,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
 
 [system.ruby.l1_cntrl2]
 type=L1Cache_Controller
@@ -573,7 +518,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
@@ -587,7 +531,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
 
 [system.ruby.l1_cntrl3]
 type=L1Cache_Controller
@@ -646,7 +590,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
@@ -660,7 +603,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
 
 [system.ruby.l1_cntrl4]
 type=L1Cache_Controller
@@ -719,7 +662,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
@@ -733,7 +675,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
 
 [system.ruby.l1_cntrl5]
 type=L1Cache_Controller
@@ -792,7 +734,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
@@ -806,7 +747,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
 
 [system.ruby.l1_cntrl6]
 type=L1Cache_Controller
@@ -865,7 +806,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
@@ -879,7 +819,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
 
 [system.ruby.l1_cntrl7]
 type=L1Cache_Controller
@@ -938,7 +878,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
@@ -952,7 +891,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
 
 [system.ruby.l2_cntrl0]
 type=L2Cache_Controller
@@ -1296,7 +1235,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index f99cf2ff6..149e26f4e 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -45,163 +46,131 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
@@ -219,29 +188,6 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.mem_ctrls]
 type=DRAMCtrl
 IDD0=0.075000
@@ -269,7 +215,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -322,6 +268,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -444,7 +391,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
@@ -458,7 +404,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
 
 [system.ruby.l1_cntrl1]
 type=L1Cache_Controller
@@ -526,7 +472,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
@@ -540,7 +485,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
 
 [system.ruby.l1_cntrl2]
 type=L1Cache_Controller
@@ -608,7 +553,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
@@ -622,7 +566,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
 
 [system.ruby.l1_cntrl3]
 type=L1Cache_Controller
@@ -690,7 +634,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
@@ -704,7 +647,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
 
 [system.ruby.l1_cntrl4]
 type=L1Cache_Controller
@@ -772,7 +715,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
@@ -786,7 +728,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
 
 [system.ruby.l1_cntrl5]
 type=L1Cache_Controller
@@ -854,7 +796,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
@@ -868,7 +809,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
 
 [system.ruby.l1_cntrl6]
 type=L1Cache_Controller
@@ -936,7 +877,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
@@ -950,7 +890,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
 
 [system.ruby.l1_cntrl7]
 type=L1Cache_Controller
@@ -1018,7 +958,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
@@ -1032,7 +971,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
 
 [system.ruby.l2_cntrl0]
 type=L2Cache_Controller
@@ -1379,7 +1318,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 1c9a952a1..38c85fff5 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.mem_ctrls system.funcmem
+memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -45,163 +46,131 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
@@ -219,29 +188,6 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.mem_ctrls]
 type=DRAMCtrl
 IDD0=0.075000
@@ -269,7 +215,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -322,6 +268,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -466,7 +413,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
@@ -480,7 +426,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
 
 [system.ruby.l1_cntrl1]
 type=L1Cache_Controller
@@ -557,7 +503,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
@@ -571,7 +516,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
 
 [system.ruby.l1_cntrl2]
 type=L1Cache_Controller
@@ -648,7 +593,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
@@ -662,7 +606,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
 
 [system.ruby.l1_cntrl3]
 type=L1Cache_Controller
@@ -739,7 +683,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
@@ -753,7 +696,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
 
 [system.ruby.l1_cntrl4]
 type=L1Cache_Controller
@@ -830,7 +773,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
@@ -844,7 +786,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
 
 [system.ruby.l1_cntrl5]
 type=L1Cache_Controller
@@ -921,7 +863,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
@@ -935,7 +876,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
 
 [system.ruby.l1_cntrl6]
 type=L1Cache_Controller
@@ -1012,7 +953,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
@@ -1026,7 +966,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
 
 [system.ruby.l1_cntrl7]
 type=L1Cache_Controller
@@ -1103,7 +1043,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
@@ -1117,7 +1056,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
 
 [system.ruby.memctrl_clk_domain]
 type=DerivedClockDomain
@@ -1396,7 +1335,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 15c73e8ec..75224c394 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.mem_ctrls system.funcmem
+memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -45,163 +46,131 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
 
 [system.cpu1]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
 
 [system.cpu2]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
 
 [system.cpu3]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
 
 [system.cpu4]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
 
 [system.cpu5]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
 
 [system.cpu6]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
 
 [system.cpu7]
 type=MemTest
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=0
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
@@ -219,29 +188,6 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.mem_ctrls]
 type=DRAMCtrl
 IDD0=0.075000
@@ -269,7 +215,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -322,6 +268,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -411,7 +358,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=1000000
@@ -425,7 +371,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
 
 [system.ruby.l1_cntrl1]
 type=L1Cache_Controller
@@ -467,7 +413,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.cacheMemory
 deadlock_threshold=1000000
@@ -481,7 +426,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
 
 [system.ruby.l1_cntrl2]
 type=L1Cache_Controller
@@ -523,7 +468,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl2.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl2.cacheMemory
 deadlock_threshold=1000000
@@ -537,7 +481,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
 
 [system.ruby.l1_cntrl3]
 type=L1Cache_Controller
@@ -579,7 +523,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl3.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl3.cacheMemory
 deadlock_threshold=1000000
@@ -593,7 +536,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
 
 [system.ruby.l1_cntrl4]
 type=L1Cache_Controller
@@ -635,7 +578,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl4.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl4.cacheMemory
 deadlock_threshold=1000000
@@ -649,7 +591,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
 
 [system.ruby.l1_cntrl5]
 type=L1Cache_Controller
@@ -691,7 +633,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl5.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl5.cacheMemory
 deadlock_threshold=1000000
@@ -705,7 +646,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
 
 [system.ruby.l1_cntrl6]
 type=L1Cache_Controller
@@ -747,7 +688,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl6.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl6.cacheMemory
 deadlock_threshold=1000000
@@ -761,7 +701,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
 
 [system.ruby.l1_cntrl7]
 type=L1Cache_Controller
@@ -803,7 +743,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl7.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl7.cacheMemory
 deadlock_threshold=1000000
@@ -817,7 +756,7 @@ system=system
 using_network_tester=false
 using_ruby_tester=false
 version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
 
 [system.ruby.memctrl_clk_domain]
 type=DerivedClockDomain
@@ -1096,7 +1035,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index 6605d530a..27d9847c3 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -46,23 +47,19 @@ voltage_domain=system.voltage_domain
 [system.cpu0]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.cpu0.l1c.cpu_side
+system=system
+port=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
 type=BaseCache
@@ -70,6 +67,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -86,7 +84,7 @@ tags=system.cpu0.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu0.test
+cpu_side=system.cpu0.port
 mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l1c.tags]
@@ -102,23 +100,19 @@ size=32768
 [system.cpu1]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.cpu1.l1c.cpu_side
+system=system
+port=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
 type=BaseCache
@@ -126,6 +120,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -142,7 +137,7 @@ tags=system.cpu1.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu1.test
+cpu_side=system.cpu1.port
 mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l1c.tags]
@@ -158,23 +153,19 @@ size=32768
 [system.cpu2]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.cpu2.l1c.cpu_side
+system=system
+port=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
 type=BaseCache
@@ -182,6 +173,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -198,7 +190,7 @@ tags=system.cpu2.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu2.test
+cpu_side=system.cpu2.port
 mem_side=system.toL2Bus.slave[2]
 
 [system.cpu2.l1c.tags]
@@ -214,23 +206,19 @@ size=32768
 [system.cpu3]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.cpu3.l1c.cpu_side
+system=system
+port=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
 type=BaseCache
@@ -238,6 +226,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -254,7 +243,7 @@ tags=system.cpu3.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu3.test
+cpu_side=system.cpu3.port
 mem_side=system.toL2Bus.slave[3]
 
 [system.cpu3.l1c.tags]
@@ -270,23 +259,19 @@ size=32768
 [system.cpu4]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.cpu4.l1c.cpu_side
+system=system
+port=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
 type=BaseCache
@@ -294,6 +279,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -310,7 +296,7 @@ tags=system.cpu4.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu4.test
+cpu_side=system.cpu4.port
 mem_side=system.toL2Bus.slave[4]
 
 [system.cpu4.l1c.tags]
@@ -326,23 +312,19 @@ size=32768
 [system.cpu5]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.cpu5.l1c.cpu_side
+system=system
+port=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
 type=BaseCache
@@ -350,6 +332,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -366,7 +349,7 @@ tags=system.cpu5.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu5.test
+cpu_side=system.cpu5.port
 mem_side=system.toL2Bus.slave[5]
 
 [system.cpu5.l1c.tags]
@@ -382,23 +365,19 @@ size=32768
 [system.cpu6]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.cpu6.l1c.cpu_side
+system=system
+port=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
 type=BaseCache
@@ -406,6 +385,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -422,7 +402,7 @@ tags=system.cpu6.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu6.test
+cpu_side=system.cpu6.port
 mem_side=system.toL2Bus.slave[6]
 
 [system.cpu6.l1c.tags]
@@ -438,23 +418,19 @@ size=32768
 [system.cpu7]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.cpu7.l1c.cpu_side
+system=system
+port=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
 type=BaseCache
@@ -462,6 +438,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -478,7 +455,7 @@ tags=system.cpu7.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu7.test
+cpu_side=system.cpu7.port
 mem_side=system.toL2Bus.slave[7]
 
 [system.cpu7.l1c.tags]
@@ -507,35 +484,13 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.l2c]
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -570,8 +525,11 @@ type=CoherentXBar
 children=snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
 system=system
 use_default_range=false
 width=16
@@ -581,7 +539,7 @@ slave=system.l2c.mem_side system.system_port
 [system.membus.snoop_filter]
 type=SnoopFilter
 eventq_index=0
-lookup_latency=3
+lookup_latency=1
 system=system
 
 [system.physmem]
@@ -602,18 +560,21 @@ type=CoherentXBar
 children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=16
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 
 [system.toL2Bus.snoop_filter]
 type=SnoopFilter
 eventq_index=0
-lookup_latency=3
+lookup_latency=1
 system=system
 
 [system.voltage_domain]
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 06da0f372..a476e7586 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -22,7 +22,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -46,23 +47,19 @@ voltage_domain=system.voltage_domain
 [system.cpu0]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.cpu0.l1c.cpu_side
+system=system
+port=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
 type=BaseCache
@@ -70,6 +67,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -86,7 +84,7 @@ tags=system.cpu0.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu0.test
+cpu_side=system.cpu0.port
 mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l1c.tags]
@@ -102,23 +100,19 @@ size=32768
 [system.cpu1]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.cpu1.l1c.cpu_side
+system=system
+port=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
 type=BaseCache
@@ -126,6 +120,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -142,7 +137,7 @@ tags=system.cpu1.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu1.test
+cpu_side=system.cpu1.port
 mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l1c.tags]
@@ -158,23 +153,19 @@ size=32768
 [system.cpu2]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.cpu2.l1c.cpu_side
+system=system
+port=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
 type=BaseCache
@@ -182,6 +173,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -198,7 +190,7 @@ tags=system.cpu2.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu2.test
+cpu_side=system.cpu2.port
 mem_side=system.toL2Bus.slave[2]
 
 [system.cpu2.l1c.tags]
@@ -214,23 +206,19 @@ size=32768
 [system.cpu3]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.cpu3.l1c.cpu_side
+system=system
+port=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
 type=BaseCache
@@ -238,6 +226,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -254,7 +243,7 @@ tags=system.cpu3.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu3.test
+cpu_side=system.cpu3.port
 mem_side=system.toL2Bus.slave[3]
 
 [system.cpu3.l1c.tags]
@@ -270,23 +259,19 @@ size=32768
 [system.cpu4]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.cpu4.l1c.cpu_side
+system=system
+port=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
 type=BaseCache
@@ -294,6 +279,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -310,7 +296,7 @@ tags=system.cpu4.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu4.test
+cpu_side=system.cpu4.port
 mem_side=system.toL2Bus.slave[4]
 
 [system.cpu4.l1c.tags]
@@ -326,23 +312,19 @@ size=32768
 [system.cpu5]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.cpu5.l1c.cpu_side
+system=system
+port=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
 type=BaseCache
@@ -350,6 +332,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -366,7 +349,7 @@ tags=system.cpu5.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu5.test
+cpu_side=system.cpu5.port
 mem_side=system.toL2Bus.slave[5]
 
 [system.cpu5.l1c.tags]
@@ -382,23 +365,19 @@ size=32768
 [system.cpu6]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.cpu6.l1c.cpu_side
+system=system
+port=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
 type=BaseCache
@@ -406,6 +385,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -422,7 +402,7 @@ tags=system.cpu6.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu6.test
+cpu_side=system.cpu6.port
 mem_side=system.toL2Bus.slave[6]
 
 [system.cpu6.l1c.tags]
@@ -438,23 +418,19 @@ size=32768
 [system.cpu7]
 type=MemTest
 children=l1c
-atomic=false
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-issue_dmas=false
+interval=1
 max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
 percent_functional=50
 percent_reads=65
-percent_source_unaligned=50
 percent_uncacheable=10
+progress_check=5000000
 progress_interval=10000
+size=65536
 suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.cpu7.l1c.cpu_side
+system=system
+port=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
 type=BaseCache
@@ -462,6 +438,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -478,7 +455,7 @@ tags=system.cpu7.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu7.test
+cpu_side=system.cpu7.port
 mem_side=system.toL2Bus.slave[7]
 
 [system.cpu7.l1c.tags]
@@ -507,35 +484,13 @@ eventq_index=0
 sys_clk_domain=system.clk_domain
 transition_latency=100000000
 
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
 [system.l2c]
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -569,8 +524,11 @@ size=65536
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
 width=16
@@ -594,11 +552,14 @@ port=system.membus.master[0]
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=16
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index 578c80a62..27433c589 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -91,7 +92,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -144,6 +145,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -264,7 +266,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -434,7 +435,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index e824f18b8..e6a208fbe 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -91,7 +92,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -144,6 +145,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -249,7 +251,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -418,7 +419,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 449426c95..6402fc4de 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -91,7 +92,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -144,6 +145,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -266,7 +268,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -438,7 +439,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index f04aef1cf..c5c0c425f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -91,7 +92,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -144,6 +145,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -288,7 +290,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -392,7 +393,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 7a41a41a1..0d98bbb99 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:268435455
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -91,7 +92,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -144,6 +145,7 @@ port=system.ruby.dir_cntrl0.memory
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -233,7 +235,6 @@ tagArrayBanks=1
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
@@ -337,7 +338,6 @@ virt_nets=10
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index b1d661d27..82326fb62 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -70,7 +71,9 @@ transition_latency=100000000
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
 width=16
 master=system.physmem.port
@@ -95,6 +98,7 @@ latency_bins=20
 outstanding_bins=20
 read_addr_mask=18446744073709551615
 sample_period=1000000000
+stack_dist_calc=Null
 system=system
 trace_compress=true
 trace_enable=false
@@ -131,7 +135,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -140,6 +144,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index c210da503..91ff0eb51 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -70,7 +71,9 @@ transition_latency=100000000
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
 width=16
 master=system.physmem.port
@@ -78,6 +81,7 @@ slave=system.monitor.master system.system_port
 
 [system.monitor]
 type=CommMonitor
+children=stack_dist_calc
 bandwidth_bins=20
 burst_length_bins=20
 clk_domain=system.clk_domain
@@ -95,6 +99,7 @@ latency_bins=20
 outstanding_bins=20
 read_addr_mask=18446744073709551615
 sample_period=1000000000
+stack_dist_calc=system.monitor.stack_dist_calc
 system=system
 trace_compress=true
 trace_enable=true
@@ -104,6 +109,15 @@ write_addr_mask=18446744073709551615
 master=system.membus.slave[0]
 slave=system.cpu.port
 
+[system.monitor.stack_dist_calc]
+type=StackDistCalc
+disable_linear_hists=false
+disable_log_hists=false
+eventq_index=0
+linear_hist_bins=16
+log_hist_bins=32
+verify=true
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-- 
cgit v1.2.3