From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 25 Jan 2012 17:19:50 +0000
Subject: stats: Update stats for final tick and memory bandwidth patches

---
 .../ref/alpha/tru64/inorder-timing/config.ini      |   10 +-
 .../00.gzip/ref/alpha/tru64/inorder-timing/simout  |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   19 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/config.ini   |    8 +-
 .../long/00.gzip/ref/alpha/tru64/o3-timing/simout  |    6 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt    |   19 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../00.gzip/ref/alpha/tru64/simple-atomic/simout   |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   19 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../00.gzip/ref/alpha/tru64/simple-timing/simout   |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   19 +-
 .../00.gzip/ref/arm/linux/o3-timing/config.ini     |   10 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/simout  |    6 +-
 .../long/00.gzip/ref/arm/linux/o3-timing/stats.txt |   19 +-
 .../00.gzip/ref/arm/linux/simple-atomic/config.ini |   13 +-
 .../00.gzip/ref/arm/linux/simple-atomic/simerr     |    1 -
 .../00.gzip/ref/arm/linux/simple-atomic/simout     |   16 +-
 .../00.gzip/ref/arm/linux/simple-atomic/stats.txt  |  109 +-
 .../00.gzip/ref/arm/linux/simple-timing/config.ini |   11 +-
 .../00.gzip/ref/arm/linux/simple-timing/simerr     |    1 -
 .../00.gzip/ref/arm/linux/simple-timing/simout     |   16 +-
 .../00.gzip/ref/arm/linux/simple-timing/stats.txt  |  475 ++---
 .../00.gzip/ref/sparc/linux/o3-timing/config.ini   |   10 +-
 .../long/00.gzip/ref/sparc/linux/o3-timing/simout  |    6 +-
 .../00.gzip/ref/sparc/linux/o3-timing/stats.txt    |   19 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   12 +-
 .../00.gzip/ref/sparc/linux/simple-atomic/simout   |    6 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   10 +-
 .../00.gzip/ref/sparc/linux/simple-timing/simout   |    6 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   19 +-
 .../00.gzip/ref/x86/linux/o3-timing/config.ini     |   10 +-
 tests/long/00.gzip/ref/x86/linux/o3-timing/simout  |    8 +-
 .../long/00.gzip/ref/x86/linux/o3-timing/stats.txt |   19 +-
 .../00.gzip/ref/x86/linux/simple-atomic/config.ini |   12 +-
 .../00.gzip/ref/x86/linux/simple-atomic/simout     |    8 +-
 .../00.gzip/ref/x86/linux/simple-atomic/stats.txt  |   19 +-
 .../00.gzip/ref/x86/linux/simple-timing/config.ini |   10 +-
 .../00.gzip/ref/x86/linux/simple-timing/simout     |    8 +-
 .../00.gzip/ref/x86/linux/simple-timing/stats.txt  |   19 +-
 .../ref/alpha/linux/tsunami-o3-dual/config.ini     |   47 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout         |    8 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt      |   19 +-
 .../ref/alpha/linux/tsunami-o3/config.ini          |   47 +-
 .../ref/alpha/linux/tsunami-o3/simout              |    8 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt           |   19 +-
 .../ref/arm/linux/realview-o3-dual/config.ini      |   68 +-
 .../ref/arm/linux/realview-o3-dual/simout          |    6 +-
 .../ref/arm/linux/realview-o3-dual/stats.txt       |   28 +-
 .../ref/arm/linux/realview-o3/config.ini           |   68 +-
 .../10.linux-boot/ref/arm/linux/realview-o3/simout |    6 +-
 .../ref/arm/linux/realview-o3/stats.txt            |   28 +-
 .../ref/x86/linux/pc-o3-timing/config.ini          |   85 +-
 .../ref/x86/linux/pc-o3-timing/simout              |   11 +-
 .../ref/x86/linux/pc-o3-timing/stats.txt           |   19 +-
 .../long/10.mcf/ref/arm/linux/o3-timing/config.ini |   12 +-
 tests/long/10.mcf/ref/arm/linux/o3-timing/simout   |    6 +-
 .../long/10.mcf/ref/arm/linux/o3-timing/stats.txt  |   19 +-
 .../10.mcf/ref/arm/linux/simple-atomic/config.ini  |   13 +-
 .../long/10.mcf/ref/arm/linux/simple-atomic/simerr |    1 -
 .../long/10.mcf/ref/arm/linux/simple-atomic/simout |   16 +-
 .../10.mcf/ref/arm/linux/simple-atomic/stats.txt   |  109 +-
 .../10.mcf/ref/arm/linux/simple-timing/config.ini  |   11 +-
 .../long/10.mcf/ref/arm/linux/simple-timing/simerr |    1 -
 .../long/10.mcf/ref/arm/linux/simple-timing/simout |   16 +-
 .../10.mcf/ref/arm/linux/simple-timing/stats.txt   |  475 ++---
 .../ref/sparc/linux/simple-atomic/config.ini       |   12 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/simout    |    6 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   10 +-
 .../10.mcf/ref/sparc/linux/simple-timing/simout    |    6 +-
 .../10.mcf/ref/sparc/linux/simple-timing/stats.txt |   19 +-
 .../long/10.mcf/ref/x86/linux/o3-timing/config.ini |   12 +-
 tests/long/10.mcf/ref/x86/linux/o3-timing/simout   |    8 +-
 .../long/10.mcf/ref/x86/linux/o3-timing/stats.txt  |   19 +-
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |   14 +-
 .../long/10.mcf/ref/x86/linux/simple-atomic/simout |    8 +-
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |   19 +-
 .../10.mcf/ref/x86/linux/simple-timing/config.ini  |   12 +-
 .../long/10.mcf/ref/x86/linux/simple-timing/simout |    8 +-
 .../10.mcf/ref/x86/linux/simple-timing/stats.txt   |   19 +-
 .../20.parser/ref/arm/linux/o3-timing/config.ini   |    7 +-
 .../long/20.parser/ref/arm/linux/o3-timing/simout  |    6 +-
 .../20.parser/ref/arm/linux/o3-timing/stats.txt    |   19 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   13 +-
 .../20.parser/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../20.parser/ref/arm/linux/simple-atomic/simout   |   16 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |   11 +-
 .../20.parser/ref/arm/linux/simple-timing/simerr   |    1 -
 .../20.parser/ref/arm/linux/simple-timing/simout   |   16 +-
 .../ref/arm/linux/simple-timing/stats.txt          |  475 ++---
 .../20.parser/ref/x86/linux/o3-timing/config.ini   |   12 +-
 .../long/20.parser/ref/x86/linux/o3-timing/simout  |    8 +-
 .../20.parser/ref/x86/linux/o3-timing/stats.txt    |   19 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   14 +-
 .../20.parser/ref/x86/linux/simple-atomic/simout   |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt          |   19 +-
 .../ref/x86/linux/simple-timing/config.ini         |   12 +-
 .../20.parser/ref/x86/linux/simple-timing/simout   |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt          |   19 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |   10 +-
 .../30.eon/ref/alpha/tru64/inorder-timing/simout   |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   18 +-
 .../30.eon/ref/alpha/tru64/o3-timing/config.ini    |    8 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../30.eon/ref/alpha/tru64/o3-timing/stats.txt     |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/simerr    |   11 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/simout    |   16 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |   89 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../30.eon/ref/alpha/tru64/simple-timing/simerr    |   11 +-
 .../30.eon/ref/alpha/tru64/simple-timing/simout    |   16 +-
 .../30.eon/ref/alpha/tru64/simple-timing/stats.txt |  446 ++---
 .../long/30.eon/ref/arm/linux/o3-timing/config.ini |   10 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/simout   |    6 +-
 .../long/30.eon/ref/arm/linux/o3-timing/stats.txt  |   18 +-
 .../30.eon/ref/arm/linux/simple-atomic/config.ini  |   13 +-
 .../long/30.eon/ref/arm/linux/simple-atomic/simerr |    1 -
 .../long/30.eon/ref/arm/linux/simple-atomic/simout |   16 +-
 .../30.eon/ref/arm/linux/simple-atomic/stats.txt   |  109 +-
 .../30.eon/ref/arm/linux/simple-timing/config.ini  |   11 +-
 .../long/30.eon/ref/arm/linux/simple-timing/simerr |    1 -
 .../long/30.eon/ref/arm/linux/simple-timing/simout |   16 +-
 .../30.eon/ref/arm/linux/simple-timing/stats.txt   |  474 ++---
 .../ref/alpha/tru64/o3-timing/config.ini           |    8 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/simout    |    6 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |   19 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../ref/alpha/tru64/simple-atomic/simout           |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   19 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../ref/alpha/tru64/simple-timing/simout           |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   19 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/config.ini  |   10 +-
 .../long/40.perlbmk/ref/arm/linux/o3-timing/simout |    6 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/stats.txt   |   19 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   13 +-
 .../40.perlbmk/ref/arm/linux/simple-atomic/simerr  |    2 -
 .../40.perlbmk/ref/arm/linux/simple-atomic/simout  |   16 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |   11 +-
 .../40.perlbmk/ref/arm/linux/simple-timing/simerr  |    2 -
 .../40.perlbmk/ref/arm/linux/simple-timing/simout  |   16 +-
 .../ref/arm/linux/simple-timing/stats.txt          |  475 ++---
 .../ref/alpha/tru64/inorder-timing/config.ini      |   10 +-
 .../ref/alpha/tru64/inorder-timing/simout          |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   19 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/config.ini |    8 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/simout     |    6 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt  |   19 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../50.vortex/ref/alpha/tru64/simple-atomic/simout |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   19 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../50.vortex/ref/alpha/tru64/simple-timing/simout |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   19 +-
 .../50.vortex/ref/arm/linux/o3-timing/config.ini   |   10 +-
 .../long/50.vortex/ref/arm/linux/o3-timing/simout  |    6 +-
 .../50.vortex/ref/arm/linux/o3-timing/stats.txt    |   19 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   13 +-
 .../50.vortex/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../50.vortex/ref/arm/linux/simple-atomic/simout   |   16 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |   11 +-
 .../50.vortex/ref/arm/linux/simple-timing/simerr   |    1 -
 .../50.vortex/ref/arm/linux/simple-timing/simout   |   16 +-
 .../ref/arm/linux/simple-timing/stats.txt          |  475 ++---
 .../ref/sparc/linux/simple-atomic/config.ini       |   12 +-
 .../50.vortex/ref/sparc/linux/simple-atomic/simout |    6 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   10 +-
 .../50.vortex/ref/sparc/linux/simple-timing/simout |    6 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   19 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |   10 +-
 .../60.bzip2/ref/alpha/tru64/inorder-timing/simout |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   19 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini  |    8 +-
 .../long/60.bzip2/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt   |   19 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../60.bzip2/ref/alpha/tru64/simple-atomic/simout  |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   19 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../60.bzip2/ref/alpha/tru64/simple-timing/simout  |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   19 +-
 .../60.bzip2/ref/arm/linux/o3-timing/config.ini    |   10 +-
 tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |    6 +-
 .../60.bzip2/ref/arm/linux/o3-timing/stats.txt     |   19 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   13 +-
 .../60.bzip2/ref/arm/linux/simple-atomic/simerr    |    1 -
 .../60.bzip2/ref/arm/linux/simple-atomic/simout    |   16 +-
 .../60.bzip2/ref/arm/linux/simple-atomic/stats.txt |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |   11 +-
 .../60.bzip2/ref/arm/linux/simple-timing/simerr    |    1 -
 .../60.bzip2/ref/arm/linux/simple-timing/simout    |   16 +-
 .../60.bzip2/ref/arm/linux/simple-timing/stats.txt |  475 ++---
 .../ref/x86/linux/simple-atomic/config.ini         |   12 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/simout    |    8 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt |   19 +-
 .../ref/x86/linux/simple-timing/config.ini         |   10 +-
 .../60.bzip2/ref/x86/linux/simple-timing/simout    |    8 +-
 .../60.bzip2/ref/x86/linux/simple-timing/stats.txt |   19 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |   10 +-
 .../70.twolf/ref/alpha/tru64/inorder-timing/simout |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   18 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/config.ini  |    8 +-
 .../long/70.twolf/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt   |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   13 +-
 .../70.twolf/ref/alpha/tru64/simple-atomic/simout  |   12 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   19 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   11 +-
 .../70.twolf/ref/alpha/tru64/simple-timing/simout  |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   18 +-
 .../70.twolf/ref/arm/linux/o3-timing/config.ini    |   10 +-
 tests/long/70.twolf/ref/arm/linux/o3-timing/simout |    6 +-
 .../70.twolf/ref/arm/linux/o3-timing/stats.txt     |   18 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   13 +-
 .../70.twolf/ref/arm/linux/simple-atomic/simerr    |    1 -
 .../70.twolf/ref/arm/linux/simple-atomic/simout    |   20 +-
 .../70.twolf/ref/arm/linux/simple-atomic/stats.txt |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |   11 +-
 .../70.twolf/ref/arm/linux/simple-timing/simerr    |    1 -
 .../70.twolf/ref/arm/linux/simple-timing/simout    |   20 +-
 .../70.twolf/ref/arm/linux/simple-timing/stats.txt |  474 ++---
 .../ref/sparc/linux/simple-atomic/config.ini       |   12 +-
 .../70.twolf/ref/sparc/linux/simple-atomic/simout  |   10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   10 +-
 .../70.twolf/ref/sparc/linux/simple-timing/simout  |   10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   18 +-
 .../70.twolf/ref/x86/linux/o3-timing/config.ini    |   10 +-
 tests/long/70.twolf/ref/x86/linux/o3-timing/simout |    8 +-
 .../70.twolf/ref/x86/linux/o3-timing/stats.txt     |   18 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   12 +-
 .../70.twolf/ref/x86/linux/simple-atomic/simout    |    8 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |   19 +-
 .../ref/x86/linux/simple-timing/config.ini         |   10 +-
 .../70.twolf/ref/x86/linux/simple-timing/simout    |    8 +-
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |   18 +-
 .../sparc/solaris/t1000-simple-atomic/config.ini   |   25 +-
 .../ref/sparc/solaris/t1000-simple-atomic/simout   |    8 +-
 .../sparc/solaris/t1000-simple-atomic/stats.txt    |   63 +-
 .../ref/alpha/linux/inorder-timing/config.ini      |   10 +-
 .../00.hello/ref/alpha/linux/inorder-timing/simout |    6 +-
 .../ref/alpha/linux/inorder-timing/stats.txt       |   18 +-
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  |    8 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout      |    4 +-
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   |   18 +-
 .../ref/alpha/linux/simple-atomic/config.ini       |   11 +-
 .../00.hello/ref/alpha/linux/simple-atomic/simout  |    8 +-
 .../ref/alpha/linux/simple-atomic/stats.txt        |   19 +-
 .../config.ini                                     |   72 +-
 .../ruby.stats                                     |   59 +-
 .../simple-timing-ruby-MESI_CMP_directory/simerr   |    1 -
 .../simple-timing-ruby-MESI_CMP_directory/simout   |   16 +-
 .../stats.txt                                      |   89 +-
 .../config.ini                                     |   72 +-
 .../ruby.stats                                     |   35 +-
 .../simple-timing-ruby-MOESI_CMP_directory/simerr  |    1 -
 .../simple-timing-ruby-MOESI_CMP_directory/simout  |   16 +-
 .../stats.txt                                      |   89 +-
 .../simple-timing-ruby-MOESI_CMP_token/config.ini  |   72 +-
 .../simple-timing-ruby-MOESI_CMP_token/ruby.stats  |   27 +-
 .../simple-timing-ruby-MOESI_CMP_token/simerr      |    1 -
 .../simple-timing-ruby-MOESI_CMP_token/simout      |   16 +-
 .../simple-timing-ruby-MOESI_CMP_token/stats.txt   |   89 +-
 .../simple-timing-ruby-MOESI_hammer/config.ini     |   21 +-
 .../simple-timing-ruby-MOESI_hammer/ruby.stats     |   24 +-
 .../linux/simple-timing-ruby-MOESI_hammer/simout   |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt      |   19 +-
 .../ref/alpha/linux/simple-timing-ruby/config.ini  |   87 +-
 .../ref/alpha/linux/simple-timing-ruby/ruby.stats  |   47 +-
 .../ref/alpha/linux/simple-timing-ruby/simerr      |    1 -
 .../ref/alpha/linux/simple-timing-ruby/simout      |   16 +-
 .../ref/alpha/linux/simple-timing-ruby/stats.txt   |   89 +-
 .../ref/alpha/linux/simple-timing/config.ini       |    9 +-
 .../00.hello/ref/alpha/linux/simple-timing/simout  |    8 +-
 .../ref/alpha/linux/simple-timing/stats.txt        |   18 +-
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  |    8 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout      |    4 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   11 +-
 .../00.hello/ref/alpha/tru64/simple-atomic/simerr  |    2 -
 .../00.hello/ref/alpha/tru64/simple-atomic/simout  |   16 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   89 +-
 .../config.ini                                     |   72 +-
 .../ruby.stats                                     |   55 +-
 .../simple-timing-ruby-MESI_CMP_directory/simerr   |    2 -
 .../simple-timing-ruby-MESI_CMP_directory/simout   |   16 +-
 .../stats.txt                                      |   89 +-
 .../config.ini                                     |   72 +-
 .../ruby.stats                                     |   27 +-
 .../simple-timing-ruby-MOESI_CMP_directory/simerr  |    2 -
 .../simple-timing-ruby-MOESI_CMP_directory/simout  |   16 +-
 .../stats.txt                                      |   89 +-
 .../simple-timing-ruby-MOESI_CMP_token/config.ini  |   72 +-
 .../simple-timing-ruby-MOESI_CMP_token/ruby.stats  |   35 +-
 .../simple-timing-ruby-MOESI_CMP_token/simerr      |    2 -
 .../simple-timing-ruby-MOESI_CMP_token/simout      |   16 +-
 .../simple-timing-ruby-MOESI_CMP_token/stats.txt   |   89 +-
 .../simple-timing-ruby-MOESI_hammer/config.ini     |   21 +-
 .../simple-timing-ruby-MOESI_hammer/ruby.stats     |   20 +-
 .../tru64/simple-timing-ruby-MOESI_hammer/simout   |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt      |   19 +-
 .../ref/alpha/tru64/simple-timing-ruby/config.ini  |   87 +-
 .../ref/alpha/tru64/simple-timing-ruby/ruby.stats  |   47 +-
 .../ref/alpha/tru64/simple-timing-ruby/simerr      |    2 -
 .../ref/alpha/tru64/simple-timing-ruby/simout      |   16 +-
 .../ref/alpha/tru64/simple-timing-ruby/stats.txt   |   89 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    9 +-
 .../00.hello/ref/alpha/tru64/simple-timing/simerr  |    2 -
 .../00.hello/ref/alpha/tru64/simple-timing/simout  |   16 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  436 +++--
 .../00.hello/ref/arm/linux/o3-timing/config.ini    |   10 +-
 .../quick/00.hello/ref/arm/linux/o3-timing/simout  |    6 +-
 .../00.hello/ref/arm/linux/o3-timing/stats.txt     |   18 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   11 +-
 .../00.hello/ref/arm/linux/simple-atomic/simerr    |    1 -
 .../00.hello/ref/arm/linux/simple-atomic/simout    |   16 +-
 .../00.hello/ref/arm/linux/simple-atomic/stats.txt |  109 +-
 .../ref/arm/linux/simple-timing/config.ini         |    9 +-
 .../00.hello/ref/arm/linux/simple-timing/simerr    |    1 -
 .../00.hello/ref/arm/linux/simple-timing/simout    |   16 +-
 .../00.hello/ref/arm/linux/simple-timing/stats.txt |  466 ++---
 .../ref/mips/linux/inorder-timing/config.ini       |    8 +-
 .../00.hello/ref/mips/linux/inorder-timing/simout  |    4 +-
 .../ref/mips/linux/inorder-timing/stats.txt        |   18 +-
 .../00.hello/ref/mips/linux/o3-timing/config.ini   |    8 +-
 .../quick/00.hello/ref/mips/linux/o3-timing/simout |    4 +-
 .../00.hello/ref/mips/linux/o3-timing/stats.txt    |   18 +-
 .../ref/mips/linux/simple-atomic/config.ini        |   10 +-
 .../00.hello/ref/mips/linux/simple-atomic/simout   |    4 +-
 .../ref/mips/linux/simple-atomic/stats.txt         |   19 +-
 .../ref/mips/linux/simple-timing-ruby/config.ini   |   21 +-
 .../ref/mips/linux/simple-timing-ruby/simout       |    4 +-
 .../ref/mips/linux/simple-timing-ruby/stats.txt    |   19 +-
 .../ref/mips/linux/simple-timing/config.ini        |    8 +-
 .../00.hello/ref/mips/linux/simple-timing/simout   |    4 +-
 .../ref/mips/linux/simple-timing/stats.txt         |   18 +-
 .../00.hello/ref/power/linux/o3-timing/config.ini  |   11 +-
 .../00.hello/ref/power/linux/o3-timing/simout      |    6 +-
 .../00.hello/ref/power/linux/o3-timing/stats.txt   |   18 +-
 .../ref/power/linux/simple-atomic/config.ini       |   11 +-
 .../00.hello/ref/power/linux/simple-atomic/simerr  |    3 -
 .../00.hello/ref/power/linux/simple-atomic/simout  |   16 +-
 .../ref/power/linux/simple-atomic/stats.txt        |   69 +-
 .../ref/sparc/linux/inorder-timing/config.ini      |   10 +-
 .../00.hello/ref/sparc/linux/inorder-timing/simout |    6 +-
 .../ref/sparc/linux/inorder-timing/stats.txt       |   18 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   11 +-
 .../00.hello/ref/sparc/linux/simple-atomic/simerr  |    1 -
 .../00.hello/ref/sparc/linux/simple-atomic/simout  |   16 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   19 +-
 .../ref/sparc/linux/simple-timing-ruby/config.ini  |  138 +-
 .../ref/sparc/linux/simple-timing-ruby/ruby.stats  |   71 +-
 .../ref/sparc/linux/simple-timing-ruby/simerr      |    1 -
 .../ref/sparc/linux/simple-timing-ruby/simout      |   16 +-
 .../ref/sparc/linux/simple-timing-ruby/stats.txt   |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |    9 +-
 .../00.hello/ref/sparc/linux/simple-timing/simerr  |    1 -
 .../00.hello/ref/sparc/linux/simple-timing/simout  |   16 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   18 +-
 .../00.hello/ref/x86/linux/o3-timing/config.ini    |   10 +-
 .../quick/00.hello/ref/x86/linux/o3-timing/simout  |    8 +-
 .../00.hello/ref/x86/linux/o3-timing/stats.txt     |   18 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   12 +-
 .../00.hello/ref/x86/linux/simple-atomic/simout    |    8 +-
 .../00.hello/ref/x86/linux/simple-atomic/stats.txt |   19 +-
 .../ref/x86/linux/simple-timing-ruby/config.ini    |   22 +-
 .../ref/x86/linux/simple-timing-ruby/ruby.stats    |   32 +-
 .../ref/x86/linux/simple-timing-ruby/simout        |    8 +-
 .../ref/x86/linux/simple-timing-ruby/stats.txt     |   19 +-
 .../ref/x86/linux/simple-timing/config.ini         |   10 +-
 .../00.hello/ref/x86/linux/simple-timing/simout    |    8 +-
 .../00.hello/ref/x86/linux/simple-timing/stats.txt |   18 +-
 .../ref/alpha/linux/o3-timing/config.ini           |    8 +-
 .../ref/alpha/linux/o3-timing/simout               |    4 +-
 .../ref/alpha/linux/o3-timing/stats.txt            |   18 +-
 .../ref/sparc/linux/inorder-timing/config.ini      |   10 +-
 .../ref/sparc/linux/inorder-timing/simout          |    6 +-
 .../ref/sparc/linux/inorder-timing/stats.txt       |   18 +-
 .../ref/sparc/linux/o3-timing/config.ini           |    8 +-
 .../02.insttest/ref/sparc/linux/o3-timing/simout   |    6 +-
 .../ref/sparc/linux/o3-timing/stats.txt            |   18 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   11 +-
 .../ref/sparc/linux/simple-atomic/simerr           |    1 -
 .../ref/sparc/linux/simple-atomic/simout           |   16 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   19 +-
 .../ref/sparc/linux/simple-timing/config.ini       |    9 +-
 .../ref/sparc/linux/simple-timing/simerr           |    1 -
 .../ref/sparc/linux/simple-timing/simout           |   16 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   18 +-
 .../linux/tsunami-simple-atomic-dual/config.ini    |   56 +-
 .../alpha/linux/tsunami-simple-atomic-dual/simerr  |    8 +-
 .../alpha/linux/tsunami-simple-atomic-dual/simout  |   17 +-
 .../linux/tsunami-simple-atomic-dual/stats.txt     | 1681 ++++++++--------
 .../alpha/linux/tsunami-simple-atomic/config.ini   |   56 +-
 .../ref/alpha/linux/tsunami-simple-atomic/simerr   |    8 +-
 .../ref/alpha/linux/tsunami-simple-atomic/simout   |   17 +-
 .../alpha/linux/tsunami-simple-atomic/stats.txt    |  965 +++++-----
 .../linux/tsunami-simple-timing-dual/config.ini    |   56 +-
 .../alpha/linux/tsunami-simple-timing-dual/simerr  |    8 +-
 .../alpha/linux/tsunami-simple-timing-dual/simout  |   17 +-
 .../linux/tsunami-simple-timing-dual/stats.txt     | 2033 ++++++++++----------
 .../alpha/linux/tsunami-simple-timing/config.ini   |   56 +-
 .../ref/alpha/linux/tsunami-simple-timing/simerr   |    8 +-
 .../ref/alpha/linux/tsunami-simple-timing/simout   |   17 +-
 .../alpha/linux/tsunami-simple-timing/stats.txt    | 1207 ++++++------
 .../linux/realview-simple-atomic-dual/config.ini   |   78 +-
 .../arm/linux/realview-simple-atomic-dual/simout   |    8 +-
 .../linux/realview-simple-atomic-dual/stats.txt    |   28 +-
 .../arm/linux/realview-simple-atomic/config.ini    |   76 +-
 .../ref/arm/linux/realview-simple-atomic/simout    |    8 +-
 .../ref/arm/linux/realview-simple-atomic/stats.txt |   28 +-
 .../linux/realview-simple-timing-dual/config.ini   |   78 +-
 .../arm/linux/realview-simple-timing-dual/simout   |    8 +-
 .../linux/realview-simple-timing-dual/stats.txt    |   28 +-
 .../arm/linux/realview-simple-timing/config.ini    |   76 +-
 .../ref/arm/linux/realview-simple-timing/simout    |    8 +-
 .../ref/arm/linux/realview-simple-timing/stats.txt |   28 +-
 .../ref/x86/linux/pc-simple-atomic/config.ini      |   85 +-
 .../ref/x86/linux/pc-simple-atomic/simout          |   11 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt       |   19 +-
 .../ref/x86/linux/pc-simple-timing/config.ini      |   85 +-
 .../ref/x86/linux/pc-simple-timing/simout          |   11 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt       |   19 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini        |    6 +-
 .../ref/sparc/linux/o3-timing-mp/simout            |    6 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt         |   18 +-
 .../ref/sparc/linux/simple-atomic-mp/config.ini    |    5 +-
 .../ref/sparc/linux/simple-atomic-mp/simerr        |    1 -
 .../ref/sparc/linux/simple-atomic-mp/simout        |   16 +-
 .../ref/sparc/linux/simple-atomic-mp/stats.txt     |   18 +-
 .../ref/sparc/linux/simple-timing-mp/config.ini    |    9 +-
 .../ref/sparc/linux/simple-timing-mp/simerr        |    1 -
 .../ref/sparc/linux/simple-timing-mp/simout        |   16 +-
 .../ref/sparc/linux/simple-timing-mp/stats.txt     |   18 +-
 .../memtest-ruby-MESI_CMP_directory/config.ini     |   38 +-
 .../memtest-ruby-MESI_CMP_directory/ruby.stats     |  105 +-
 .../linux/memtest-ruby-MESI_CMP_directory/simout   |    6 +-
 .../memtest-ruby-MESI_CMP_directory/stats.txt      |   19 +-
 .../memtest-ruby-MOESI_CMP_directory/config.ini    |   38 +-
 .../memtest-ruby-MOESI_CMP_directory/ruby.stats    |   33 +-
 .../linux/memtest-ruby-MOESI_CMP_directory/simout  |    6 +-
 .../memtest-ruby-MOESI_CMP_directory/stats.txt     |   19 +-
 .../linux/memtest-ruby-MOESI_CMP_token/config.ini  |   38 +-
 .../linux/memtest-ruby-MOESI_CMP_token/ruby.stats  |   33 +-
 .../linux/memtest-ruby-MOESI_CMP_token/simout      |    6 +-
 .../linux/memtest-ruby-MOESI_CMP_token/stats.txt   |   19 +-
 .../linux/memtest-ruby-MOESI_hammer/config.ini     |   19 +-
 .../linux/memtest-ruby-MOESI_hammer/ruby.stats     |  814 ++++----
 .../alpha/linux/memtest-ruby-MOESI_hammer/simerr   |  146 +-
 .../alpha/linux/memtest-ruby-MOESI_hammer/simout   |   12 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt      |   19 +-
 .../ref/alpha/linux/memtest-ruby/config.ini        |   29 +-
 .../ref/alpha/linux/memtest-ruby/ruby.stats        |   37 +-
 .../50.memtest/ref/alpha/linux/memtest-ruby/simout |    6 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt         |   19 +-
 .../50.memtest/ref/alpha/linux/memtest/config.ini  |   15 +-
 .../50.memtest/ref/alpha/linux/memtest/simerr      |  146 +-
 .../50.memtest/ref/alpha/linux/memtest/simout      |   16 +-
 .../50.memtest/ref/alpha/linux/memtest/stats.txt   | 1742 ++++++++---------
 .../rubytest-ruby-MESI_CMP_directory/config.ini    |   68 +-
 .../rubytest-ruby-MESI_CMP_directory/ruby.stats    |   47 +-
 .../linux/rubytest-ruby-MESI_CMP_directory/simout  |   16 +-
 .../rubytest-ruby-MESI_CMP_directory/stats.txt     |   15 +-
 .../rubytest-ruby-MOESI_CMP_directory/config.ini   |   68 +-
 .../rubytest-ruby-MOESI_CMP_directory/ruby.stats   |   23 +-
 .../linux/rubytest-ruby-MOESI_CMP_directory/simout |   16 +-
 .../rubytest-ruby-MOESI_CMP_directory/stats.txt    |   15 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/config.ini |   68 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/ruby.stats |   31 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/simout     |   16 +-
 .../linux/rubytest-ruby-MOESI_CMP_token/stats.txt  |   15 +-
 .../linux/rubytest-ruby-MOESI_hammer/config.ini    |   19 +-
 .../linux/rubytest-ruby-MOESI_hammer/ruby.stats    |   20 +-
 .../alpha/linux/rubytest-ruby-MOESI_hammer/simout  |   10 +-
 .../linux/rubytest-ruby-MOESI_hammer/stats.txt     |   13 +-
 .../ref/alpha/linux/rubytest-ruby/config.ini       |   83 +-
 .../ref/alpha/linux/rubytest-ruby/ruby.stats       |   43 +-
 .../ref/alpha/linux/rubytest-ruby/simout           |   16 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt        |   15 +-
 .../linux/twosys-tsunami-simple-atomic/config.ini  |  138 +-
 .../linux/twosys-tsunami-simple-atomic/simerr      |    9 +-
 .../linux/twosys-tsunami-simple-atomic/simout      |   18 +-
 .../linux/twosys-tsunami-simple-atomic/stats.txt   | 1016 +++++-----
 490 files changed, 13489 insertions(+), 11321 deletions(-)

(limited to 'tests')

diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index b6c1d1a1d..6c1c0e974 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 9da502021..30b31a527 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:09:24
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index ec1428295..b5662ac02 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.274500                       # Number of seconds simulated
 sim_ticks                                274500333500                       # Number of ticks simulated
+final_tick                               274500333500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56944                       # Simulator instruction rate (inst/s)
-host_tick_rate                               25971361                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245756                       # Number of bytes of host memory used
-host_seconds                                 10569.35                       # Real time elapsed on the host
+host_inst_rate                                 113367                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51705325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207980                       # Number of bytes of host memory used
+host_seconds                                  5308.94                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                     5894016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  54720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3798080                       # Number of bytes written to this memory
+system.physmem.num_reads                        92094                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59345                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       21471799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    199344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      13836340                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35308139                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index b11fadb7f..cc9b0c683 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 9acd0ed7e..ad1c408b1 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index bcb696265..8681db468 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.144450                       # Number of seconds simulated
 sim_ticks                                144450185500                       # Number of ticks simulated
+final_tick                               144450185500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180758                       # Simulator instruction rate (inst/s)
-host_tick_rate                               46168195                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205240                       # Number of bytes of host memory used
-host_seconds                                  3128.78                       # Real time elapsed on the host
+host_inst_rate                                 205040                       # Simulator instruction rate (inst/s)
+host_tick_rate                               52370107                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208620                       # Number of bytes of host memory used
+host_seconds                                  2758.26                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
+system.physmem.bytes_read                     5936768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  60416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3797120                       # Number of bytes written to this memory
+system.physmem.num_reads                        92762                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59330                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       41099068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    418248                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      26286709                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      67385777                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 355960d42..282141772 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 7ce6e1e9f..1dc402141 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:20:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index b2d2b0068..ad4f39b85 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.300931                       # Number of seconds simulated
 sim_ticks                                300930958000                       # Number of ticks simulated
+final_tick                               300930958000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3663682                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1831855621                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 184012                       # Number of bytes of host memory used
-host_seconds                                   164.28                       # Real time elapsed on the host
+host_inst_rate                                4527143                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2263589972                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 198960                       # Number of bytes of host memory used
+host_seconds                                   132.94                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                  2782990928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2407447588                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                152669504                       # Number of bytes written to this memory
+system.physmem.num_reads                    716375939                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    39451321                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9247938286                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999747                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     507324022                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9755262308                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 50ef6266f..0bc5277c7 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 26ae974dd..36bd68fb7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:47:45
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 9bcf790a8..4d7850adf 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.765623                       # Number of seconds simulated
 sim_ticks                                765623032000                       # Number of ticks simulated
+final_tick                               765623032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1640067                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2086331180                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 192652                       # Number of bytes of host memory used
-host_seconds                                   366.97                       # Real time elapsed on the host
+host_inst_rate                                2199350                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2797795440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207676                       # Number of bytes of host memory used
+host_seconds                                   273.65                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                     5889984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  50880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3797824                       # Number of bytes written to this memory
+system.physmem.num_reads                        92031                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59341                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7693060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     66456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4960436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      12653496                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index 158bcba97..9f24d0367 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index c90a30371..d3786fda6 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 16:59:04
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:31:06
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 7a98c6c82..5022d17a1 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.177099                       # Number of seconds simulated
 sim_ticks                                177098873000                       # Number of ticks simulated
+final_tick                               177098873000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 166594                       # Simulator instruction rate (inst/s)
-host_tick_rate                               48979898                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214636                       # Number of bytes of host memory used
-host_seconds                                  3615.75                       # Real time elapsed on the host
+host_inst_rate                                 154897                       # Simulator instruction rate (inst/s)
+host_tick_rate                               45541130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220436                       # Number of bytes of host memory used
+host_seconds                                  3888.77                       # Real time elapsed on the host
 sim_insts                                   602359805                       # Number of instructions simulated
+system.physmem.bytes_read                     5833856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  46976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3720192                       # Number of bytes written to this memory
+system.physmem.num_reads                        91154                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58128                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       32941237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    265253                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      21006300                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      53947537                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 17d38a039..8c7671d34 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index ceb1053f2..95da0efca 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:47:58
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:36:54
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index 2dd995d75..f48dc3640 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2791643                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 253504                       # Number of bytes of host memory used
-host_seconds                                   215.77                       # Real time elapsed on the host
-host_tick_rate                             1395873441                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   602359851                       # Number of instructions simulated
 sim_seconds                                  0.301191                       # Number of seconds simulated
 sim_ticks                                301191370000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               301191370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2998309                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1499211130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210136                       # Number of bytes of host memory used
+host_seconds                                   200.90                       # Real time elapsed on the host
+sim_insts                                   602359851                       # Number of instructions simulated
+system.physmem.bytes_read                  2680160157                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2280298136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                236359611                       # Number of bytes written to this memory
+system.physmem.num_reads                    717867713                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    69418858                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8898529055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7570927866                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     784748949                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9683278004                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 system.cpu.numCycles                        602382741                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  602382741                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        602359851                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_int_register_reads          2770243005                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          614470985                       # number of times the integer registers were written
-system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     219173607                       # number of memory refs
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
-system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  602382741                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index f2a118cfd..6a1e2b970 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 99cb1ccc7..589b03862 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:48:29
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:40:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index ba03a3195..3846f97fb 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1298278                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260992                       # Number of bytes of host memory used
-host_seconds                                   462.46                       # Real time elapsed on the host
-host_tick_rate                             1722888732                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   600398281                       # Number of instructions simulated
 sim_seconds                                  0.796763                       # Number of seconds simulated
 sim_ticks                                796762926000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses         1327                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits             1327                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          147791852                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              147602036                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     3956274000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001284                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               189816                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3386826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001284                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          189816                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses          1327                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits              1327                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              69169783                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5180170000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 495.412038                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           217209383                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22578.841038                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               216771819                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      9879688000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002014                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                437564                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   8566996000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002014                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           437564                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999566                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              216771819                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     9879688000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002014                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               437564                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   8566996000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002014                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          437564                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 433468                       # number of replacements
-system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.222434                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                216774473                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              537031000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   392392                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               796762926000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1450316                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1924652930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219100                       # Number of bytes of host memory used
+host_seconds                                   413.98                       # Real time elapsed on the host
+sim_insts                                   600398281                       # Number of instructions simulated
+system.physmem.bytes_read                     5759488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3704704                       # Number of bytes written to this memory
+system.physmem.num_reads                        89992                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       57886                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7228609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     49480                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4649694                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      11878304                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          570074535                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54236.391913                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       1593525852                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        600398281                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          3212467108                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          614470985                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     219173607                       # number of memory refs
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_store_insts                   70221013                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1593525852                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     12                       # number of replacements
+system.cpu.icache.tagsinuse                577.728532                       # Cycle average of tags in use
+system.cpu.icache.total_refs                570073892                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               886584.590980                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.282094                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              570073892                       # number of ReadReq hits
+system.cpu.icache.demand_hits               570073892                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              570073892                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  643                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   643                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  643                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency       34874000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        34874000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       34874000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          570074535                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           570074535                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  643                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     32945000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             643                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               886584.590980                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54236.391913                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54236.391913                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           570074535                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54236.391913                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               570073892                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        34874000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   643                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             643                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              643                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             643                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     32945000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency     32945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     32945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              643                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.282094                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              570073892                       # number of overall hits
-system.cpu.icache.overall_miss_latency       34874000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  643                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     32945000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             643                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     12                       # number of replacements
-system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                577.728532                       # Cycle average of tags in use
-system.cpu.icache.total_refs                570073892                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          247748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 433468                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.222434                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                216774473                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 495.412038                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              537031000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999566                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              147602036                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              69169783                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             1327                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              1327                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               216771819                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              216771819                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               189816                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                437564                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               437564                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     3956274000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      9879688000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9879688000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          147791852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         1327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          1327                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           217209383                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001284                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002014                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002014                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   392392                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          189816                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           437564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          437564                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3386826000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5180170000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   8566996000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   8566996000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001284                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002014                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002014                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 71804                       # number of replacements
+system.cpu.l2cache.tagsinuse             17904.014680                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  411836                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 87286                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.718237                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.053777                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.492610                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                158918                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              392392                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits              189297                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3039452000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.235929                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                 348215                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                348215                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31541                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses             58451                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            190459                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                158918                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses                89992                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               89992                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency    1640132000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.165605                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               31541                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1261640000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165605                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          31541                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency   3039452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4679584000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4679584000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            190459                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses          392392                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              392392                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.718237                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses          247748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             438207                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165605                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235929                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.205364                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.205364                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             438207                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 348215                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     4679584000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.205364                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                89992                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   57886                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31541                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           89992                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          89992                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1261640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency   3599680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3599680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.205364                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           89992                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.053777                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.492610                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.205364                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                348215                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    4679584000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.205364                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               89992                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   3599680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.205364                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          89992                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 71804                       # number of replacements
-system.cpu.l2cache.sampled_refs                 87286                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17904.014680                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  411836                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   57886                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1593525852                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1593525852                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        600398281                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
-system.cpu.num_int_insts                    533522639                       # number of integer instructions
-system.cpu.num_int_register_reads          3212467108                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          614470985                       # number of times the integer registers were written
-system.cpu.num_load_insts                   148952594                       # Number of load instructions
-system.cpu.num_mem_refs                     219173607                       # number of memory refs
-system.cpu.num_store_insts                   70221013                       # Number of store instructions
-system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index f1874f64f..dcba73ec2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -495,7 +497,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index df0fa130a..a835cbd79 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:17:40
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 8c5bfcb3c..e4d9fca07 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.408816                       # Number of seconds simulated
 sim_ticks                                408816360000                       # Number of ticks simulated
+final_tick                               408816360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 252046                       # Simulator instruction rate (inst/s)
-host_tick_rate                               73306837                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206388                       # Number of bytes of host memory used
-host_seconds                                  5576.78                       # Real time elapsed on the host
+host_inst_rate                                 175830                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51139829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215728                       # Number of bytes of host memory used
+host_seconds                                  7994.10                       # Real time elapsed on the host
 sim_insts                                  1405604152                       # Number of instructions simulated
+system.physmem.bytes_read                     6021376                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  81792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3792448                       # Number of bytes written to this memory
+system.physmem.num_reads                        94084                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59257                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       14728804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    200070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       9276654                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      24005458                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
 system.cpu.numCycles                        817632721                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 864c2771b..b52495d06 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index 3eb09159b..d2df5cc09 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:18:03
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index ae12e23e4..afe2bae4f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.744764                       # Number of seconds simulated
 sim_ticks                                744764119000                       # Number of ticks simulated
+final_tick                               744764119000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4241689                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2120851440                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 196528                       # Number of bytes of host memory used
-host_seconds                                   351.16                       # Real time elapsed on the host
+host_inst_rate                                3773289                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1886650577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205844                       # Number of bytes of host memory used
+host_seconds                                   394.75                       # Real time elapsed on the host
 sim_insts                                  1489523295                       # Number of instructions simulated
+system.physmem.bytes_read                  7326269637                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             5940452044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                614672063                       # Number of bytes written to this memory
+system.physmem.num_reads                   1887625855                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   166846816                       # Number of write requests responded to by this memory
+system.physmem.num_other                         1326                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9837033566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7976286575                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     825324485                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10662358051                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
 system.cpu.numCycles                       1489528239                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 6dbddf888..ea98a23a1 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 4a77ef60d..b26fb3f41 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:19:05
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index d75fccee8..059312926 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.064259                       # Number of seconds simulated
 sim_ticks                                2064258667000                       # Number of ticks simulated
+final_tick                               2064258667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2284016                       # Simulator instruction rate (inst/s)
-host_tick_rate                             3165307188                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205232                       # Number of bytes of host memory used
-host_seconds                                   652.15                       # Real time elapsed on the host
+host_inst_rate                                1766930                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2448703239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214556                       # Number of bytes of host memory used
+host_seconds                                   843.00                       # Real time elapsed on the host
 sim_insts                                  1489523295                       # Number of instructions simulated
+system.physmem.bytes_read                     5909952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  70592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3778240                       # Number of bytes written to this memory
+system.physmem.num_reads                        92343                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59035                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2862990                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     34197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1830313                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       4693303                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
 system.cpu.numCycles                       4128517334                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index c626036a3..42f7aa66f 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index d3f649818..48ae315a0 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:28:24
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 9655899ee..802bd6f5d 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.586294                       # Number of seconds simulated
 sim_ticks                                586294224000                       # Number of ticks simulated
+final_tick                               586294224000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115446                       # Simulator instruction rate (inst/s)
-host_tick_rate                               41742717                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244900                       # Number of bytes of host memory used
-host_seconds                                 14045.43                       # Real time elapsed on the host
+host_inst_rate                                 145094                       # Simulator instruction rate (inst/s)
+host_tick_rate                               52462700                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215548                       # Number of bytes of host memory used
+host_seconds                                 11175.48                       # Real time elapsed on the host
 sim_insts                                  1621493982                       # Number of instructions simulated
+system.physmem.bytes_read                     5880640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  56960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3744192                       # Number of bytes written to this memory
+system.physmem.num_reads                        91885                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58503                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       10030186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     97153                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       6386200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      16416386                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
 system.cpu.numCycles                       1172588449                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index dd4d7f0aa..393d71365 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,7 +69,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 510b69206..3da3c7641 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:33:19
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index a5e9437b0..3a54bb2c8 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.963993                       # Number of seconds simulated
 sim_ticks                                963992704000                       # Number of ticks simulated
+final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1220339                       # Simulator instruction rate (inst/s)
-host_tick_rate                              725502264                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234168                       # Number of bytes of host memory used
-host_seconds                                  1328.72                       # Real time elapsed on the host
+host_inst_rate                                2202720                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1309536712                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204800                       # Number of bytes of host memory used
+host_seconds                                   736.13                       # Real time elapsed on the host
 sim_insts                                  1621493983                       # Number of instructions simulated
+system.physmem.bytes_read                 11334586825                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             9492133912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                864451000                       # Number of bytes written to this memory
+system.physmem.num_reads                   1605558864                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   188186057                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11757959140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                9846686466                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     896740189                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12654699330                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
 system.cpu.numCycles                       1927985409                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 129642a98..f841786ec 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,7 +172,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 613f79639..c3d33da65 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:37:10
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 5aedfb687..8e512b7b9 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.803259                       # Number of seconds simulated
 sim_ticks                                1803258587000                       # Number of ticks simulated
+final_tick                               1803258587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 760773                       # Simulator instruction rate (inst/s)
-host_tick_rate                              846053445                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242892                       # Number of bytes of host memory used
-host_seconds                                  2131.38                       # Real time elapsed on the host
+host_inst_rate                                1279975                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1423455894                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213784                       # Number of bytes of host memory used
+host_seconds                                  1266.82                       # Real time elapsed on the host
 sim_insts                                  1621493983                       # Number of instructions simulated
+system.physmem.bytes_read                     5725952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  46208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3712448                       # Number of bytes written to this memory
+system.physmem.num_reads                        89468                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58007                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3175336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     25625                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2058744                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5234080                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
 system.cpu.numCycles                       3606517174                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 78fc12019..94bfc8925 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -10,13 +10,14 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/projects/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu0]
 type=DerivO3CPU
@@ -933,7 +932,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -953,7 +952,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -969,7 +968,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -1000,8 +999,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -1033,7 +1032,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -1045,7 +1044,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -1082,7 +1081,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -1195,9 +1194,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1583,8 +1582,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index cb23e1c15..35f0311de 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:05:33
-gem5 started Nov 21 2011 19:03:16
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:48
+gem5 executing on zizzer
 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 106949500
 Exiting @ tick 1897465263500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 65d49a60e..d2e784a3f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.897465                       # Number of seconds simulated
 sim_ticks                                1897465263500                       # Number of ticks simulated
+final_tick                               1897465263500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 138767                       # Simulator instruction rate (inst/s)
-host_tick_rate                             4690907118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293696                       # Number of bytes of host memory used
-host_seconds                                   404.50                       # Real time elapsed on the host
+host_inst_rate                                 131690                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4451680142                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298548                       # Number of bytes of host memory used
+host_seconds                                   426.24                       # Real time elapsed on the host
 sim_insts                                    56130966                       # Number of instructions simulated
+system.physmem.bytes_read                    30408320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1097728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10468544                       # Number of bytes written to this memory
+system.physmem.num_reads                       475130                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      163571                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       16025758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    578523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5517120                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      21542879                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        397795                       # number of replacements
 system.l2c.tagsinuse                     35116.884908                       # Cycle average of tags in use
 system.l2c.total_refs                         2482671                       # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index c437d8a70..b0a37466e 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -10,13 +10,14 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/projects/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -497,7 +496,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -517,7 +516,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -533,7 +532,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -564,8 +563,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -597,7 +596,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -609,7 +608,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -646,7 +645,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -759,9 +758,9 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1147,8 +1146,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index b8893b11f..2911b29fc 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:05:33
-gem5 started Nov 21 2011 18:56:50
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:15
+gem5 executing on zizzer
 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1858873594500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 16f374a0c..de8941321 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.858874                       # Number of seconds simulated
 sim_ticks                                1858873594500                       # Number of ticks simulated
+final_tick                               1858873594500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 141632                       # Simulator instruction rate (inst/s)
-host_tick_rate                             4958330764                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290572                       # Number of bytes of host memory used
-host_seconds                                   374.90                       # Real time elapsed on the host
+host_inst_rate                                 134152                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4696460042                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295432                       # Number of bytes of host memory used
+host_seconds                                   395.80                       # Real time elapsed on the host
 sim_insts                                    53097697                       # Number of instructions simulated
+system.physmem.bytes_read                    29819840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1062784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10193408                       # Number of bytes written to this memory
+system.physmem.num_reads                       465935                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      159272                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       16041887                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    571735                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5483648                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      21525535                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        391354                       # number of replacements
 system.l2c.tagsinuse                     34898.086140                       # Cycle average of tags in use
 system.l2c.total_refs                         2410581                       # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index e6a0de845..6f9417ef5 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -987,7 +985,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -1018,8 +1016,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -1051,7 +1049,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -1063,7 +1061,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -1125,7 +1123,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -1179,9 +1177,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1196,7 +1194,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -1207,7 +1205,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -1224,7 +1222,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -1246,7 +1244,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -1256,7 +1254,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -1266,7 +1264,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -1280,7 +1278,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1294,7 +1292,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1333,7 +1331,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1354,7 +1352,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -1364,7 +1362,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -1374,7 +1372,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -1384,7 +1382,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -1394,7 +1392,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -1445,7 +1443,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -1455,7 +1453,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -1465,7 +1463,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1475,7 +1473,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 13d4b63f2..28da0bb31 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  8 2012 22:12:58
-gem5 started Jan  9 2012 03:33:38
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 09:54:17
 gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 3163bcf32..11b3b4098 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.582494                       # Number of seconds simulated
 sim_ticks                                2582494395500                       # Number of ticks simulated
+final_tick                               2582494395500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65512                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2118472138                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384260                       # Number of bytes of host memory used
-host_seconds                                  1219.04                       # Real time elapsed on the host
+host_inst_rate                                  77486                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2505663009                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 386072                       # Number of bytes of host memory used
+host_seconds                                  1030.66                       # Real time elapsed on the host
 sim_insts                                    79862069                       # Number of instructions simulated
+system.nvmem.bytes_read                           384                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                      384                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                              6                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                              149                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                         149                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                             149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   131490980                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1177856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10251344                       # Number of bytes written to this memory
+system.physmem.num_reads                     15129077                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      870131                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       50916269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    456092                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       3969551                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      54885821                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        132200                       # number of replacements
 system.l2c.tagsinuse                     27582.989225                       # Cycle average of tags in use
 system.l2c.total_refs                         1817822                       # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 0e78591b5..c84a9ea85 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -533,7 +531,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -564,8 +562,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -597,7 +595,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -609,7 +607,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -671,7 +669,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -725,9 +723,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -742,7 +740,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -753,7 +751,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -770,7 +768,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -792,7 +790,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -802,7 +800,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -812,7 +810,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -826,7 +824,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -840,7 +838,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -879,7 +877,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -900,7 +898,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -910,7 +908,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -920,7 +918,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -930,7 +928,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -940,7 +938,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -991,7 +989,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -1001,7 +999,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -1011,7 +1009,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1021,7 +1019,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
index 9d4c8ae86..231dec8b1 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  8 2012 22:12:58
-gem5 started Jan  9 2012 03:32:35
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 09:54:06
 gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 768983a75..ad6b1630f 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.503566                       # Number of seconds simulated
 sim_ticks                                2503566110500                       # Number of ticks simulated
+final_tick                               2503566110500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72389                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2360079964                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384076                       # Number of bytes of host memory used
-host_seconds                                  1060.80                       # Real time elapsed on the host
+host_inst_rate                                  76624                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2498140220                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 386188                       # Number of bytes of host memory used
+host_seconds                                  1002.17                       # Real time elapsed on the host
 sim_insts                                    76790007                       # Number of instructions simulated
+system.nvmem.bytes_read                            64                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                       64                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                              1                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                               26                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                          26                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                              26                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   130731152                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1101568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  9585992                       # Number of bytes written to this memory
+system.physmem.num_reads                     15117140                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      856673                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       52217975                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    440000                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       3828935                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      56046910                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        119509                       # number of replacements
 system.l2c.tagsinuse                     25929.897253                       # Cycle average of tags in use
 system.l2c.total_refs                         1795434                       # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 9ef75afe6..f406247a4 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_cpu_frequency=500
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -31,6 +31,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[3]
 
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
@@ -52,16 +53,13 @@ oem_table_id=
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
+master=system.iobus.port[0]
+slave=system.membus.port[1]
 
 [system.cpu]
 type=DerivO3CPU
@@ -535,8 +533,8 @@ pio_addr=2305843009213693952
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
@@ -947,6 +945,17 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
+[system.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.iobus]
 type=Bus
 block_size=64
@@ -956,7 +965,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -987,8 +996,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[21]
+mem_side=system.membus.port[4]
 
 [system.l2c]
 type=BaseCache
@@ -1020,7 +1029,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[5]
 
 [system.membus]
 type=Bus
@@ -1032,7 +1041,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -1072,7 +1081,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.pc.com_1]
 type=Uart8250
@@ -1082,7 +1091,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -1113,7 +1122,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -1130,7 +1139,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1147,7 +1156,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1164,7 +1173,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.pc.i_dont_exist]
 type=IsaFake
@@ -1181,7 +1190,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.pc.pciconfig]
 type=PciConfigAll
@@ -1215,7 +1224,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[1]
+pio=system.iobus.port[2]
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
@@ -1226,7 +1235,7 @@ pio_addr=9223372036854775808
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[2]
+pio=system.iobus.port[3]
 
 [system.pc.south_bridge.ide]
 type=IdeController
@@ -1281,9 +1290,9 @@ pci_func=0
 pio_latency=1000
 platform=system.pc
 system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
+config=system.iobus.port[5]
+dma=system.iobus.port[6]
+pio=system.iobus.port[4]
 
 [system.pc.south_bridge.ide.disks0]
 type=IdeDisk
@@ -1302,7 +1311,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1322,7 +1331,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1411,8 +1420,8 @@ pio_addr=4273995776
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
+int_port=system.iobus.port[13]
+pio=system.iobus.port[12]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1425,7 +1434,7 @@ pio_addr=0
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[4]
+pio=system.iobus.port[7]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1443,7 +1452,7 @@ pio_latency=1000
 platform=system.pc
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.port[5]
+pio=system.iobus.port[8]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1458,7 +1467,7 @@ pio_latency=1000
 platform=system.pc
 slave=Null
 system=system
-pio=system.iobus.port[6]
+pio=system.iobus.port[9]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1471,7 +1480,7 @@ pio_addr=9223372036854775872
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[7]
+pio=system.iobus.port[10]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1483,7 +1492,7 @@ pio_addr=9223372036854775905
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[8]
+pio=system.iobus.port[11]
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 18f42b689..873e1bea2 100755
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 20:47:38
-gem5 started Jan  9 2012 21:13:16
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Jan 23 2012 04:12:17
+gem5 started Jan 23 2012 08:29:15
+gem5 executing on zizzer
+command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5161177988500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index e687ea7eb..c62526985 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.161178                       # Number of seconds simulated
 sim_ticks                                5161177988500                       # Number of ticks simulated
+final_tick                               5161177988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 384526                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2360358751                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386468                       # Number of bytes of host memory used
-host_seconds                                  2186.61                       # Real time elapsed on the host
+host_inst_rate                                 290092                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1780684720                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 364016                       # Number of bytes of host memory used
+host_seconds                                  2898.42                       # Real time elapsed on the host
 sim_insts                                   840808469                       # Number of instructions simulated
+system.physmem.bytes_read                    16106624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1233856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 12115136                       # Number of bytes written to this memory
+system.physmem.num_reads                       251666                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      189299                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3120726                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    239065                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2347359                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5468085                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        169467                       # number of replacements
 system.l2c.tagsinuse                     38339.786444                       # Cycle average of tags in use
 system.l2c.total_refs                         3812924                       # Total number of references to valid blocks.
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index 665888efd..bec9490f3 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,9 +502,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index af9fa8a65..db74d3d24 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:34:42
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:43:41
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index b76763b67..190781128 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.033081                       # Number of seconds simulated
 sim_ticks                                 33080569000                       # Number of ticks simulated
+final_tick                                33080569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152633                       # Simulator instruction rate (inst/s)
-host_tick_rate                               55333677                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347340                       # Number of bytes of host memory used
-host_seconds                                   597.84                       # Real time elapsed on the host
+host_inst_rate                                 140676                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50998874                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353196                       # Number of bytes of host memory used
+host_seconds                                   648.65                       # Real time elapsed on the host
 sim_insts                                    91249885                       # Number of instructions simulated
+system.physmem.bytes_read                      997440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  44864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
+system.physmem.num_reads                        15585                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       30151839                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1356204                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                         61909                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      30213749                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index a584d29ed..67a5d19a5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index 778a5635d..902784594 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:50:38
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:47:31
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 6dfbf09ec..66ab48bd5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1991743                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 385676                       # Number of bytes of host memory used
-host_seconds                                    45.82                       # Real time elapsed on the host
-host_tick_rate                             1183885034                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91252969                       # Number of instructions simulated
 sim_seconds                                  0.054241                       # Number of seconds simulated
 sim_ticks                                 54240666000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2777644                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1651027932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 342980                       # Number of bytes of host memory used
+host_seconds                                    32.85                       # Real time elapsed on the host
+sim_insts                                    91252969                       # Number of instructions simulated
+system.physmem.bytes_read                   521339715                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              431323116                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 18908138                       # Number of bytes written to this memory
+system.physmem.num_reads                    130384074                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     4738868                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9611602391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7952024704                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     348597084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9960199475                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
 system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                         91252969                       # Number of instructions executed
 system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
 system.cpu.num_int_register_reads           396912516                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
-system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index b43580bea..2f73411a5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index ce41a8bab..959967602 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:51:14
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:48:15
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 9c2d92308..d6f3be234 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1371366                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 393424                       # Number of bytes of host memory used
-host_seconds                                    66.52                       # Real time elapsed on the host
-host_tick_rate                             2226109550                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91226321                       # Number of instructions simulated
 sim_seconds                                  0.148086                       # Number of seconds simulated
 sim_ticks                                148086239000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26337591                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               946798                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 942702                       # number of replacements
-system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   942309                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1300672                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2111359212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 351948                       # Number of bytes of host memory used
+host_seconds                                    70.14                       # Real time elapsed on the host
+sim_insts                                    91226321                       # Number of instructions simulated
+system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  36992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
+system.physmem.num_reads                        15408                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        6659039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    249800                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                         13830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       6672869                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         91226321                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_int_register_reads           464563396                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
+system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
+system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              107830181                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  599                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              107830181                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  599                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
-system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 942702                       # number of replacements
+system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               26337591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               946798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   942309                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   634                       # number of replacements
+system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                931989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15408                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                      32                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                931989                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               15408                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                   634                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         91226321                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
-system.cpu.num_int_insts                     72525682                       # number of integer instructions
-system.cpu.num_int_register_reads           464563396                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
-system.cpu.num_load_insts                    22573967                       # Number of load instructions
-system.cpu.num_mem_refs                      27318811                       # number of memory refs
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 7b0140e7c..77055bd16 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index ef22c481f..18a19b6d7 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:20:13
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index a31e20e25..e3ffceab4 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.122216                       # Number of seconds simulated
 sim_ticks                                122215830000                       # Number of ticks simulated
+final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3705610                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1857336235                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 328592                       # Number of bytes of host memory used
-host_seconds                                    65.80                       # Real time elapsed on the host
+host_inst_rate                                3409932                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1709135687                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 338176                       # Number of bytes of host memory used
+host_seconds                                    71.51                       # Real time elapsed on the host
 sim_insts                                   243835278                       # Number of instructions simulated
+system.physmem.bytes_read                  1306360053                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              977686044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 91606089                       # Number of bytes written to this memory
+system.physmem.num_reads                    326641945                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    22901951                       # Number of write requests responded to by this memory
+system.physmem.num_other                         3886                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10688959466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999667834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     749543566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11438503032                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index f14a1754a..acd41b2d5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 5a81ca9dc..ca44a686d 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:21:35
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index cec6d8979..7dc591cfe 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.362431                       # Number of seconds simulated
 sim_ticks                                362430887000                       # Number of ticks simulated
+final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1940887                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2884887520                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 337564                       # Number of bytes of host memory used
-host_seconds                                   125.63                       # Real time elapsed on the host
+host_inst_rate                                1587659                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2359857170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346888                       # Number of bytes of host memory used
+host_seconds                                   153.58                       # Real time elapsed on the host
 sim_insts                                   243835278                       # Number of instructions simulated
+system.physmem.bytes_read                     1001472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  56256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2560                       # Number of bytes written to this memory
+system.physmem.num_reads                        15648                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          40                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2763208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    155219                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                          7063                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2770272                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
index 103b3f085..cfda7ba22 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,9 +502,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index 5b6f3a1bd..426afea0c 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:45:46
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 6fc7a3666..f9c970889 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.070313                       # Number of seconds simulated
 sim_ticks                                 70312944500                       # Number of ticks simulated
+final_tick                                70312944500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109444                       # Simulator instruction rate (inst/s)
-host_tick_rate                               27661822                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378996                       # Number of bytes of host memory used
-host_seconds                                  2541.88                       # Real time elapsed on the host
+host_inst_rate                                 168126                       # Simulator instruction rate (inst/s)
+host_tick_rate                               42493747                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 349904                       # Number of bytes of host memory used
+host_seconds                                  1654.67                       # Real time elapsed on the host
 sim_insts                                   278192519                       # Number of instructions simulated
+system.physmem.bytes_read                     4896576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  65344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  1867840                       # Number of bytes written to this memory
+system.physmem.num_reads                        76509                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       29185                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       69639752                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    929331                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      26564668                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      96204419                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        140625890                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index aaa5a7780..96706c5cc 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,9 +69,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index c929e4789..eb189c10a 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:52:52
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 0cce68f38..e99e16cd0 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.168950                       # Number of seconds simulated
 sim_ticks                                168950072000                       # Number of ticks simulated
+final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1147935                       # Simulator instruction rate (inst/s)
-host_tick_rate                              697156581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 368676                       # Number of bytes of host memory used
-host_seconds                                   242.34                       # Real time elapsed on the host
+host_inst_rate                                2042288                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1240309006                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339312                       # Number of bytes of host memory used
+host_seconds                                   136.22                       # Real time elapsed on the host
 sim_insts                                   278192520                       # Number of instructions simulated
+system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1741569664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                243173115                       # Number of bytes written to this memory
+system.physmem.num_reads                    308475658                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    31439751                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    14553504772                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               10308191310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1439319393                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   15992824164                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index 2ff958baf..008adeebb 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,9 +172,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:268435455
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 07f15598f..e89b51a20 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:55:19
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 35887f197..59ae818d2 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.370011                       # Number of seconds simulated
 sim_ticks                                370010840000                       # Number of ticks simulated
+final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 588786                       # Simulator instruction rate (inst/s)
-host_tick_rate                              783116445                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 377276                       # Number of bytes of host memory used
-host_seconds                                   472.49                       # Real time elapsed on the host
+host_inst_rate                                1163147                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1547047043                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348152                       # Number of bytes of host memory used
+host_seconds                                   239.17                       # Real time elapsed on the host
 sim_insts                                   278192520                       # Number of instructions simulated
+system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  51712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  1885440                       # Number of bytes written to this memory
+system.physmem.num_reads                        76575                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       29460                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       13245017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    139758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5095634                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      18340652                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index bdd61e6fb..e2c071016 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -478,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -520,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -530,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index a9de996c2..c61c0591a 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  8 2012 22:11:51
-gem5 started Jan  9 2012 02:13:40
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:49:36
 gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index 6e5455372..0cc2b2b8d 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.274199                       # Number of seconds simulated
 sim_ticks                                274198757500                       # Number of ticks simulated
+final_tick                               274198757500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113676                       # Simulator instruction rate (inst/s)
-host_tick_rate                               54365362                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225168                       # Number of bytes of host memory used
-host_seconds                                  5043.63                       # Real time elapsed on the host
+host_inst_rate                                 114096                       # Simulator instruction rate (inst/s)
+host_tick_rate                               54566255                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225172                       # Number of bytes of host memory used
+host_seconds                                  5025.06                       # Real time elapsed on the host
 sim_insts                                   573341162                       # Number of instructions simulated
+system.physmem.bytes_read                    15248640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 230400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10960192                       # Number of bytes written to this memory
+system.physmem.num_reads                       238260                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      171253                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       55611631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    840266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      39971706                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      95583336                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 8b55eca4f..cbe7d05b4 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index 7da122073..e26a927e8 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:53:21
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 6d10538b7..12a51d6fd 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3887693                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256484                       # Number of bytes of host memory used
-host_seconds                                   146.87                       # Real time elapsed on the host
-host_tick_rate                             1977989899                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   570968176                       # Number of instructions simulated
 sim_seconds                                  0.290499                       # Number of seconds simulated
 sim_ticks                                290498972000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               290498972000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3123764                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1589318228                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213568                       # Number of bytes of host memory used
+host_seconds                                   182.78                       # Real time elapsed on the host
+sim_insts                                   570968176                       # Number of instructions simulated
+system.physmem.bytes_read                  2489298238                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2066445536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                216067624                       # Number of bytes written to this memory
+system.physmem.num_reads                    641840242                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    55727847                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8569043191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7113434935                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     743781028                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9312824219                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
 system.cpu.numCycles                        580997945                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  580997945                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        570968176                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_int_register_reads          2465023721                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
-system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     182890035                       # number of memory refs
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  580997945                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 1771ad8e9..5a2d86232 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 3ee3b4f05..8c1353073 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:55:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 9f67dc057..f9d747bd5 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1138464                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 264236                       # Number of bytes of host memory used
-host_seconds                                   499.83                       # Real time elapsed on the host
-host_tick_rate                             1444968716                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   569034848                       # Number of instructions simulated
 sim_seconds                                  0.722234                       # Number of seconds simulated
 sim_ticks                                722234364000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits          1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          123740317                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              122957659                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    15502704000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.006325                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               782658                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  13154730000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.006325                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          782658                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses       1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits           1488541                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              53883046                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   10028942000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              356260                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   8960162000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006568                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         356260                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           177979623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22417.457622                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               176840705                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     25531646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.006399                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1138918                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  22114892000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.006399                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1138918                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              176840705                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    25531646000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.006399                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1138918                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  22114892000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1138918                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1134822                       # number of replacements
-system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                179817787                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1025440                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               722234364000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1518630                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1927485562                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222536                       # Number of bytes of host memory used
+host_seconds                                   374.70                       # Real time elapsed on the host
+sim_insts                                   569034848                       # Number of instructions simulated
+system.physmem.bytes_read                    14797056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 188608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 11027328                       # Number of bytes written to this memory
+system.physmem.num_reads                       231204                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      172302                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       20487887                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    261145                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      15268351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35756238                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          516611385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24743.338252                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        569034848                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          2844375220                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     182890035                       # number of memory refs
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_store_insts                   56860479                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1444468728                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   9788                       # number of replacements
+system.cpu.icache.tagsinuse                984.426148                       # Cycle average of tags in use
+system.cpu.icache.total_refs                516599864                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              516599864                       # number of ReadReq hits
+system.cpu.icache.demand_hits               516599864                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              516599864                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11521                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11521                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11521                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      285068000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       285068000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      285068000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          516611385                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           516611385                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000022                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                11521                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    250505000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           11521                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000022                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000022                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24743.338252                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24743.338252                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           516611385                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24743.338252                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               516599864                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       285068000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000022                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 11521                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           11521                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            11521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           11521                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    250505000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    250505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    250505000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000022                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            11521                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000022                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              516599864                       # number of overall hits
-system.cpu.icache.overall_miss_latency      285068000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000022                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                11521                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    250505000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           11521                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   9788                       # number of replacements
-system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                984.426148                       # Cycle average of tags in use
-system.cpu.icache.total_refs                516599864                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          356260                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1134822                       # number of replacements
+system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                179817787                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              122957659                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              53883046                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits          1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits           1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               176840705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              176840705                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               782658                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              356260                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1138918                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1138918                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    15502704000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   10028942000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     25531646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    25531646000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses       1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           177979623                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.006325                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.006399                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.006399                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1025440                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1138918                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1138918                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  13154730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8960162000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  22114892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.006325                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006399                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006399                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                212089                       # number of replacements
+system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1426644                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                683006                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1025440                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits              236229                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   6241612000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.336920                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                 919235                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                919235                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              111173                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses            120031                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336920                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       120031                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            794179                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                683006                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses               231204                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              231204                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency    5780996000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.139985                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              111173                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4446920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139985                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         111173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency   6241612000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    12022608000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   12022608000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            794179                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses         1025440                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1025440                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses          356260                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1150439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.139985                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.336920                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.200970                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.200970                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1150439                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 919235                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    12022608000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.200970                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               231204                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                  172302                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         111173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       120031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          231204                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         231204                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4446920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801240000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency   9248160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   9248160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139985                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336920                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.200970                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          231204                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.200970                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                919235                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   12022608000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.200970                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              231204                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   9248160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.200970                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         231204                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                212089                       # number of replacements
-system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1426644                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  172302                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1444468728                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        569034848                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
-system.cpu.num_int_insts                    470727703                       # number of integer instructions
-system.cpu.num_int_register_reads          2844375220                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
-system.cpu.num_load_insts                   126029556                       # Number of load instructions
-system.cpu.num_mem_refs                     182890035                       # number of memory refs
-system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
index b2ef015f3..9cc27361f 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,9 +502,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index f37768727..de72d963a 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:58:28
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index 556f62c4f..92ece0bed 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.493912                       # Number of seconds simulated
 sim_ticks                                493912286000                       # Number of ticks simulated
+final_tick                               493912286000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108889                       # Simulator instruction rate (inst/s)
-host_tick_rate                               35174673                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280548                       # Number of bytes of host memory used
-host_seconds                                 14041.70                       # Real time elapsed on the host
+host_inst_rate                                 145271                       # Simulator instruction rate (inst/s)
+host_tick_rate                               46927205                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251468                       # Number of bytes of host memory used
+host_seconds                                 10525.07                       # Real time elapsed on the host
 sim_insts                                  1528988756                       # Number of instructions simulated
+system.physmem.bytes_read                    37487424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 347584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26320960                       # Number of bytes written to this memory
+system.physmem.num_reads                       585741                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411265                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       75898950                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    703736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      53290758                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     129189708                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                        987824573                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index da3b012b0..b1057156b 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,9 +69,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index d3e847fa3..b86175ab2 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:59:28
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index c9073b3b2..4e0a10e13 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.885229                       # Number of seconds simulated
 sim_ticks                                885229360000                       # Number of ticks simulated
+final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1063398                       # Simulator instruction rate (inst/s)
-host_tick_rate                              615669149                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237896                       # Number of bytes of host memory used
-host_seconds                                  1437.83                       # Real time elapsed on the host
+host_inst_rate                                2258239                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1307438877                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208528                       # Number of bytes of host memory used
+host_seconds                                   677.07                       # Real time elapsed on the host
 sim_insts                                  1528988757                       # Number of instructions simulated
+system.physmem.bytes_read                 10832432532                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             8546776872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                991849460                       # Number of bytes written to this memory
+system.physmem.num_reads                   1452449298                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   149160201                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    12236865406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                9654872803                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1120443475                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13357308881                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       1770458721                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index e63456bf2..c570a48d2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,9 +172,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 268de88f4..a297c4bc8 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:10:56
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index a96327ae0..28d09902a 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.658730                       # Number of seconds simulated
 sim_ticks                                1658729604000                       # Number of ticks simulated
+final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 746220                       # Simulator instruction rate (inst/s)
-host_tick_rate                              809539282                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246668                       # Number of bytes of host memory used
-host_seconds                                  2048.98                       # Real time elapsed on the host
+host_inst_rate                                1326745                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1439324936                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217512                       # Number of bytes of host memory used
+host_seconds                                  1152.44                       # Real time elapsed on the host
 sim_insts                                  1528988757                       # Number of instructions simulated
+system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 148544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26349376                       # Number of bytes written to this memory
+system.physmem.num_reads                       579609                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411709                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       22363486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     89553                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      15885275                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      38248761                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index c7fe40f76..16e4d1756 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
index 9794df862..1c2a18294 100755
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:09:26
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 8f2720cda..a04efd18a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.139995                       # Number of seconds simulated
 sim_ticks                                139995113500                       # Number of ticks simulated
+final_tick                               139995113500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56567                       # Simulator instruction rate (inst/s)
-host_tick_rate                               19864025                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252292                       # Number of bytes of host memory used
-host_seconds                                  7047.67                       # Real time elapsed on the host
+host_inst_rate                                 118986                       # Simulator instruction rate (inst/s)
+host_tick_rate                               41783300                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214012                       # Number of bytes of host memory used
+host_seconds                                  3350.50                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
+system.physmem.bytes_read                      469184                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 214784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7331                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3351431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1534225                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3351431                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 01d03e5c5..0fce2844b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 46133d214..137fd0ee8 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index f27e3deec..28785f469 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.089480                       # Number of seconds simulated
 sim_ticks                                 89480174500                       # Number of ticks simulated
+final_tick                                89480174500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168732                       # Simulator instruction rate (inst/s)
-host_tick_rate                               40200085                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211620                       # Number of bytes of host memory used
-host_seconds                                  2225.87                       # Real time elapsed on the host
+host_inst_rate                                 190161                       # Simulator instruction rate (inst/s)
+host_tick_rate                               45305657                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214676                       # Number of bytes of host memory used
+host_seconds                                  1975.03                       # Real time elapsed on the host
 sim_insts                                   375574794                       # Number of instructions simulated
+system.physmem.bytes_read                      475840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 219968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7435                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        5317826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2458288                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5317826                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 5f40a4aa8..8310ba9e4 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,11 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 0fd1f360f..3a628f576 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:03:34
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 6655c3650..3ed2b47f1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5567399                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202284                       # Number of bytes of host memory used
-host_seconds                                    71.61                       # Real time elapsed on the host
-host_tick_rate                             2783694716                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   398664595                       # Number of instructions simulated
 sim_seconds                                  0.199332                       # Number of seconds simulated
 sim_ticks                                199332411500                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                168275274                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    168275218                       # DTB hits
-system.cpu.dtb.data_misses                         56                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3927016                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1963508553                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204908                       # Number of bytes of host memory used
+host_seconds                                   101.52                       # Real time elapsed on the host
+sim_insts                                   398664595                       # Number of instructions simulated
+system.physmem.bytes_read                  2257107875                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1594658604                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                492356798                       # Number of bytes written to this memory
+system.physmem.num_reads                    493419140                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    73520729                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11323336020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999996548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    2470028804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13793364824                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 94754510                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                     94754489                       # DTB read hits
 system.cpu.dtb.read_misses                         21                       # DTB read misses
-system.cpu.dtb.write_accesses                73520764                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 94754510                       # DTB read accesses
 system.cpu.dtb.write_hits                    73520729                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               398664824                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73520764                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275218                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                168275274                       # DTB accesses
 system.cpu.itb.fetch_hits                   398664651                       # ITB hits
 system.cpu.itb.fetch_misses                       173                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               398664824                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
 system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  398664824                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     25997787                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
-system.cpu.num_fp_insts                     155295119                       # number of float instructions
-system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
-system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        398664595                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             316365907                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     25997787                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    316365907                       # number of integer instructions
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
 system.cpu.num_int_register_reads           372938760                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          159335860                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94754510                       # Number of load instructions
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     168275274                       # number of memory refs
+system.cpu.num_load_insts                    94754510                       # Number of load instructions
 system.cpu.num_store_insts                   73520764                       # Number of store instructions
-system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  398664824                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index c222d6133..63aac5a1a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -1,11 +1,7 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 2be6be9ef..06075d86e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:04:03
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 94a73b71f..af7a7f90d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,255 +1,265 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2583171                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210032                       # Number of bytes of host memory used
-host_seconds                                   154.33                       # Real time elapsed on the host
-host_tick_rate                             3676130341                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567343                       # Number of seconds simulated
 sim_ticks                                567343170000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       48286000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     176792000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    167186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54209.537572                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       225078000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    212622000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.802957                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              168271068                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      225078000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4152                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    212622000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                    764                       # number of replacements
-system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      649                       # number of writebacks
-system.cpu.dtb.data_accesses                168275276                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    168275220                       # DTB hits
-system.cpu.dtb.data_misses                         56                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                               567343170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1814376                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2582053806                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213620                       # Number of bytes of host memory used
+host_seconds                                   219.73                       # Real time elapsed on the host
+sim_insts                                   398664609                       # Number of instructions simulated
+system.physmem.bytes_read                      459520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 205120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7180                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         809951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    361545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        809951                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                     94754490                       # DTB read hits
 system.cpu.dtb.read_misses                         21                       # DTB read misses
-system.cpu.dtb.write_accesses                73520765                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
 system.cpu.dtb.write_hits                    73520730                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 50648.516199                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199                       # average ReadReq mshr miss latency
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73520765                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275220                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                168275276                       # DTB accesses
+system.cpu.itb.fetch_hits                   398664666                       # ITB hits
+system.cpu.itb.fetch_misses                       173                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        398664609                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     25997790                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    316365921                       # number of integer instructions
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
+system.cpu.num_int_register_reads           372938779                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          159335870                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     168275276                       # number of memory refs
+system.cpu.num_load_insts                    94754511                       # Number of load instructions
+system.cpu.num_store_insts                   73520765                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1134686340                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1769                       # number of replacements
+system.cpu.icache.tagsinuse               1795.131074                       # Cycle average of tags in use
+system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.876529                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              398660993                       # number of ReadReq hits
+system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              398660993                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 3673                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      186032000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       186032000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      186032000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    175013000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 50648.516199                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 50648.516199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 50648.516199                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       186032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    175013000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    175013000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    175013000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.876529                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              398660993                       # number of overall hits
-system.cpu.icache.overall_miss_latency      186032000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 3673                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    175013000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   1769                       # number of replacements
-system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1795.131074                       # Cycle average of tags in use
-system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   398664666                       # ITB hits
-system.cpu.itb.fetch_misses                       173                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    764                       # number of replacements
+system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.802957                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              168271068                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 4152                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       48286000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     176792000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       225078000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      225078000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      649                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    167186000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    212622000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    212622000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    13                       # number of replacements
+system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     656                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4572                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.143482                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.103674                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011338                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    163384000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                    645                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                   645                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses              3142                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    125680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981262                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         3142                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses                 7180                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7180                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency     209976000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency    163384000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      373360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     373360000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.143482                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.917572                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.917572                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                    645                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      373360000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.917572                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7180                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         3142                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7180                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7180                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    125680000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency    287200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    287200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981262                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.917572                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7180                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.103674                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011338                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.917572                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                   645                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     373360000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.917572                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7180                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    287200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.917572                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7180                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    13                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4572                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     656                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1134686340                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     25997790                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
-system.cpu.num_fp_insts                     155295119                       # number of float instructions
-system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
-system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        398664609                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
-system.cpu.num_int_insts                    316365921                       # number of integer instructions
-system.cpu.num_int_register_reads           372938779                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          159335870                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94754511                       # Number of load instructions
-system.cpu.num_mem_refs                     168275276                       # number of memory refs
-system.cpu.num_store_insts                   73520765                       # Number of store instructions
-system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index 8c023b5bc..297538e80 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index 5bda3e9bb..2948fc7c4 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:59:30
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:57:55
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index 3a7bc5069..995432cc7 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.104498                       # Number of seconds simulated
 sim_ticks                                104497559500                       # Number of ticks simulated
+final_tick                               104497559500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 166687                       # Simulator instruction rate (inst/s)
-host_tick_rate                               49899949                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223124                       # Number of bytes of host memory used
-host_seconds                                  2094.14                       # Real time elapsed on the host
+host_inst_rate                                 155883                       # Simulator instruction rate (inst/s)
+host_tick_rate                               46665641                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228988                       # Number of bytes of host memory used
+host_seconds                                  2239.28                       # Real time elapsed on the host
 sim_insts                                   349066034                       # Number of instructions simulated
+system.physmem.bytes_read                      464512                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 192704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7258                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        4445195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1844100                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       4445195                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index a5b41f00b..5628f29f0 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -1,5 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index e711f37f2..2369bef1b 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:58:30
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:01:21
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 01b0f0b3b..7857a9031 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1939083                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 261408                       # Number of bytes of host memory used
-host_seconds                                   180.02                       # Real time elapsed on the host
-host_tick_rate                             1179584644                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   349065408                       # Number of instructions simulated
 sim_seconds                                  0.212344                       # Number of seconds simulated
 sim_ticks                                212344048000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               212344048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2434260                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1480812932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218160                       # Number of bytes of host memory used
+host_seconds                                   143.40                       # Real time elapsed on the host
+sim_insts                                   349065408                       # Number of instructions simulated
+system.physmem.bytes_read                  1875350709                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1394641440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                400047783                       # Number of bytes written to this memory
+system.physmem.num_reads                    443242866                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    82063572                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8831661291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                6567838624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1883960425                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10715621716                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
 system.cpu.numCycles                        424688097                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  424688097                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     16271154                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
-system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        349065408                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             279584926                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     16271154                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    279584926                       # number of integer instructions
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
 system.cpu.num_int_register_reads          1887652191                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          251197918                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     177024357                       # number of memory refs
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
-system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  424688097                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index aed18b872..28a0917d8 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index daf6c8759..3428f8224 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:00:20
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:03:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 1ba27a33f..3b365c759 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,279 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1262416                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 269124                       # Number of bytes of host memory used
-host_seconds                                   276.21                       # Real time elapsed on the host
-host_tick_rate                             1903846429                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   348687131                       # Number of instructions simulated
 sim_seconds                                  0.525854                       # Number of seconds simulated
 sim_ticks                                525854475000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits            10895                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           94571611                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               94570005                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       79898000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 1606                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses            1606                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             10895                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              82049805                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               39446.538633                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           176624288                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53608.307280                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               176619810                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       240058000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4478                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4478                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.751562                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              176619810                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      240058000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4478                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    226624000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4478                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                   1332                       # number of replacements
-system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                176641600                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      998                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               525854475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1206167                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1819018700                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227092                       # Number of bytes of host memory used
+host_seconds                                   289.09                       # Real time elapsed on the host
+sim_insts                                   348687131                       # Number of instructions simulated
+system.physmem.bytes_read                      437312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 167040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         6833                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         831622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    317654                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        831622                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          348660359                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 21025.572005                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                       1051708950                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        348687131                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             279584925                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     16271153                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    279584925                       # number of integer instructions
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
+system.cpu.num_int_register_reads          2212913209                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          251197915                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     177024357                       # number of memory refs
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_store_insts                   82375599                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1051708950                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  13796                       # number of replacements
+system.cpu.icache.tagsinuse               1765.984158                       # Cycle average of tags in use
+system.cpu.icache.total_refs                348644756                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               22344.725758                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.862297                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              348644756                       # number of ReadReq hits
+system.cpu.icache.demand_hits               348644756                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              348644756                       # number of overall hits
+system.cpu.icache.ReadReq_misses                15603                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 15603                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                15603                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      328062000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       328062000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      328062000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          348660359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           348660359                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000045                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                15603                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    281253000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000045                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           15603                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               22344.725758                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 21025.572005                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 21025.572005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           348660359                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 21025.572005                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               348644756                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       328062000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 15603                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           15603                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            15603                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           15603                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    281253000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    281253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    281253000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000045                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            15603                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.862297                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000045                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              348644756                       # number of overall hits
-system.cpu.icache.overall_miss_latency      328062000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                15603                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    281253000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           15603                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  13796                       # number of replacements
-system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1765.984158                       # Cycle average of tags in use
-system.cpu.icache.total_refs                348644756                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            2872                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1332                       # number of replacements
+system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                176641600                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               39446.538633                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94570005                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              82049805                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            10895                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             10895                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               176619810                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              176619810                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1606                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  4478                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 4478                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       79898000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       240058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      240058000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94571611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           176624288                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      998                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses            1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4478                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     75080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    151544000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    226624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    226624000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    48                       # number of replacements
+system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13308                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.725374                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.095644                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 13232                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                  16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    148512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                  13248                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 13248                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3977                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses              2856                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             17209                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 13232                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                6833                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency     206804000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.231100                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                3977                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231100                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency    148512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             17209                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses             998                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.725374                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses            2872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              20081                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.231100                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.340272                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.340272                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              20081                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  13248                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.340272                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency    273320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231100                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.340272                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.095644                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.010425                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.340272                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 13248                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.340272                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                6833                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.340272                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    48                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13308                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1051708950                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1051708950                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     16271153                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
-system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        348687131                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             279584925                       # Number of integer alu accesses
-system.cpu.num_int_insts                    279584925                       # number of integer instructions
-system.cpu.num_int_register_reads          2212913209                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          251197915                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94648758                       # Number of load instructions
-system.cpu.num_mem_refs                     177024357                       # number of memory refs
-system.cpu.num_store_insts                   82375599                       # Number of store instructions
-system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 7c1b2f7e5..c87170fbe 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index ec96cb05b..2a099e16b 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 21:33:28
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:04
 gem5 executing on zizzer
-command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index c68641234..90210da82 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.643030                       # Number of seconds simulated
 sim_ticks                                643030478500                       # Number of ticks simulated
+final_tick                               643030478500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 153773                       # Simulator instruction rate (inst/s)
-host_tick_rate                               54239400                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218648                       # Number of bytes of host memory used
-host_seconds                                 11855.41                       # Real time elapsed on the host
+host_inst_rate                                 153915                       # Simulator instruction rate (inst/s)
+host_tick_rate                               54289503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215008                       # Number of bytes of host memory used
+host_seconds                                 11844.47                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
+system.physmem.bytes_read                    94779264                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 185664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
+system.physmem.num_reads                      1480926                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66898                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      147394668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    288733                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       6658272                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     154052940                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index f80631f28..a895468a4 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index c5f9e3fdc..67c7a90bd 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:33:29
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:36
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index b6ea3474a..5a9e50b92 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.004711                       # Number of seconds simulated
 sim_ticks                                1004710587000                       # Number of ticks simulated
+final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3394241                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1697486503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 190248                       # Number of bytes of host memory used
-host_seconds                                   591.88                       # Real time elapsed on the host
+host_inst_rate                                4051601                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2026237516                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204820                       # Number of bytes of host memory used
+host_seconds                                   495.85                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
+system.physmem.bytes_read                 11607100996                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             8037684280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1586125963                       # Number of bytes written to this memory
+system.physmem.num_reads                   2520491096                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   210794896                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11552681087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999586                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1578689409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13131370496                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index d0df4a5be..f60b78837 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 8bb74946d..e767ec1c4 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 13:15:24
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:03
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index eed39f9d4..668a6f1dd 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.813468                       # Number of seconds simulated
 sim_ticks                                2813467842000                       # Number of ticks simulated
+final_tick                               2813467842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1436300                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2011453251                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 198964                       # Number of bytes of host memory used
-host_seconds                                  1398.72                       # Real time elapsed on the host
+host_inst_rate                                1954286                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2736861040                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213480                       # Number of bytes of host memory used
+host_seconds                                  1027.99                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
+system.physmem.bytes_read                    94708160                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 152128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
+system.physmem.num_reads                      1479815                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66898                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       33662428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     54071                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1521777                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35184206                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index eaf32daa6..7e5e4838d 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
index fc03e6958..af8b043ac 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:31:45
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:08:55
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index e47b3cac2..7b72f7ce4 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.708403                       # Number of seconds simulated
 sim_ticks                                708403313500                       # Number of ticks simulated
+final_tick                               708403313500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 129621                       # Simulator instruction rate (inst/s)
-host_tick_rate                               48704258                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220728                       # Number of bytes of host memory used
-host_seconds                                 14545.00                       # Real time elapsed on the host
+host_inst_rate                                 118434                       # Simulator instruction rate (inst/s)
+host_tick_rate                               44501063                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226576                       # Number of bytes of host memory used
+host_seconds                                 15918.80                       # Real time elapsed on the host
 sim_insts                                  1885333786                       # Number of instructions simulated
+system.physmem.bytes_read                    94812032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 200960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
+system.physmem.num_reads                      1481438                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66099                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      133839058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    283680                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5971649                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     139810707                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 97cb6c6e4..6a275dc9a 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index 805a6606f..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: fcntl64(3, 2) passed through to host
-For more information see: http://www.m5sim.org/warn/a55e2c46
 hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 343cd2a25..dd29e750e 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:03:45
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:17:45
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 9d864db40..49ae2817e 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1799997                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258316                       # Number of bytes of host memory used
-host_seconds                                  1047.41                       # Real time elapsed on the host
-host_tick_rate                              902810159                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1885336367                       # Number of instructions simulated
 sim_seconds                                  0.945613                       # Number of seconds simulated
 sim_ticks                                945613131000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               945613131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2997522                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1503443037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215364                       # Number of bytes of host memory used
+host_seconds                                   628.97                       # Real time elapsed on the host
+sim_insts                                  1885336367                       # Number of instructions simulated
+system.physmem.bytes_read                  8025491315                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             5561086040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1123958396                       # Number of bytes written to this memory
+system.physmem.num_reads                   2010616909                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   276945663                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8487076852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                5880931491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1188602780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9675679632                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
 system.cpu.numCycles                       1891226263                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1891226263                       # Number of busy cycles
-system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
-system.cpu.num_fp_insts                      52289415                       # number of float instructions
-system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                       1885336367                       # Number of instructions executed
 system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1653698876                       # number of integer instructions
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
 system.cpu.num_int_register_reads          8601515950                       # number of times the integer registers were read
 system.cpu.num_int_register_writes         1874331406                       # number of times the integer registers were written
-system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     908382480                       # number of memory refs
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1891226263                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index f566d5f40..01aaafc03 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
index 805a6606f..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: fcntl64(3, 2) passed through to host
-For more information see: http://www.m5sim.org/warn/a55e2c46
 hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index 5a9581642..df0dd80b9 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:11:59
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:28:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index fd9599dfa..117215dc5 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 933614                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 266072                       # Number of bytes of host memory used
-host_seconds                                  2007.52                       # Real time elapsed on the host
-host_tick_rate                             1180515097                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1874244950                       # Number of instructions simulated
 sim_seconds                                  2.369902                       # Number of seconds simulated
 sim_ticks                                2369901960000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits             9985                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          620335414                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              618874541                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    79725982000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1460873                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  75343363000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1460873                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses          9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits              9985                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             276862898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 584.067849                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           897271092                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54458.738711                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               895737439                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     83520808000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1533653                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  78919849000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1533653                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999746                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              895737439                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    83520808000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1533653                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  78919849000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1533653                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1529557                       # number of replacements
-system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.960333                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                895757409                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              997882000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   107259                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               2369901960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1407810                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1780114775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224180                       # Number of bytes of host memory used
+host_seconds                                  1331.32                       # Real time elapsed on the host
+sim_insts                                  1874244950                       # Number of instructions simulated
+system.physmem.bytes_read                    94696320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 144448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
+system.physmem.num_reads                      1479630                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66099                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       39957906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     60951                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1785026                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      41742932                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses         1390271511                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.numCycles                       4739803920                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1874244950                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1653698876                       # number of integer instructions
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
+system.cpu.num_int_register_reads         10466679954                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1874331406                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     908382480                       # number of memory refs
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_store_insts                  276995298                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 4739803920                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  18364                       # number of replacements
+system.cpu.icache.tagsinuse               1392.324437                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1390251708                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               70204.095743                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.679846                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits             1390251708                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1390251708                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1390251708                       # number of overall hits
+system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                19803                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      372036000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1390271511                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1390271511                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    312627000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               70204.095743                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1390271511                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1390251708                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            19803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           19803                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    312627000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    312627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    312627000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            19803                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.679846                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1390251708                       # number of overall hits
-system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                19803                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    312627000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           19803                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  18364                       # number of replacements
-system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1392.324437                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1390251708                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           72780                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1529557                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.960333                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                895757409                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 584.067849                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              997882000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              618874541                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             276862898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             9985                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              9985                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               895737439                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              895737439                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1460873                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1533653                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1533653                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    79725982000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     83520808000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    83520808000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          620335414                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         9985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          9985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           897271092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   107259                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1460873                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1533653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1533653                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  75343363000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  78919849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  78919849000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1478755                       # number of replacements
+system.cpu.l2cache.tagsinuse             31934.844118                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   75453                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1511475                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.049920                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.881757                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.092817                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 67139                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                6687                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3436836000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.908120                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                  73826                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 73826                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1413537                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses             66093                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1480676                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 67139                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses              1479630                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1479630                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency   73503924000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.954657                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1413537                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56541480000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954657                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1413537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency   3436836000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    76940760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   76940760000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1480676                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses          107259                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.049920                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses           72780                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1553456                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.954657                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.908120                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.952476                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.952476                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1553456                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  73826                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    76940760000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.952476                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1479630                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   66099                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1413537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1479630                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1479630                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56541480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency  59185200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  59185200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954657                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.952476                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1479630                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.881757                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.092817                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.952476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 73826                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   76940760000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.952476                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1479630                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  59185200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.952476                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1479630                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1478755                       # number of replacements
-system.cpu.l2cache.sampled_refs               1511475                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31934.844118                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   75453                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4739803920                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 4739803920                       # Number of busy cycles
-system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
-system.cpu.num_fp_insts                      52289415                       # number of float instructions
-system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1874244950                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1653698876                       # number of integer instructions
-system.cpu.num_int_register_reads         10466679954                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1874331406                       # number of times the integer registers were written
-system.cpu.num_load_insts                   631387182                       # Number of load instructions
-system.cpu.num_mem_refs                     908382480                       # number of memory refs
-system.cpu.num_store_insts                  276995298                       # Number of store instructions
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index e20a60e8c..1b963b10c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index a3cf9c876..0aab67a06 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:45:59
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index a84fb4906..32a07ce20 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.046914                       # Number of seconds simulated
 sim_ticks                                 46914279500                       # Number of ticks simulated
+final_tick                                46914279500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53929                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28639497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254456                       # Number of bytes of host memory used
-host_seconds                                  1638.10                       # Real time elapsed on the host
+host_inst_rate                                 107347                       # Simulator instruction rate (inst/s)
+host_tick_rate                               57007816                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216192                       # Number of bytes of host memory used
+host_seconds                                   822.94                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11164096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 599296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712960                       # Number of bytes written to this memory
+system.physmem.num_reads                       174439                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120515                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      237967973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  12774277                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     164405381                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     402373354                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2f92d3206..ea038d4da 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 6c1f5182e..9e435cc97 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:08
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:35:02
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index a5baa0129..9c4b77b7d 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.021260                       # Number of seconds simulated
 sim_ticks                                 21259532000                       # Number of ticks simulated
+final_tick                                21259532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 184165                       # Simulator instruction rate (inst/s)
-host_tick_rate                               49191900                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214460                       # Number of bytes of host memory used
-host_seconds                                   432.18                       # Real time elapsed on the host
+host_inst_rate                                 187781                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50157547                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217440                       # Number of bytes of host memory used
+host_seconds                                   423.86                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
+system.physmem.bytes_read                    11229312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 642688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7713344                       # Number of bytes written to this memory
+system.physmem.num_reads                       175458                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120521                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      528201279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  30230581                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     362818147                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     891019426                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index d98970549..d8535707b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index c4b225cf1..160c80ddb 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:18:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:17
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 1ca39fde6..4fc91e266 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.044221                       # Number of seconds simulated
 sim_ticks                                 44221003000                       # Number of ticks simulated
+final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3266324                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1635033806                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 192576                       # Number of bytes of host memory used
-host_seconds                                    27.05                       # Real time elapsed on the host
+host_inst_rate                                3998504                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2001543652                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206876                       # Number of bytes of host memory used
+host_seconds                                    22.09                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                   480454939                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              353752292                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 91652896                       # Number of bytes written to this memory
+system.physmem.num_reads                    108714711                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    14613377                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10864858470                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999644241                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    2072610067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12937468537                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 7e8e19e97..f99b5fb55 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index eff2b3a97..e74b48d2a 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:44:27
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 02c53f6a1..59b869a9f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.134277                       # Number of seconds simulated
 sim_ticks                                134276988000                       # Number of ticks simulated
+final_tick                               134276988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1277823                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1942278600                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201212                       # Number of bytes of host memory used
-host_seconds                                    69.13                       # Real time elapsed on the host
+host_inst_rate                                1801981                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2738992827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215584                       # Number of bytes of host memory used
+host_seconds                                    49.02                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11121920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 558272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712384                       # Number of bytes written to this memory
+system.physmem.num_reads                       173780                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120506                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       82828191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4157615                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      57436379                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     140264570                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index 64e40f331..1feff9641 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 46db9d24e..41153b9d0 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:34:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:34:51
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index ceab52925..858b9d08f 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.031183                       # Number of seconds simulated
 sim_ticks                                 31183407000                       # Number of ticks simulated
+final_tick                                31183407000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167832                       # Simulator instruction rate (inst/s)
-host_tick_rate                               52006067                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223216                       # Number of bytes of host memory used
-host_seconds                                   599.61                       # Real time elapsed on the host
+host_inst_rate                                 157932                       # Simulator instruction rate (inst/s)
+host_tick_rate                               48938242                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229072                       # Number of bytes of host memory used
+host_seconds                                   637.20                       # Real time elapsed on the host
 sim_insts                                   100634165                       # Number of instructions simulated
+system.physmem.bytes_read                     8651648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 350016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5661184                       # Number of bytes written to this memory
+system.physmem.num_reads                       135182                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       88456                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      277443962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  11224431                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     181544756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     458988718                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index d284ed163..321a621c1 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 6efadf55b..cba7edc9e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:19:31
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:35:25
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 7bc0f9c46..550377594 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3680206                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260724                       # Number of bytes of host memory used
-host_seconds                                    27.34                       # Real time elapsed on the host
-host_tick_rate                             1972325214                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   100632437                       # Number of instructions simulated
 sim_seconds                                  0.053932                       # Number of seconds simulated
 sim_ticks                                 53932162000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                                53932162000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3016681                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1616735818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217624                       # Number of bytes of host memory used
+host_seconds                                    33.36                       # Real time elapsed on the host
+sim_insts                                   100632437                       # Number of instructions simulated
+system.physmem.bytes_read                   419153654                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              312580308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 78660211                       # Number of bytes written to this memory
+system.physmem.num_reads                    105301330                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    19865820                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     7771868185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                5795805256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1458502832                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9230371017                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        107864325                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  107864325                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
-system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        100632437                       # Number of instructions executed
 system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_fp_insts                            56                       # number of float instructions
 system.cpu.num_int_register_reads           452177233                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           96252298                       # number of times the integer registers were written
-system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      47862848                       # number of memory refs
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  107864325                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 8d849c15a..62eb4cdbf 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 7b793d7b7..4fb750502 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:20:07
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 4595bb26f..2fff6cef5 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 978868                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 268480                       # Number of bytes of host memory used
-host_seconds                                   101.95                       # Real time elapsed on the host
-host_tick_rate                             1305762006                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    99791663                       # Number of instructions simulated
 sim_seconds                                  0.133117                       # Number of seconds simulated
 sim_ticks                                133117442000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               46830237                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               159998                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 155902                       # number of replacements
-system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 46862075                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   122808                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               133117442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1410680                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1881780580                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226592                       # Number of bytes of host memory used
+host_seconds                                    70.74                       # Real time elapsed on the host
+sim_insts                                    99791663                       # Number of instructions simulated
+system.physmem.bytes_read                     8570688                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 294208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5660736                       # Number of bytes written to this memory
+system.physmem.num_reads                       133917                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       88449                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       64384410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2210139                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      42524375                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     106908785                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         99791663                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_int_register_reads           533542913                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           96252298                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      47862848                       # number of memory refs
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  266234884                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  16890                       # number of replacements
+system.cpu.icache.tagsinuse               1736.182852                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 78126170                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits               78126170                       # number of ReadReq hits
+system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               78126170                       # number of overall hits
+system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                18908                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    401062000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000242                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               78126170                       # number of overall hits
-system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                18908                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  16890                       # number of replacements
-system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1736.182852                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 78126170                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 155902                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 46862075                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               46830237                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               159998                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   122808                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                113660                       # number of replacements
+system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   61800                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                4405                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              133917                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency    1627080000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses          122808                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   88449                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency   5356680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.748533                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              133917                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                113660                       # number of replacements
-system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   61800                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   88449                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  266234884                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
-system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         99791663                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
-system.cpu.num_int_insts                     91472788                       # number of integer instructions
-system.cpu.num_int_register_reads           533542913                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           96252298                       # number of times the integer registers were written
-system.cpu.num_load_insts                    27307109                       # Number of load instructions
-system.cpu.num_mem_refs                      47862848                       # number of memory refs
-system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index dcd4bf473..2df6b792d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 746f2d87f..542479326 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:17:49
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:20
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 2fa280f51..dc6c31998 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.068149                       # Number of seconds simulated
 sim_ticks                                 68148678500                       # Number of ticks simulated
+final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3860753                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1932617843                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204428                       # Number of bytes of host memory used
-host_seconds                                    35.26                       # Real time elapsed on the host
+host_inst_rate                                3420916                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1712444497                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214012                       # Number of bytes of host memory used
+host_seconds                                    39.80                       # Real time elapsed on the host
 sim_insts                                   136139203                       # Number of instructions simulated
+system.physmem.bytes_read                   685773693                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              538214332                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 89882950                       # Number of bytes written to this memory
+system.physmem.num_reads                    171784884                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    20864304                       # Number of write requests responded to by this memory
+system.physmem.num_other                        15916                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10062905226                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7897648844                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1318924328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11381829554                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 51f71312a..5e34ae7a1 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 7c4300466..787eaa97a 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:48
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 15f83a274..168a8eefa 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.202942                       # Number of seconds simulated
 sim_ticks                                202941992000                       # Number of ticks simulated
+final_tick                               202941992000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2092270                       # Simulator instruction rate (inst/s)
-host_tick_rate                             3118935472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213400                       # Number of bytes of host memory used
-host_seconds                                    65.07                       # Real time elapsed on the host
+host_inst_rate                                1608666                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2398029397                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222724                       # Number of bytes of host memory used
+host_seconds                                    84.63                       # Real time elapsed on the host
 sim_insts                                   136139203                       # Number of instructions simulated
+system.physmem.bytes_read                     8970304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 835264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5584960                       # Number of bytes written to this memory
+system.physmem.num_reads                       140161                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       87265                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       44201320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4115777                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      27519982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      71721303                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index e32660b85..0d09e2e14 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 1fce660ea..8bc14bb8a 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 17:14:45
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:50
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 48a5816be..bf815a6e1 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.009857                       # Number of seconds simulated
 sim_ticks                                1009857089500                       # Number of ticks simulated
+final_tick                               1009857089500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45175                       # Simulator instruction rate (inst/s)
-host_tick_rate                               25069239                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245844                       # Number of bytes of host memory used
-host_seconds                                 40282.72                       # Real time elapsed on the host
+host_inst_rate                                 102085                       # Simulator instruction rate (inst/s)
+host_tick_rate                               56650413                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208040                       # Number of bytes of host memory used
+host_seconds                                 17826.12                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                   172617984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  54912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74938304                       # Number of bytes written to this memory
+system.physmem.num_reads                      2697156                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1170911                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      170933081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     54376                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      74206841                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     245139922                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index a21027897..4951679e2 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index a891031f9..35ea78ab1 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 21:33:03
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:43:49
 gem5 executing on zizzer
-command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 73dcce945..3e098da07 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.615292                       # Number of seconds simulated
 sim_ticks                                615292058500                       # Number of ticks simulated
+final_tick                               615292058500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 150883                       # Simulator instruction rate (inst/s)
-host_tick_rate                               53476218                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211804                       # Number of bytes of host memory used
-host_seconds                                 11505.90                       # Real time elapsed on the host
+host_inst_rate                                 151558                       # Simulator instruction rate (inst/s)
+host_tick_rate                               53715526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208624                       # Number of bytes of host memory used
+host_seconds                                 11454.64                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
+system.physmem.bytes_read                   173080384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  60288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74996480                       # Number of bytes written to this memory
+system.physmem.num_reads                      2704381                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1171820                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      281297933                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     97983                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     121887612                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     403185545                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index e886c5917..52ac7c920 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index eccdc3c2f..3465b9fda 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:23:57
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:45:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 0df85f934..1f32f6942 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.913189                       # Number of seconds simulated
 sim_ticks                                913189263000                       # Number of ticks simulated
+final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3384825                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1698548817                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 183944                       # Number of bytes of host memory used
-host_seconds                                   537.63                       # Real time elapsed on the host
+host_inst_rate                                4221832                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2118570165                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 198896                       # Number of bytes of host memory used
+host_seconds                                   431.04                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                  9280309971                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             7305514036                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                827777307                       # Number of bytes written to this memory
+system.physmem.num_reads                   2270974172                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   160728502                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10162526375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     906468506                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11068994882                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6ccdf7868..b74c06509 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 1b40535c5..5e40861f7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:54:26
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:52:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 03eecacc7..99a911858 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.663444                       # Number of seconds simulated
 sim_ticks                                2663443716000                       # Number of ticks simulated
+final_tick                               2663443716000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1486818                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2176118189                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 192584                       # Number of bytes of host memory used
-host_seconds                                  1223.94                       # Real time elapsed on the host
+host_inst_rate                                1948044                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2851171142                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207608                       # Number of bytes of host memory used
+host_seconds                                   934.16                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                   172614208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  51328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74939072                       # Number of bytes written to this memory
+system.physmem.num_reads                      2697097                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1170923                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       64808656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     19271                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      28136158                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      92944814                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 0e065d7b6..669a8b83b 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
index 0aaab6517..1474108e5 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:44:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:09
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 42652cb1d..bd2b3efef 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.483463                       # Number of seconds simulated
 sim_ticks                                483463019500                       # Number of ticks simulated
+final_tick                               483463019500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167165                       # Simulator instruction rate (inst/s)
-host_tick_rate                               46903472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214756                       # Number of bytes of host memory used
-host_seconds                                 10307.62                       # Real time elapsed on the host
+host_inst_rate                                 152421                       # Simulator instruction rate (inst/s)
+host_tick_rate                               42766664                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220608                       # Number of bytes of host memory used
+host_seconds                                 11304.67                       # Real time elapsed on the host
 sim_insts                                  1723073849                       # Number of instructions simulated
+system.physmem.bytes_read                   188174592                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  45888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 77926272                       # Number of bytes written to this memory
+system.physmem.num_reads                      2940228                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1217598                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      389222307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     94915                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     161183522                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     550405829                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 8d90d74d0..bbede2479 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index 4e09f0c47..e599bde0b 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:22:49
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:37:28
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 42e09915d..e23300649 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3743034                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 253144                       # Number of bytes of host memory used
-host_seconds                                   460.34                       # Real time elapsed on the host
-host_tick_rate                             1871519168                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1723073862                       # Number of instructions simulated
 sim_seconds                                  0.861538                       # Number of seconds simulated
 sim_ticks                                861538205000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               861538205000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3027828                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1513916118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210380                       # Number of bytes of host memory used
+host_seconds                                   569.08                       # Real time elapsed on the host
+sim_insts                                  1723073862                       # Number of instructions simulated
+system.physmem.bytes_read                  7759650064                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             6178262392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                624158392                       # Number of bytes written to this memory
+system.physmem.num_reads                   2026949786                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   172586108                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9006739363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7171199555                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     724469778                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9731209141                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                       1723076411                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1723076411                       # Number of busy cycles
-system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
-system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                       1723073862                       # Number of instructions executed
 system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_fp_insts                            36                       # number of float instructions
 system.cpu.num_int_register_reads          7861284536                       # number of times the integer registers were read
 system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
-system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     660773816                       # number of memory refs
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1723076411                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 00bc540f8..71abd898d 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index 88386aeb5..8198567b7 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:25:15
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:45:39
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index c692715dc..04e3122e6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1772581                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260892                       # Number of bytes of host memory used
-host_seconds                                   968.80                       # Real time elapsed on the host
-host_tick_rate                             2509731503                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1717270343                       # Number of instructions simulated
 sim_seconds                                  2.431420                       # Number of seconds simulated
 sim_ticks                                2431419954000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  58156775000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997002                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              645854938                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9115236                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9111140                       # number of replacements
-system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  3061985                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               2431419954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1410228                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1996689457                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219344                       # Number of bytes of host memory used
+host_seconds                                  1217.73                       # Real time elapsed on the host
+sim_insts                                  1717270343                       # Number of instructions simulated
+system.physmem.bytes_read                   172766016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 75006720                       # Number of bytes written to this memory
+system.physmem.num_reads                      2699469                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1171980                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       71055605                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     16214                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      30848937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     101904542                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1717270343                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_fp_insts                            36                       # number of float instructions
+system.cpu.num_int_register_reads          9304894713                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_store_insts                  174847046                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      7                       # number of replacements
+system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.251403                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits             1544564961                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1544564961                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  638                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency       34804000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     32890000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             638                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     32890000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency     32890000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     32890000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              638                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.251403                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1544564961                       # number of overall hits
-system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  638                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     32890000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             638                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      7                       # number of replacements
-system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses         1889149                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9111140                       # number of replacements
+system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              645854938                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              9115236                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3061985                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  58156775000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2687066                       # number of replacements
+system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.458607                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.338956                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits              999241                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  46275216000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.471063                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses            889908                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency   94097172000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency  46275216000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses         3061985                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses         1889149                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.471063                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency 107978760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.296128                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.458607                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.338956                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2687066                       # number of replacements
-system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
-system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
-system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1717270343                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1536941850                       # number of integer instructions
-system.cpu.num_int_register_reads          9304894713                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
-system.cpu.num_load_insts                   485926770                       # Number of load instructions
-system.cpu.num_mem_refs                     660773816                       # number of memory refs
-system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 862679185..fe30d10a3 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,7 +69,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index bad0385b9..a5a0064e6 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:13:31
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 9b17b524e..6725100b8 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.846007                       # Number of seconds simulated
 sim_ticks                                2846007259500                       # Number of ticks simulated
+final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1508697                       # Simulator instruction rate (inst/s)
-host_tick_rate                              916127309                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234076                       # Number of bytes of host memory used
-host_seconds                                  3106.56                       # Real time elapsed on the host
+host_inst_rate                                2006575                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1218454030                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204704                       # Number of bytes of host memory used
+host_seconds                                  2335.75                       # Real time elapsed on the host
 sim_insts                                  4686862651                       # Number of instructions simulated
+system.physmem.bytes_read                 37129731755                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read            32105863408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1544656790                       # Number of bytes written to this memory
+system.physmem.num_reads                   5252417675                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   438528337                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    13046253354                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               11281019506                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     542745204                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13588998558                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                       5692014520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 90d473af2..e57f67518 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,7 +172,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index bfa3c0689..5d5232885 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:30:19
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 75fcf4f7a..94c5d24c6 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.923548                       # Number of seconds simulated
 sim_ticks                                5923548078000                       # Number of ticks simulated
+final_tick                               5923548078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 871353                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1101269643                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242804                       # Number of bytes of host memory used
-host_seconds                                  5378.84                       # Real time elapsed on the host
+host_inst_rate                                1176749                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1487248019                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213688                       # Number of bytes of host memory used
+host_seconds                                  3982.89                       # Real time elapsed on the host
 sim_insts                                  4686862651                       # Number of instructions simulated
+system.physmem.bytes_read                   173910080                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  43200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 75176384                       # Number of bytes written to this memory
+system.physmem.num_reads                      2717345                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1174631                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       29359107                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                      7293                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      12691107                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      42050214                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                      11847096156                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index e1977cd05..64fd65cd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 90052853e..ab1cbef0e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 17:47:44
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:57:18
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index e905042e7..db43e1bd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.041834                       # Number of seconds simulated
 sim_ticks                                 41833966000                       # Number of ticks simulated
+final_tick                                41833966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47398                       # Simulator instruction rate (inst/s)
-host_tick_rate                               21575287                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249684                       # Number of bytes of host memory used
-host_seconds                                  1938.98                       # Real time elapsed on the host
+host_inst_rate                                 111295                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50660994                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211656                       # Number of bytes of host memory used
+host_seconds                                   825.76                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                      316032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 178816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4938                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7554436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4274421                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       7554436                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 249041a4d..a6f9e5430 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2583cc940..9901dc40b 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:08:28
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index f77f26233..55d9dc21f 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.029167                       # Number of seconds simulated
 sim_ticks                                 29167093500                       # Number of ticks simulated
+final_tick                                29167093500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 127298                       # Simulator instruction rate (inst/s)
-host_tick_rate                               44106983                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209296                       # Number of bytes of host memory used
-host_seconds                                   661.28                       # Real time elapsed on the host
+host_inst_rate                                 155660                       # Simulator instruction rate (inst/s)
+host_tick_rate                               53933893                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212576                       # Number of bytes of host memory used
+host_seconds                                   540.79                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
+system.physmem.bytes_read                      332416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 193856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5194                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       11396953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   6646394                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      11396953                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 1801d3968..c3b5c0104 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 6101328db..887ca3f4e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:19:40
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index f61998e0c..af93195e1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.045952                       # Number of seconds simulated
 sim_ticks                                 45951567500                       # Number of ticks simulated
+final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3424834                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1712417014                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 187848                       # Number of bytes of host memory used
-host_seconds                                    26.83                       # Real time elapsed on the host
+host_inst_rate                                4191883                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2095941744                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 202544                       # Number of bytes of host memory used
+host_seconds                                    21.92                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                   475949877                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              367612356                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 30920974                       # Number of bytes written to this memory
+system.physmem.num_reads                    111899287                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     6501103                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10357641815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999995996                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     672903574                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11030545389                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index f2a594baf..2fe44f969 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index e569eee9e..84097b1db 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:46:11
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:54
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index c41863436..ba87aad33 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.118740                       # Number of seconds simulated
 sim_ticks                                118740049000                       # Number of ticks simulated
+final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1530436                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1977344021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 196484                       # Number of bytes of host memory used
-host_seconds                                    60.05                       # Real time elapsed on the host
+host_inst_rate                                2095418                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2707308980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211256                       # Number of bytes of host memory used
+host_seconds                                    43.86                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                      304960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 167744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4765                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2568299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1412699                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2568299                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index e5f29e92c..8db3f9119 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index e68aac2cc..bee9aa417 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:53:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:47:07
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
 Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
 Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 37554b8e7..4282a0231 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.105875                       # Number of seconds simulated
 sim_ticks                                105874925000                       # Number of ticks simulated
+final_tick                               105874925000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114442                       # Simulator instruction rate (inst/s)
-host_tick_rate                               64221605                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218340                       # Number of bytes of host memory used
-host_seconds                                  1648.59                       # Real time elapsed on the host
+host_inst_rate                                 103612                       # Simulator instruction rate (inst/s)
+host_tick_rate                               58144234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224188                       # Number of bytes of host memory used
+host_seconds                                  1820.90                       # Real time elapsed on the host
 sim_insts                                   188667572                       # Number of instructions simulated
+system.physmem.bytes_read                      240192                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 128512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3753                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2268639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1213810                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2268639                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 283406dc2..01def30a3 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index 03f12e59d..f2a9f0661 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,16 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:30:09
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:50:48
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index a4b991833..079a70f11 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1596483                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256912                       # Number of bytes of host memory used
-host_seconds                                   118.18                       # Real time elapsed on the host
-host_tick_rate                              872460307                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   188670900                       # Number of instructions simulated
 sim_seconds                                  0.103107                       # Number of seconds simulated
 sim_ticks                                103106771000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               103106771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3006793                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1643182108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213456                       # Number of bytes of host memory used
+host_seconds                                    62.75                       # Real time elapsed on the host
+sim_insts                                   188670900                       # Number of instructions simulated
+system.physmem.bytes_read                   869973902                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              759440240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 45252940                       # Number of bytes written to this memory
+system.physmem.num_reads                    219482514                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    12386694                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8437602047                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7365570977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     438893969                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    8876496016                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        206213543                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  206213543                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
-system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                        188670900                       # Number of instructions executed
 system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
 system.cpu.num_int_register_reads           809396650                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
-system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  206213543                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index c22086808..3f54c6512 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index a62fdd8f9..b21763742 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,16 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:31:09
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:52:01
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 022cf6be1..d861ddab1 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,279 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1108469                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 264128                       # Number of bytes of host memory used
-host_seconds                                   169.77                       # Real time elapsed on the host
-host_tick_rate                             1366998833                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   188185929                       # Number of instructions simulated
 sim_seconds                                  0.232077                       # Number of seconds simulated
 sim_ticks                                232077154000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               41962545                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 1789                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                     40                       # number of replacements
-system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 42007359                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       16                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                               232077154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1497030                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1846187485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222460                       # Number of bytes of host memory used
+host_seconds                                   125.71                       # Real time elapsed on the host
+sim_insts                                   188185929                       # Number of instructions simulated
+system.physmem.bytes_read                      220992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 110656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3453                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         952235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    476807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        952235                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        188185929                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_int_register_reads           898652287                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  464154308                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1506                       # number of replacements
+system.cpu.icache.tagsinuse               1147.981155                       # Cycle average of tags in use
+system.cpu.icache.total_refs                189857010                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits              189857010                       # number of ReadReq hits
+system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              189857010                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 3051                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency      115332000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3051                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    106179000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency    106179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000016                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             3051                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.000016                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              189857010                       # number of overall hits
-system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 3051                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    106179000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            3051                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   1506                       # number of replacements
-system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1147.981155                       # Cycle average of tags in use
-system.cpu.icache.total_refs                189857010                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     40                       # number of replacements
+system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 42007359                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               41962545                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1789                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       16                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses              1092                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
+system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3453                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency     122772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.713430                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                3453                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  464154308                       # Number of busy cycles
-system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
-system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        188185929                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
-system.cpu.num_int_insts                    150106226                       # number of integer instructions
-system.cpu.num_int_register_reads           898652287                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
-system.cpu.num_load_insts                    29849485                       # Number of load instructions
-system.cpu.num_mem_refs                      42494120                       # number of memory refs
-system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index b59640844..5551fc718 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index a36de6b20..5a1dc45d3 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:25:10
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 9a564c8ae..fabf573dd 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.096723                       # Number of seconds simulated
 sim_ticks                                 96722951500                       # Number of ticks simulated
+final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3820563                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1910292029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 200496                       # Number of bytes of host memory used
-host_seconds                                    50.63                       # Real time elapsed on the host
+host_inst_rate                                3381365                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1690691780                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210080                       # Number of bytes of host memory used
+host_seconds                                    57.21                       # Real time elapsed on the host
 sim_insts                                   193444769                       # Number of instructions simulated
+system.physmem.bytes_read                   997245606                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              773782192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 72065412                       # Number of bytes written to this memory
+system.physmem.num_reads                    251180617                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    18976439                       # Number of write requests responded to by this memory
+system.physmem.num_other                        22406                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10310330594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999985319                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     745070440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11055401034                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        193445904                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 6069e1413..2d0b36d34 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index 1a7df931f..e7f89f9a0 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:26:18
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 106cfd4f6..16bfeed42 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.270577                       # Number of seconds simulated
 sim_ticks                                270576960000                       # Number of ticks simulated
+final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2077025                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2905196336                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209472                       # Number of bytes of host memory used
-host_seconds                                    93.14                       # Real time elapsed on the host
+host_inst_rate                                1675606                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2343719954                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218792                       # Number of bytes of host memory used
+host_seconds                                   115.45                       # Real time elapsed on the host
 sim_insts                                   193444769                       # Number of instructions simulated
+system.physmem.bytes_read                      331072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 230208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5173                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        1223578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    850804                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       1223578                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        541153920                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index d20296793..0cd9938ef 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index a8f7791d3..1f9424384 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:52:38
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index f73117896..71e8505e4 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.096690                       # Number of seconds simulated
 sim_ticks                                 96689893000                       # Number of ticks simulated
+final_tick                                96689893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71082                       # Simulator instruction rate (inst/s)
-host_tick_rate                               31048201                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253148                       # Number of bytes of host memory used
-host_seconds                                  3114.19                       # Real time elapsed on the host
+host_inst_rate                                 118200                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51629155                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224032                       # Number of bytes of host memory used
+host_seconds                                  1872.78                       # Real time elapsed on the host
 sim_insts                                   221363017                       # Number of instructions simulated
+system.physmem.bytes_read                      340224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 215424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5316                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3518713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2227989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3518713                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        193379787                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 22a2b62b1..4d9868de9 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,7 +69,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index d0fe2b96b..3217ab200 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:24:02
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 727d7b7f0..39967f660 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.131393                       # Number of seconds simulated
 sim_ticks                                131393100000                       # Number of ticks simulated
+final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 733183                       # Simulator instruction rate (inst/s)
-host_tick_rate                              435191133                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241232                       # Number of bytes of host memory used
-host_seconds                                   301.92                       # Real time elapsed on the host
+host_inst_rate                                1953897                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1159762651                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211876                       # Number of bytes of host memory used
+host_seconds                                   113.29                       # Real time elapsed on the host
 sim_insts                                   221363018                       # Number of instructions simulated
+system.physmem.bytes_read                  1698379042                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1387955288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 99822189                       # Number of bytes written to this memory
+system.physmem.num_reads                    230176419                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    20515730                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    12925937831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               10563380330                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     759721698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13685659529                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        262786201                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 2acc29c81..d7a510398 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,7 +172,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index a9cb69d9f..a3170a407 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:26:06
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index d8ed7223d..1c9d2c1e6 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.250961                       # Number of seconds simulated
 sim_ticks                                250960631000                       # Number of ticks simulated
+final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 461238                       # Simulator instruction rate (inst/s)
-host_tick_rate                              522908265                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250008                       # Number of bytes of host memory used
-host_seconds                                   479.93                       # Real time elapsed on the host
+host_inst_rate                                1263573                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1432520595                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220856                       # Number of bytes of host memory used
+host_seconds                                   175.19                       # Real time elapsed on the host
 sim_insts                                   221363018                       # Number of instructions simulated
+system.physmem.bytes_read                      303040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 181760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4735                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        1207520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    724257                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       1207520                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 395184da9..409b736b6 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -19,7 +19,8 @@ init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
-memories=system.nvram system.physmem2 system.partition_desc system.physmem system.hypervisor_desc system.rom
+memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
 nvram_bin=/dist/m5/system/binaries/nvram1
@@ -41,20 +42,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[9]
 
 [system.bridge]
 type=Bridge
 delay=100
-filter_ranges_a=
-filter_ranges_b=
 nack_delay=8
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[14]
-side_b=system.membus.port[2]
+master=system.iobus.port[14]
+slave=system.membus.port[2]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -84,8 +83,8 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
-dcache_port=system.membus.port[10]
-icache_port=system.membus.port[9]
+dcache_port=system.membus.port[11]
+icache_port=system.membus.port[10]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -146,7 +145,7 @@ clock=2
 header_cycles=1
 use_default_range=false
 width=64
-port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio
+port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
 
 [system.membus]
 type=Bus
@@ -158,7 +157,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 6ef01a659..d81b5c20f 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,15 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 27 2011 04:34:45
-gem5 started Nov 27 2011 04:35:04
-gem5 executing on chips
+gem5 compiled Jan 23 2012 04:05:05
+gem5 started Jan 23 2012 06:26:23
+gem5 executing on zizzer
 command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing...
       0: system.t1000.htod: Real-time clock set to Thu Jan  1 00:00:00 2009
 
       0: system.t1000.htod: Real-time clock set to 1230768000
+info: No kernel set for full system simulation. Assuming you know what you're doing...
 info: Entering event queue @ 0.  Starting simulation...
 info: Ignoring write to SPARC ERROR regsiter
 info: Ignoring write to SPARC ERROR regsiter
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index a8935aa0a..21a50a501 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -2,12 +2,67 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.116889                       # Number of seconds simulated
 sim_ticks                                  2233777512                       # Number of ticks simulated
+final_tick                                 2233777512                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                 941153                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 943102                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 535596                       # Number of bytes of host memory used
-host_seconds                                  2368.54                       # Real time elapsed on the host
+host_inst_rate                                3505728                       # Simulator instruction rate (inst/s)
+host_tick_rate                                3512989                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 500940                       # Number of bytes of host memory used
+host_seconds                                   635.86                       # Real time elapsed on the host
 sim_insts                                  2229160714                       # Number of instructions simulated
+system.hypervisor_desc.bytes_read               16792                       # Number of bytes read from this memory
+system.hypervisor_desc.bytes_inst_read              0                       # Number of instructions bytes read from this memory
+system.hypervisor_desc.bytes_written                0                       # Number of bytes written to this memory
+system.hypervisor_desc.num_reads                 9024                       # Number of read requests responded to by this memory
+system.hypervisor_desc.num_writes                   0                       # Number of write requests responded to by this memory
+system.hypervisor_desc.num_other                    0                       # Number of other requests responded to by this memory
+system.hypervisor_desc.bw_read                  15035                       # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_total                 15035                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bytes_read                 9813991967                       # Number of bytes read from this memory
+system.physmem2.bytes_inst_read            8318106840                       # Number of instructions bytes read from this memory
+system.physmem2.bytes_written               897268422                       # Number of bytes written to this memory
+system.physmem2.num_reads                  2403489130                       # Number of read requests responded to by this memory
+system.physmem2.num_writes                  187387796                       # Number of write requests responded to by this memory
+system.physmem2.num_other                     5403067                       # Number of other requests responded to by this memory
+system.physmem2.bw_read                    8786901931                       # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_inst_read               7447569684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem2.bw_write                    803364182                       # Write bandwidth from this memory (bytes/s)
+system.physmem2.bw_total                   9590266113                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read                           284                       # Number of bytes read from this memory
+system.nvram.bytes_inst_read                        0                       # Number of instructions bytes read from this memory
+system.nvram.bytes_written                         92                       # Number of bytes written to this memory
+system.nvram.num_reads                            284                       # Number of read requests responded to by this memory
+system.nvram.num_writes                            92                       # Number of write requests responded to by this memory
+system.nvram.num_other                              0                       # Number of other requests responded to by this memory
+system.nvram.bw_read                              254                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write                              82                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total                             337                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read                 4846                       # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read               0                       # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written                 0                       # Number of bytes written to this memory
+system.partition_desc.num_reads                   608                       # Number of read requests responded to by this memory
+system.partition_desc.num_writes                    0                       # Number of write requests responded to by this memory
+system.partition_desc.num_other                     0                       # Number of other requests responded to by this memory
+system.partition_desc.bw_read                    4339                       # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total                   4339                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read                         1128688                       # Number of bytes read from this memory
+system.rom.bytes_inst_read                     432296                       # Number of instructions bytes read from this memory
+system.rom.bytes_written                            0                       # Number of bytes written to this memory
+system.rom.num_reads                           195123                       # Number of read requests responded to by this memory
+system.rom.num_writes                               0                       # Number of write requests responded to by this memory
+system.rom.num_other                                0                       # Number of other requests responded to by this memory
+system.rom.bw_read                            1010564                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read                        387054                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total                           1010564                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   709825348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              612291324                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 15400223                       # Number of bytes written to this memory
+system.physmem.num_reads                    165224885                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1927067                       # Number of write requests responded to by this memory
+system.physmem.num_other                           14                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      635538091                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 548211557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      13788502                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     649326593                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 56fbbd75c..b17544f09 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index d51796d4d..ba10334c5 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 15:20:58
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 118e4e630..4ce82e64f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
 sim_ticks                                    21216000                       # Number of ticks simulated
+final_tick                                   21216000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29106                       # Simulator instruction rate (inst/s)
-host_tick_rate                               96412699                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242900                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  36015                       # Simulator instruction rate (inst/s)
+host_tick_rate                              119302866                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207132                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       30016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          469                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     1414781297                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 907993967                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1414781297                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index d63a5e401..db5baf5c5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index 7a521752f..6e993ab1c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 15:52:45
-gem5 started Aug 20 2011 15:52:55
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 1aa86fca4..3b3d572bb 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
 sim_ticks                                    12004500                       # Number of ticks simulated
+final_tick                                   12004500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61962                       # Simulator instruction rate (inst/s)
-host_tick_rate                              116453376                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204272                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  38695                       # Simulator instruction rate (inst/s)
+host_tick_rate                               72731813                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208040                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
+system.physmem.bytes_read                       31040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  19904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          485                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2585697030                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1658044900                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2585697030                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 14af20ce8..df86e7077 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index c3032cdcb..9f50fe960 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:18:08
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index adb951856..7ceb6a8be 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     3215000                       # Number of ticks simulated
+final_tick                                    3215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 887593                       # Simulator instruction rate (inst/s)
-host_tick_rate                              444402423                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 183180                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  76916                       # Simulator instruction rate (inst/s)
+host_tick_rate                               38606134                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 198176                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10718506998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7980093313                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    2082737170                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12801244168                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index cd6b55738..b9fd9c5f2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_mem_ctrl_latency=1
 transitions_per_cycle=32
 version=0
@@ -119,7 +123,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -129,7 +133,8 @@ l1_response_latency=2
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 to_l2_latency=1
 transitions_per_cycle=32
 version=0
@@ -137,6 +142,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -145,11 +151,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -160,6 +182,7 @@ l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_l1_latency=1
 transitions_per_cycle=32
 version=0
@@ -167,6 +190,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -180,35 +204,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -218,6 +225,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -304,8 +312,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 658d83110..c2d3c97af 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:32:56
+Real time: Jan/23/2012 04:21:55
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
 
-Virtual_time_in_seconds: 0.59
-Virtual_time_in_minutes: 0.00983333
-Virtual_time_in_hours:   0.000163889
-Virtual_time_in_days:    6.8287e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours:   0.000105556
+Virtual_time_in_days:    4.39815e-06
 
 Ruby_current_time: 279353
 Ruby_start_time: 0
 Ruby_cycles: 279353
 
-mbytes_resident: 39.4609
-mbytes_total: 222.137
-resident_ratio: 0.177678
+mbytes_resident: 45.5547
+mbytes_total: 214.371
+resident_ratio: 0.212504
 
 ruby_cycles_executed: [ 279354 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11320
-page_faults: 0
+page_reclaims: 11862
+page_faults: 127
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 22816
+block_outputs: 96
 
 Network Stats
 -------------
@@ -198,20 +198,27 @@ links_utilized_percent_switch_3: 2.42686
   outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 691
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 691
   system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   691    100%
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 799
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 799
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   72.9662%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   27.0338%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   799    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -326,12 +333,17 @@ SINK_WB_ACK  L1_Replacement [0 ] 0
 SINK_WB_ACK  WB_Ack [0 ] 0
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 0
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_misses: 1460
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1460
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   39.0411%
+  system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   46.9863%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   13.9726%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   1460    100%
 
  --- L2Cache ---
  - Event Counts -
@@ -625,4 +637,5 @@ M_DWRI  Fetch [0 ] 0
 M_DWRI  Data [0 ] 0
 M_DWRI  Memory_Ack [0 ] 0
 M_DWRI  DMA_READ [0 ] 0
-M_DWRI  DMA_WRITE
\ No newline at end of file
+M_DWRI  DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 2f32125b9..c93c8f8af 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:32:19
-M5 started Apr 28 2011 14:32:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:21:53
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index d48699882..3bba58631 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  23386                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227472                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
-host_tick_rate                                1019507                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000279                       # Number of seconds simulated
 sim_ticks                                      279353                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                   2836                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 123728                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219520                       # Number of bytes of host memory used
+host_seconds                                     2.26                       # Real time elapsed on the host
+sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      123356470                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  91840789                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      23969673                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     147326143                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     868                       # DTB write accesses
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.itb.fetch_hits                        6415                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                           279353                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     279353                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             6404                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_fp_insts                            10                       # number of float instructions
 system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     279353                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index e475f8582..607ab419c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -118,7 +122,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -127,13 +131,15 @@ l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -142,11 +148,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -157,12 +179,14 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 response_latency=2
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -176,35 +200,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -214,6 +221,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -300,8 +308,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 0bc0d81dd..03b0eda65 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:49:15
+Real time: Jan/23/2012 04:22:13
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours:   0.000169444
-Virtual_time_in_days:    7.06019e-06
+Virtual_time_in_seconds: 0.39
+Virtual_time_in_minutes: 0.0065
+Virtual_time_in_hours:   0.000108333
+Virtual_time_in_days:    4.51389e-06
 
 Ruby_current_time: 223694
 Ruby_start_time: 0
 Ruby_cycles: 223694
 
-mbytes_resident: 39.6055
-mbytes_total: 222.41
-resident_ratio: 0.178127
+mbytes_resident: 45.5586
+mbytes_total: 214.484
+resident_ratio: 0.21241
 
 ruby_cycles_executed: [ 223695 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11338
-page_faults: 0
+page_reclaims: 11886
+page_faults: 121
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 21600
+block_outputs: 88
 
 Network Stats
 -------------
@@ -1466,4 +1466,5 @@ MD  PUTO [0 ] 0
 MD  PUTO_SHARERS [0 ] 0
 MD  DMA_READ [0 ] 0
 MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK
\ No newline at end of file
+MD  DMA_ACK [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 79291085b..ed47704f6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:48:31
-M5 started Apr 28 2011 14:49:14
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 63f11d46d..44a6426b2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  19980                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227752                       # Number of bytes of host memory used
-host_seconds                                     0.32                       # Real time elapsed on the host
-host_tick_rate                                 697544                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000224                       # Number of seconds simulated
 sim_ticks                                      223694                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  19611                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 684980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219636                       # Number of bytes of host memory used
+host_seconds                                     0.33                       # Real time elapsed on the host
+sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      154049729                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 114692392                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      29933749                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     183983477                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     868                       # DTB write accesses
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.itb.fetch_hits                        6415                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                           223694                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     223694                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             6404                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_fp_insts                            10                       # number of float instructions
 system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     223694                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 9d759f6bf..e664ed4cf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -87,6 +90,7 @@ l2_select_num_bits=0
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -121,7 +125,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 N_tokens=2
@@ -136,13 +140,15 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -151,11 +157,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -168,12 +190,14 @@ l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
 size=512
@@ -187,35 +211,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -225,6 +232,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -311,8 +319,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index c3749a713..216172e7b 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 15:03:53
+Real time: Jan/23/2012 04:22:26
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.55
-Virtual_time_in_minutes: 0.00916667
-Virtual_time_in_hours:   0.000152778
-Virtual_time_in_days:    6.36574e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours:   8.61111e-05
+Virtual_time_in_days:    3.58796e-06
 
 Ruby_current_time: 231701
 Ruby_start_time: 0
 Ruby_cycles: 231701
 
-mbytes_resident: 39.457
-mbytes_total: 222.211
-resident_ratio: 0.177618
+mbytes_resident: 44.0234
+mbytes_total: 212.691
+resident_ratio: 0.206983
 
 ruby_cycles_executed: [ 231702 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11316
-page_faults: 0
+page_reclaims: 11434
+page_faults: 122
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 21928
+block_outputs: 104
 
 Network Stats
 -------------
@@ -1039,4 +1039,5 @@ DR_L  Tokens [0 ] 0
 DR_L  Request_Timeout [0 ] 0
 DR_L  DMA_READ [0 ] 0
 DR_L  DMA_WRITE [0 ] 0
-DR_L  DMA_WRITE_All_Tokens
\ No newline at end of file
+DR_L  DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 8c53e7b8f..6ef144b06 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:03:17
-M5 started Apr 28 2011 15:03:52
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:25
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index a5ec386b7..4911f0b0e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  32190                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227548                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
-host_tick_rate                                1163713                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000232                       # Number of seconds simulated
 sim_ticks                                      231701                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  23819                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 861729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217800                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
+sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      148726160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 110728914                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      28899314                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     177625474                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     868                       # DTB write accesses
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.itb.fetch_hits                        6415                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                           231701                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     231701                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             6404                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_fp_insts                            10                       # number of float instructions
 system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     231701                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 3c544cad1..aa987ffa6 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -65,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -200,11 +201,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -288,8 +289,14 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index c8eb7f5d6..15beb0d93 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/10/2012 12:41:50
+Real time: Jan/23/2012 04:21:44
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.28
-Virtual_time_in_minutes: 0.00466667
-Virtual_time_in_hours:   7.77778e-05
-Virtual_time_in_days:    3.24074e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 208400
 Ruby_start_time: 0
 Ruby_cycles: 208400
 
-mbytes_resident: 39.0547
-mbytes_total: 234.742
-resident_ratio: 0.166439
+mbytes_resident: 43.3594
+mbytes_total: 212.09
+resident_ratio: 0.204439
 
 ruby_cycles_executed: [ 208401 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10898
-page_faults: 53
+page_reclaims: 11268
+page_faults: 126
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 22864
+block_outputs: 104
 
 Network Stats
 -------------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 88e64f8c5..fa89dfcd6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:41:49
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 76c45d699..dfbcac63c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000208                       # Number of seconds simulated
 sim_ticks                                      208400                       # Number of ticks simulated
+final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9071                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 295192                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240380                       # Number of bytes of host memory used
-host_seconds                                     0.71                       # Real time elapsed on the host
+host_inst_rate                                  24253                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 789193                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217184                       # Number of bytes of host memory used
+host_seconds                                     0.26                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      165355086                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 123109405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      32130518                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     197485605                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3c80d1144..0772d2ee5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=12
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -118,17 +122,43 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
+children=cacheMemory sequencer
 buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
 cache_response_latency=12
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -137,44 +167,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -184,6 +188,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -248,8 +253,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index a8866f347..c9b06e2ad 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:27:56
+Real time: Jan/23/2012 04:58:59
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours:   0.000122222
-Virtual_time_in_days:    5.09259e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 38.9805
-mbytes_total: 221.645
-resident_ratio: 0.175922
+mbytes_resident: 44.5703
+mbytes_total: 213.352
+resident_ratio: 0.208905
 
 ruby_cycles_executed: [ 342699 ]
 
@@ -122,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11208
-page_faults: 3
+page_reclaims: 11770
+page_faults: 1
 swaps: 0
-block_inputs: 1184
-block_outputs: 0
+block_inputs: 8
+block_outputs: 88
 
 Network Stats
 -------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 2.52117
   outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+  system.l1_cntrl0.cacheMemory_total_misses: 1730
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 1730
+  system.l1_cntrl0.cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   42.0231%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   15.7803%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   42.1965%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   42.0231%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   15.7803%
+  system.l1_cntrl0.cacheMemory_request_type_IFETCH:   42.1965%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   1730    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   1730    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -307,4 +307,5 @@ ID_W  PUTX [0 ] 0
 ID_W  PUTX_NotOwner [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 50fcbd6d8..9cf822901 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:26:41
-M5 started Apr 28 2011 14:27:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index d3a7d6e19..beb747c41 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  36559                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226968                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
-host_tick_rate                                1954466                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000343                       # Number of seconds simulated
 sim_ticks                                      342698                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     342698                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  32385                       # Simulator instruction rate (inst/s)
+host_tick_rate                                1732860                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218476                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
+system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      100555008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  74864750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      19539069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     120094077                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     868                       # DTB write accesses
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.itb.fetch_hits                        6415                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                           342698                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     342698                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             6404                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_fp_insts                            10                       # number of float instructions
 system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     342698                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 49928ea02..f51983ecf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index ae153f79d..d977e688b 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:43:56
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:58:59
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 73820fcfc..84a161e81 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000033                       # Number of seconds simulated
 sim_ticks                                    33007000                       # Number of ticks simulated
+final_tick                                   33007000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 622879                       # Simulator instruction rate (inst/s)
-host_tick_rate                             3204159632                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 191816                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 110064                       # Simulator instruction rate (inst/s)
+host_tick_rate                              566999999                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206896                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+system.physmem.bytes_read                       28544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          446                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      864786257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 539037174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     864786257                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index c7e464eb4..f0e8b9ebf 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index f41676f5c..2afd9a6f8 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 15:52:45
-gem5 started Aug 20 2011 15:52:55
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index d7cfe3b16..d94c5613d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000007                       # Number of seconds simulated
 sim_ticks                                     6833000                       # Number of ticks simulated
+final_tick                                    6833000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39761                       # Simulator instruction rate (inst/s)
-host_tick_rate                              113766137                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 203344                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  46364                       # Simulator instruction rate (inst/s)
+host_tick_rate                              132671945                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207164                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
+system.physmem.bytes_read                       17280                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  11840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          270                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2528903849                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1732767452                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2528903849                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 43e841230..fad1e21b6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 534040190..fdc12b275 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:00:19
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 50ec4667d..23e50fd7f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 343171                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194176                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              169102503                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
 sim_ticks                                     1297500                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 182014                       # Simulator instruction rate (inst/s)
+host_tick_rate                               91451888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 197324                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10293641618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7969171484                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1586127168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11879768786                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2596                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.itb.fetch_hits                        2585                       # ITB hits
 system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2596                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 system.cpu.numCycles                             2596                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       2596                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
 system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                       2596                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 255bc7bf6..89c8aeac1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_mem_ctrl_latency=1
 transitions_per_cycle=32
 version=0
@@ -119,7 +123,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -129,7 +133,8 @@ l1_response_latency=2
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 to_l2_latency=1
 transitions_per_cycle=32
 version=0
@@ -137,6 +142,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -145,11 +151,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -160,6 +182,7 @@ l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_l1_latency=1
 transitions_per_cycle=32
 version=0
@@ -167,6 +190,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -180,35 +204,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -218,6 +225,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -304,8 +312,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 475d0c631..1c4da6ce4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:32:56
+Real time: Jan/23/2012 04:21:58
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
 
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours:   0.000122222
-Virtual_time_in_days:    5.09259e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 104867
 Ruby_start_time: 0
 Ruby_cycles: 104867
 
-mbytes_resident: 38.1289
-mbytes_total: 221.148
-resident_ratio: 0.172449
+mbytes_resident: 43.0078
+mbytes_total: 212.113
+resident_ratio: 0.202759
 
 ruby_cycles_executed: [ 104868 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10981
+page_reclaims: 11317
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 88
 
 Network Stats
 -------------
@@ -198,20 +198,27 @@ links_utilized_percent_switch_3: 2.43896
   outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 300
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 300
   system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   300    100%
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 272
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 272
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   75%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   25%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   272    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -326,12 +333,17 @@ SINK_WB_ACK  L1_Replacement [0 ] 0
 SINK_WB_ACK  WB_Ack [0 ] 0
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 0
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_misses: 547
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 547
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   35.1005%
+  system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   53.1993%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   11.7002%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   547    100%
 
  --- L2Cache ---
  - Event Counts -
@@ -625,4 +637,5 @@ M_DWRI  Fetch [0 ] 0
 M_DWRI  Data [0 ] 0
 M_DWRI  Memory_Ack [0 ] 0
 M_DWRI  DMA_READ [0 ] 0
-M_DWRI  DMA_WRITE
\ No newline at end of file
+M_DWRI  DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 6b701bc22..dc0ba2922 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:32:19
-M5 started Apr 28 2011 14:32:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:21:56
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 78fb6974d..ebac3fa83 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  23624                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226460                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                 959767                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000105                       # Number of seconds simulated
 sim_ticks                                      104867                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     104867                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                   1196                       # Simulator instruction rate (inst/s)
+host_tick_rate                                  48657                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217208                       # Number of bytes of host memory used
+host_seconds                                     2.16                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      127361324                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  98601085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      19624858                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     146986182                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.itb.fetch_hits                        2586                       # ITB hits
 system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 system.cpu.numCycles                           104867                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     104867                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
 system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     104867                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index bc15f031c..e5748fef4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -118,7 +122,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -127,13 +131,15 @@ l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -142,11 +148,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -157,12 +179,14 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 response_latency=2
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -176,35 +200,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -214,6 +221,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -300,8 +308,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 2d6c597b0..f2273438f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:49:15
+Real time: Jan/23/2012 04:22:12
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours:   0.000119444
-Virtual_time_in_days:    4.97685e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours:   6.94444e-05
+Virtual_time_in_days:    2.89352e-06
 
 Ruby_current_time: 85418
 Ruby_start_time: 0
 Ruby_cycles: 85418
 
-mbytes_resident: 38.2812
-mbytes_total: 221.418
-resident_ratio: 0.172944
+mbytes_resident: 42.9688
+mbytes_total: 212.301
+resident_ratio: 0.202396
 
 ruby_cycles_executed: [ 85419 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11009
-page_faults: 0
+page_reclaims: 11325
+page_faults: 11
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1584
+block_outputs: 88
 
 Network Stats
 -------------
@@ -1466,4 +1466,5 @@ MD  PUTO [0 ] 0
 MD  PUTO_SHARERS [0 ] 0
 MD  DMA_READ [0 ] 0
 MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK
\ No newline at end of file
+MD  DMA_ACK [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 220322bcb..0529ad1d8 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:48:31
-M5 started Apr 28 2011 14:49:14
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index ec1a43e55..8d97fa8c6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  20652                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226736                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                 683514                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000085                       # Number of seconds simulated
 sim_ticks                                       85418                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  13096                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 434048                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217400                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      156360486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 121051769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      24093282                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     180453769                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.itb.fetch_hits                        2586                       # ITB hits
 system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 system.cpu.numCycles                            85418                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      85418                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
 system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                      85418                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 9580d477f..4c0569af0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -87,6 +90,7 @@ l2_select_num_bits=0
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -121,7 +125,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 N_tokens=2
@@ -136,13 +140,15 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -151,11 +157,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -168,12 +190,14 @@ l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
 size=512
@@ -187,35 +211,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -225,6 +232,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -311,8 +319,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 5aab6882e..2d266c770 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 15:03:52
+Real time: Jan/23/2012 04:22:26
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours:   0.000119444
-Virtual_time_in_days:    4.97685e-06
+Virtual_time_in_seconds: 0.22
+Virtual_time_in_minutes: 0.00366667
+Virtual_time_in_hours:   6.11111e-05
+Virtual_time_in_days:    2.5463e-06
 
 Ruby_current_time: 87899
 Ruby_start_time: 0
 Ruby_cycles: 87899
 
-mbytes_resident: 38.1484
-mbytes_total: 221.172
-resident_ratio: 0.172536
+mbytes_resident: 42.2227
+mbytes_total: 211.34
+resident_ratio: 0.199786
 
 ruby_cycles_executed: [ 87900 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10978
-page_faults: 0
+page_reclaims: 11088
+page_faults: 5
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1064
+block_outputs: 104
 
 Network Stats
 -------------
@@ -1032,4 +1032,5 @@ DR_L  Tokens [0 ] 0
 DR_L  Request_Timeout [0 ] 0
 DR_L  DMA_READ [0 ] 0
 DR_L  DMA_WRITE [0 ] 0
-DR_L  DMA_WRITE_All_Tokens
\ No newline at end of file
+DR_L  DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 4114133be..476a0b599 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:03:17
-M5 started Apr 28 2011 15:03:52
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:25
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 58dca509c..fd5600236 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  33219                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226484                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                                1130708                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000088                       # Number of seconds simulated
 sim_ticks                                       87899                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                      87899                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  12702                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 433208                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216416                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      151947121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 117635013                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      23413236                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     175360357                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.itb.fetch_hits                        2586                       # ITB hits
 system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 system.cpu.numCycles                            87899                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      87899                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
 system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                      87899                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index c04240cb3..209bb4d8d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -65,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -200,11 +201,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -288,8 +289,14 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index b81839414..452952d26 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/10/2012 12:42:00
+Real time: Jan/23/2012 04:21:49
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.21
-Virtual_time_in_minutes: 0.0035
-Virtual_time_in_hours:   5.83333e-05
-Virtual_time_in_days:    2.43056e-06
+Virtual_time_in_seconds: 0.23
+Virtual_time_in_minutes: 0.00383333
+Virtual_time_in_hours:   6.38889e-05
+Virtual_time_in_days:    2.66204e-06
 
 Ruby_current_time: 78448
 Ruby_start_time: 0
 Ruby_cycles: 78448
 
-mbytes_resident: 37.832
-mbytes_total: 233.867
-resident_ratio: 0.161817
+mbytes_resident: 41.5938
+mbytes_total: 210.898
+resident_ratio: 0.197222
 
 ruby_cycles_executed: [ 78449 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10644
+page_reclaims: 10974
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 01a9c1b54..20c68eff3 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:42:00
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 3836f9bae..5c579e1af 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000078                       # Number of seconds simulated
 sim_ticks                                       78448                       # Number of ticks simulated
+final_tick                                      78448                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54765                       # Simulator instruction rate (inst/s)
-host_tick_rate                                1666412                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239484                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  29294                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 891567                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215964                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      170252906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 131807057                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      26233938                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     196486845                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 2b74e07ae..2d5b16f7e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -84,6 +87,7 @@ directory_latency=12
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -118,17 +122,43 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
+children=cacheMemory sequencer
 buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
 cache_response_latency=12
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -137,44 +167,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -184,6 +188,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -248,8 +253,16 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 4b75a7bdf..2c26f3344 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:27:10
+Real time: Jan/23/2012 04:59:27
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours:   9.44444e-05
-Virtual_time_in_days:    3.93519e-06
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours:   6.66667e-05
+Virtual_time_in_days:    2.77778e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 37.6602
-mbytes_total: 220.656
-resident_ratio: 0.170727
+mbytes_resident: 42.25
+mbytes_total: 211.328
+resident_ratio: 0.199926
 
 ruby_cycles_executed: [ 123379 ]
 
@@ -122,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10875
-page_faults: 4
+page_reclaims: 11154
+page_faults: 0
 swaps: 0
-block_inputs: 2528
-block_outputs: 0
+block_inputs: 0
+block_outputs: 88
 
 Network Stats
 -------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 2.52881
   outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 626
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+  system.l1_cntrl0.cacheMemory_total_misses: 626
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 626
+  system.l1_cntrl0.cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   39.1374%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.4185%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   47.4441%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   39.1374%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   13.4185%
+  system.l1_cntrl0.cacheMemory_request_type_IFETCH:   47.4441%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   626    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   626    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -307,4 +307,5 @@ ID_W  PUTX [0 ] 0
 ID_W  PUTX_NotOwner [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 43151ea3c..af1c56980 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:26:41
-M5 started Apr 28 2011 14:27:10
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 9c0c161ed..bcff12bb9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,66 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  38181                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 225956                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                                1823203                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000123                       # Number of seconds simulated
 sim_ticks                                      123378                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                     123378                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                  44691                       # Simulator instruction rate (inst/s)
+host_tick_rate                                2138947                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216404                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
+system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      108252687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  83807486                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      16680445                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     124933132                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.itb.fetch_hits                        2586                       # ITB hits
 system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 system.cpu.numCycles                           123378                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     123378                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
 system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     123378                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 965487eb2..72df69882 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 363499d94..6a994fb76 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:24
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index a8a5eaa16..e3a7a00a0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,249 +1,259 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 195987                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201848                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             1258278911                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
 sim_ticks                                    16769000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses                415                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                    360                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.132530                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2915000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.132530                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   267                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       1512000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.091837                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  27                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      1431000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             27                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                 709                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                     627                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         4592000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.115656                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                    82                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      4346000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.115656                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses               82                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0             47.418751                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.011577                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses                709                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                    627                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        4592000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.115656                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                   82                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      4346000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.115656                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses              82                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 47.418751                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dtb.data_accesses                      717                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                          709                       # DTB hits
-system.cpu.dtb.data_misses                          8                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                                   16769000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 297044                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1928782837                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206044                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+sim_insts                                        2577                       # Number of instructions simulated
+system.physmem.bytes_read                       15680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  10432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          245                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      935058739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 622100304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     935058739                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      419                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          415                       # DTB read hits
 system.cpu.dtb.read_misses                          4                       # DTB read misses
-system.cpu.dtb.write_accesses                     298                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
-system.cpu.icache.ReadReq_accesses               2586                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
+system.cpu.itb.fetch_hits                        2586                       # ITB hits
+system.cpu.itb.fetch_misses                        11                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.numCycles                            33538                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
+system.cpu.num_func_calls                         140                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         2375                       # number of integer instructions
+system.cpu.num_fp_insts                             6                       # number of float instructions
+system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                           717                       # number of memory refs
+system.cpu.num_load_insts                         419                       # Number of load instructions
+system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                      33538                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      0                       # number of replacements
+system.cpu.icache.tagsinuse                 80.003762                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0             80.003762                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.039064                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits                   2423                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    2423                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   2423                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  163                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   163                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  163                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency        9128000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency         9128000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency        9128000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               2586                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                2586                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               2586                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.063032                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  163                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      8639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.063032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             163                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.063032                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.063032                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                2586                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    2423                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         9128000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.063032                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   163                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             163                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              163                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             163                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency      8639000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency      8639000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      8639000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.063032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.063032                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              163                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0             80.003762                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.039064                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses               2586                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.063032                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   2423                       # number of overall hits
-system.cpu.icache.overall_miss_latency        9128000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.063032                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  163                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      8639000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.063032                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             163                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                 80.003762                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                        2586                       # ITB hits
-system.cpu.itb.fetch_misses                        11                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses              27                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      1404000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 47.418751                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0             47.418751                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.011577                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                    360                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits                   267                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                     627                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                    627                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                  27                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                    82                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                   82                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       1512000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency         4592000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency        4592000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses                415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses                 709                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses                709                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.132530                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.091837                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.115656                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.115656                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses             27                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses               82                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses              82                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1431000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      4346000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      4346000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.132530                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.115656                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.115656                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse               107.101205                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           107.101205                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.003268                       # Average percentage of cache occupancy
+system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                     0                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 218                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses                27                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           27                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               218                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_misses                  245                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                 245                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency      11336000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1404000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       12740000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      12740000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses               218                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses              27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses                245                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses               245                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 218                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      8720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            218                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                245                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       12740000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  245                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses            218                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses             245                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses            245                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      8720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      1080000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency      9800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency      9800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             245                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           107.101205                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.003268                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses               245                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      12740000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 245                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      9800000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            245                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               107.101205                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            33538                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      33538                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 35f7f2ba7..21dc694d7 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 2cb4f1a9c..f402d7e9e 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 19:01:51
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index 3aaa40ec4..19b87b225 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000010                       # Number of seconds simulated
 sim_ticks                                    10001500                       # Number of ticks simulated
+final_tick                                   10001500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48143                       # Simulator instruction rate (inst/s)
-host_tick_rate                               83889434                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212568                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  15723                       # Simulator instruction rate (inst/s)
+host_tick_rate                               27400304                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218472                       # Number of bytes of host memory used
+host_seconds                                     0.37                       # Real time elapsed on the host
 sim_insts                                        5739                       # Number of instructions simulated
+system.physmem.bytes_read                       25856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  17856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          404                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2585212218                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1785332200                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2585212218                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 327106c53..1ee45ad85 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 974d1c8f4..13e73ddc3 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:32:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 1364619fb..8e7751fe7 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 931505                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 249344                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              451909477                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5739                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     2875500                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  25921                       # Simulator instruction rate (inst/s)
+host_tick_rate                               12986430                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208728                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
+sim_insts                                        5739                       # Number of instructions simulated
+system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     3648                       # Number of bytes written to this memory
+system.physmem.num_reads                         5771                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         924                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     7979134064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9247782994                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
 system.cpu.numCycles                             5752                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5752                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          793                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         185                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             5739                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                         185                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          793                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4985                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_int_register_reads               25237                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               5345                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1201                       # Number of load instructions
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2139                       # number of memory refs
+system.cpu.num_load_insts                        1201                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                       5752                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index 4214b8570..d881a3977 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index e4f30d324..25474862b 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:33:02
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index e792babc2..9108e20ee 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,264 +1,274 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 534023                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 257088                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2428466145                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5682                       # Number of instructions simulated
 sim_seconds                                  0.000026                       # Number of seconds simulated
 sim_ticks                                    26361000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits               11                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses               1147                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1049                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        4816000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.085440                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   98                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      4522000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.085440                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              98                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   870                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       2408000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  43                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      2279000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             43                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  13.765957                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2060                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51234.042553                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1919                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         7224000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.068447                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   141                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      6801000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.068447                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0             82.937979                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020249                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses               2060                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1919                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        7224000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.068447                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  141                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.068447                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 82.937979                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1941                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+final_tick                                   26361000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  20483                       # Simulator instruction rate (inst/s)
+host_tick_rate                               95024596                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217432                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
+sim_insts                                        5682                       # Number of instructions simulated
+system.physmem.bytes_read                       22400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  14400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          350                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      849740146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 546261523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     849740146                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses               4614                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.numCycles                            52722                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                             5682                       # Number of instructions executed
+system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                         185                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          793                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4985                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads               28701                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               5345                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                          2139                       # number of memory refs
+system.cpu.num_load_insts                        1201                       # Number of load instructions
+system.cpu.num_store_insts                        938                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                      52722                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.tagsinuse                114.525744                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     4373                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  18.145228                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            114.525744                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.055921                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits                   4373                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    4373                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   4373                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  241                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency       12824000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        12824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       12824000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               4614                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                4614                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               4614                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.052232                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.052232                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             241                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  18.145228                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.052232                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.052232                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 53211.618257                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 53211.618257                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 53211.618257                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                4614                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 53211.618257                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    4373                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        12824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.052232                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             241                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              241                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             241                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     12101000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency     12101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     12101000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.052232                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.052232                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              241                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            114.525744                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.055921                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses               4614                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 53211.618257                       # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate     0.052232                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   4373                       # number of overall hits
-system.cpu.icache.overall_miss_latency       12824000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.052232                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  241                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     12101000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.052232                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             241                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                114.525744                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     4373                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses              43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      2236000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses                43                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               339                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 82.937979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1941                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.765957                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0             82.937979                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020249                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   1049                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits                   870                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               11                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                    1919                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   1919                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                   98                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                  43                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                   141                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  141                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        4816000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       2408000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency         7224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency        7224000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1147                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses                2060                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2060                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.085440                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.047097                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.068447                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.068447                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 51234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 51234.042553                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses              98                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses             43                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses              141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses             141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      2279000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.085440                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.068447                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.068447                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse               153.954484                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      32                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           153.954484                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.004698                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                    32                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits                     32                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                    32                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 307                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses                43                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                  350                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                 350                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency      15964000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      2236000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       18200000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      18200000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses               339                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses              43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses                382                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses               382                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate         0.905605                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 307                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12280000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.905605                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            307                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.916230                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.916230                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                382                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                     32                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       18200000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.916230                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  350                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses            307                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses             350                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses            350                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     12280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      1720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency     14000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     14000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.905605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.916230                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             350                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           153.954484                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.004698                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses               382                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.916230                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                    32                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      18200000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.916230                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 350                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     14000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.916230                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            350                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               153.954484                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      32                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            52722                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      52722                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          793                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         185                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                             5682                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4985                       # number of integer instructions
-system.cpu.num_int_register_reads               28701                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5345                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1201                       # Number of load instructions
-system.cpu.num_mem_refs                          2139                       # number of memory refs
-system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index f9f4647e1..1ccb30b9c 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index 86af758df..677598e87 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:29
 gem5 executing on zizzer
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 844338a8e..78172e7b6 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
 sim_ticks                                    19785000                       # Number of ticks simulated
+final_tick                                   19785000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1139                       # Simulator instruction rate (inst/s)
-host_tick_rate                                3867528                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204696                       # Number of bytes of host memory used
-host_seconds                                     5.12                       # Real time elapsed on the host
+host_inst_rate                                  71616                       # Simulator instruction rate (inst/s)
+host_tick_rate                              243111037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208328                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  20288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          455                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     1471822087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1025423300                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1471822087                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index 6a2ff3124..508c3cad4 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index 1b7f6128f..eb1e6f70f 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:41
 gem5 executing on zizzer
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index 3721e6673..e49d82dd9 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
 sim_ticks                                    12272500                       # Number of ticks simulated
+final_tick                                   12272500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1003                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2382032                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205244                       # Number of bytes of host memory used
-host_seconds                                     5.15                       # Real time elapsed on the host
+host_inst_rate                                  65845                       # Simulator instruction rate (inst/s)
+host_tick_rate                              156294886                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208908                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
+system.physmem.bytes_read                       30400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  21312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          475                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2477082909                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1736565492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2477082909                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index fda15903b..8bad8df13 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 9eba211ea..4b9270f18 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:47
 gem5 executing on zizzer
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 6bf960444..397c3f1f6 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     2913500                       # Number of ticks simulated
+final_tick                                    2913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1129                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 564724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 195504                       # Number of bytes of host memory used
-host_seconds                                     5.16                       # Real time elapsed on the host
+host_inst_rate                                 231601                       # Simulator instruction rate (inst/s)
+host_tick_rate                              115720913                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 199128                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
+system.physmem.num_reads                         6992                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         925                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9503003261                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                8001372919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1255534580                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10758537841                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 41938cc87..e5b4b16c8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -7,9 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -136,6 +138,7 @@ version=0
 [system.l1_cntrl0.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -164,11 +167,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -252,8 +255,14 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index b0d2d6b62..f6eaf03f7 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:56
 gem5 executing on zizzer
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index fe1143095..65d0aed82 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000293                       # Number of seconds simulated
 sim_ticks                                      292960                       # Number of ticks simulated
+final_tick                                     292960                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1124                       # Simulator instruction rate (inst/s)
-host_tick_rate                                  56528                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213468                       # Number of bytes of host memory used
-host_seconds                                     5.18                       # Real time elapsed on the host
+host_inst_rate                                  55801                       # Simulator instruction rate (inst/s)
+host_tick_rate                                2804966                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220172                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
+system.physmem.num_reads                         6992                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         925                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       94507783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  79574003                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      12486346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     106994129                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 383b176d8..36444e22d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 09aaf2152..7525d1ad5 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 17 2011 12:31:33
-gem5 started Sep 17 2011 12:31:39
+gem5 compiled Jan 23 2012 03:56:13
+gem5 started Jan 23 2012 04:23:52
 gem5 executing on zizzer
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index 0e8242f31..566ce19a4 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000032                       # Number of seconds simulated
 sim_ticks                                    32088000                       # Number of ticks simulated
+final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1128                       # Simulator instruction rate (inst/s)
-host_tick_rate                                6214306                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204312                       # Number of bytes of host memory used
-host_seconds                                     5.16                       # Real time elapsed on the host
+host_inst_rate                                 263412                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1449372115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207940                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+system.physmem.bytes_read                       28096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          439                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      875592122                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 600349040                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     875592122                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index a3775a1dd..fb36c719f 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -103,6 +105,7 @@ smtNumFetchingThreads=1
 smtROBPolicy=Partitioned
 smtROBThreshold=100
 squashWidth=8
+store_set_clear_period=250000
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -477,7 +480,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +503,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +522,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +532,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index d1cb3e246..8cb241542 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 15 2011 17:49:29
-gem5 started Jul 15 2011 20:14:11
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 03:58:39
+gem5 started Jan 23 2012 04:24:00
+gem5 executing on zizzer
 command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index bac6ac3e3..5a2ad1a0a 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000011                       # Number of seconds simulated
 sim_ticks                                    10910500                       # Number of ticks simulated
+final_tick                                   10910500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31106                       # Simulator instruction rate (inst/s)
-host_tick_rate                               58503850                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241340                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  80565                       # Simulator instruction rate (inst/s)
+host_tick_rate                              151515044                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205800                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
+system.physmem.bytes_read                       28608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  22016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          447                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2622061317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                2017872691                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2622061317                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
index c4bee2b32..f4325cdae 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +48,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=PowerTLB
@@ -86,7 +89,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +99,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index c3d9ac55b..e45cd058f 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 30329336. This will break if not /dev/zero.
-For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index 86b3ce749..ef2f9ace6 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:26
-M5 started Apr 19 2011 12:19:32
-M5 executing on maize
-command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
+gem5 compiled Jan 23 2012 03:58:39
+gem5 started Jan 23 2012 04:24:03
+gem5 executing on zizzer
+command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index c1d1657bb..5070ee2a1 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,52 +1,63 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 259061                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193868                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              128464915                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5801                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     2900000                       # Number of ticks simulated
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 305071                       # Simulator instruction rate (inst/s)
+host_tick_rate                              152367478                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 196296                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+sim_insts                                        5801                       # Number of instructions simulated
+system.physmem.bytes_read                       26925                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  23204                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     4209                       # Number of bytes written to this memory
+system.physmem.num_reads                         6763                       # Number of read requests responded to by this memory
+system.physmem.num_writes                        1046                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9284482759                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                8001379310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1451379310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10735862069                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                    9                       # Number of system calls
 system.cpu.numCycles                             5801                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5801                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          896                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
-system.cpu.num_fp_insts                            22                       # number of float instructions
-system.cpu.num_fp_register_reads                   20                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         200                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             5801                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  5706                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
+system.cpu.num_func_calls                         200                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          896                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         5706                       # number of integer instructions
+system.cpu.num_fp_insts                            22                       # number of float instructions
 system.cpu.num_int_register_reads                9541                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               5005                       # number of times the integer registers were written
-system.cpu.num_load_insts                         962                       # Number of load instructions
+system.cpu.num_fp_register_reads                   20                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2008                       # number of memory refs
+system.cpu.num_load_insts                         962                       # Number of load instructions
 system.cpu.num_store_insts                       1046                       # Number of store instructions
-system.cpu.workload.num_syscalls                    9                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                       5801                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
index f7a4ddc40..32a7f4ad9 100644
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/sysexplr/dist/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
index 002338518..024efc4d5 100755
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  9 2011 14:58:11
-gem5 started Jul  9 2011 15:02:19
-gem5 executing on nadc-0321
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:09
+gem5 executing on zizzer
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 1b5682411..1ce5039d0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000018                       # Number of seconds simulated
 sim_ticks                                    18201500                       # Number of ticks simulated
+final_tick                                   18201500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  63270                       # Simulator instruction rate (inst/s)
-host_tick_rate                              215616708                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249768                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  29731                       # Simulator instruction rate (inst/s)
+host_tick_rate                              101330259                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213072                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+system.physmem.bytes_read                       27072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  18496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          423                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     1487349944                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1016179985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1487349944                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            36404                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index fe9f8a548..8aa4dc707 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index a3abc632d..9cbff76e8 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:20:06
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:11
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index fcb8d359c..57eaeacb0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     2701000                       # Number of ticks simulated
+final_tick                                    2701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639191                       # Simulator instruction rate (inst/s)
-host_tick_rate                              322368277                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216400                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 117056                       # Simulator instruction rate (inst/s)
+host_tick_rate                               59184907                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 203964                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
+system.physmem.num_reads                         6099                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         673                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9676045909                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7971862273                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1875231396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11551277305                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                             5403                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index aacea45cb..e13b78d74 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +44,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -78,11 +81,13 @@ uid=100
 type=Directory_Controller
 children=directory memBuffer
 buffer_size=0
+cntrl_id=1
 directory=system.dir_cntrl0.directory
 directory_latency=12
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -117,16 +122,43 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
+children=cacheMemory sequencer
 buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
 cache_response_latency=12
+cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -135,44 +167,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -180,59 +186,83 @@ children=topology
 adaptive_routing=false
 buffer_size=0
 control_msg_size=8
-endpoint_bandwidth=10000
-link_latency=1
+endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-num_int_nodes=3
 print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
 
 [system.ruby.network.topology.ext_links0]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=0
+int_node=system.ruby.network.topology.routers0
 latency=1
+link_id=0
 weight=1
 
 [system.ruby.network.topology.ext_links1]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=1
+int_node=system.ruby.network.topology.routers1
 latency=1
+link_id=1
 weight=1
 
 [system.ruby.network.topology.int_links0]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
 latency=1
-node_a=0
-node_b=2
+link_id=2
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
 weight=1
 
 [system.ruby.network.topology.int_links1]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
 latency=1
-node_a=1
-node_b=2
+link_id=3
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index e4482bc0d..d48e9e1d8 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/19/2011 12:21:28
+Real time: Jan/23/2012 04:24:20
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.16
-Virtual_time_in_minutes: 0.00266667
-Virtual_time_in_hours:   4.44444e-05
-Virtual_time_in_days:    1.85185e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 38.7109
-mbytes_total: 208.668
-resident_ratio: 0.185533
+mbytes_resident: 45.418
+mbytes_total: 219.465
+resident_ratio: 0.206949
 
 ruby_cycles_executed: [ 253365 ]
 
@@ -122,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10204
-page_faults: 0
+page_reclaims: 12012
+page_faults: 1
 swaps: 0
-block_inputs: 0
-block_outputs: 64
+block_inputs: 152
+block_outputs: 88
 
 Network Stats
 -------------
@@ -139,9 +139,9 @@ total_msgs: 15444 total_bytes: 617760
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.158621
-  links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 2.53982
+  links_utilized_percent_switch_0_link_0: 2.54298 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.53667 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
@@ -150,9 +150,9 @@ links_utilized_percent_switch_0: 0.158621
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.158857
-  links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 2.53982
+  links_utilized_percent_switch_1_link_0: 2.53667 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.54298 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
@@ -161,27 +161,27 @@ links_utilized_percent_switch_1: 0.158857
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.253982
-  links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 2.53982
+  links_utilized_percent_switch_2_link_0: 2.54298 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.53667 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+  system.l1_cntrl0.cacheMemory_total_misses: 1289
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 1289
+  system.l1_cntrl0.cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   30.6439%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.8867%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   55.4694%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   30.6439%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   13.8867%
+  system.l1_cntrl0.cacheMemory_request_type_IFETCH:   55.4694%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   1289    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   1289    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -227,9 +227,9 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_reads: 1289
   memory_writes: 1285
   memory_refreshes: 528
-  memory_total_request_delays: 3552
-  memory_delays_per_request: 1.37995
-  memory_delays_in_input_queue: 1284
+  memory_total_request_delays: 2936
+  memory_delays_per_request: 1.14064
+  memory_delays_in_input_queue: 668
   memory_delays_behind_head_of_bank_queue: 3
   memory_delays_stalled_at_head_of_bank_queue: 2265
   memory_stalls_for_bank_busy: 847
@@ -307,4 +307,5 @@ ID_W  PUTX [0 ] 0
 ID_W  PUTX_NotOwner [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index facf1db54..8b55b99bf 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:21:28
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:20
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 253364 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 44c0d650a..5fbe4680b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000253                       # Number of seconds simulated
 sim_ticks                                      253364                       # Number of ticks simulated
+final_tick                                     253364                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54602                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2590295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234524                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  57666                       # Simulator instruction rate (inst/s)
+host_tick_rate                                2735530                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224736                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
+system.physmem.num_reads                         6099                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         673                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      103151987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  84984449                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      19991001                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     123142988                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 87bc655de..31f964ca0 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 3cc40bf72..a3d57b80d 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:21:23
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:14
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index a8d6eb9ee..0e1d1294b 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000028                       # Number of seconds simulated
 sim_ticks                                    28206000                       # Number of ticks simulated
+final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 272526                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1437682899                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225224                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 103151                       # Simulator instruction rate (inst/s)
+host_tick_rate                              544654705                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212680                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+system.physmem.bytes_read                       24896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  16320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          389                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      882649082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 578600298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     882649082                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
index 9ae1576ae..8582c91b4 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -500,7 +502,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index e8531dc26..4c371922e 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:37
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index e3bb4b417..e2df7b059 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000011                       # Number of seconds simulated
 sim_ticks                                    11087000                       # Number of ticks simulated
+final_tick                                   11087000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74834                       # Simulator instruction rate (inst/s)
-host_tick_rate                               84571612                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239776                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  31087                       # Simulator instruction rate (inst/s)
+host_tick_rate                               35135175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212404                       # Number of bytes of host memory used
+host_seconds                                     0.32                       # Real time elapsed on the host
 sim_insts                                        9809                       # Number of instructions simulated
+system.physmem.bytes_read                       28288                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  18944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          442                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     2551456661                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1708667809                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2551456661                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            22175                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index b1b2b6764..e5a1ce348 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
@@ -67,7 +69,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 65af79972..de652c174 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:38
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 2f19e2e68..e2f539833 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000006                       # Number of seconds simulated
 sim_ticks                                     5651000                       # Number of ticks simulated
+final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 855797                       # Simulator instruction rate (inst/s)
-host_tick_rate                              492033087                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229652                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 225004                       # Simulator instruction rate (inst/s)
+host_tick_rate                              129531520                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 202604                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        9810                       # Number of instructions simulated
+system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
+system.physmem.num_reads                         7966                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         934                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11033091488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                9782339409                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1258184392                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12291275880                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            11303                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 752669beb..3ef5774b9 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -7,9 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -64,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -165,11 +167,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -253,8 +255,14 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index b05082262..33342e3e3 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/09/2012 14:28:32
+Real time: Jan/23/2012 04:24:44
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.31
-Virtual_time_in_minutes: 0.00516667
-Virtual_time_in_hours:   8.61111e-05
-Virtual_time_in_days:    3.58796e-06
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours:   7.5e-05
+Virtual_time_in_days:    3.125e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 40.0625
-mbytes_total: 241.918
-resident_ratio: 0.165652
+mbytes_resident: 46.1367
+mbytes_total: 218.203
+resident_ratio: 0.211439
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -125,11 +125,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11175
-page_faults: 4
+page_reclaims: 12102
+page_faults: 2
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 144
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 52f9aeb2f..9c1cf6357 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:43
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 58cff044f..49089d227 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000276                       # Number of seconds simulated
 sim_ticks                                      276484                       # Number of ticks simulated
+final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73084                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2059440                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247728                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  88128                       # Simulator instruction rate (inst/s)
+host_tick_rate                                2483404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223444                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        9810                       # Number of instructions simulated
+system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
+system.physmem.num_reads                         7966                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         934                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      225503103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 199939237                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      25715774                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     251218877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index acea7ec29..36b722b34 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -170,7 +172,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 045ceeef4..074c5468c 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 14:18:02
-gem5 started Jan  9 2012 14:28:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 04:24:38
+gem5 executing on zizzer
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index eb8aa1f61..dcf7af574 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000029                       # Number of seconds simulated
 sim_ticks                                    28768000                       # Number of ticks simulated
+final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 524711                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1537080573                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238628                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 320748                       # Simulator instruction rate (inst/s)
+host_tick_rate                              940055576                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211332                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        9810                       # Number of instructions simulated
+system.physmem.bytes_read                       23104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  14528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          361                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      803114572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 505005562                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     803114572                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            57536                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 1ccf88e60..5ef0030d0 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -538,7 +540,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -548,5 +550,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 37b9b37a2..ab4ed6a09 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 15:52:45
-gem5 started Aug 20 2011 15:52:54
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:27
 gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index e427b5b96..6ec84dd27 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
 sim_ticks                                    13202000                       # Number of ticks simulated
+final_tick                                   13202000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58060                       # Simulator instruction rate (inst/s)
-host_tick_rate                               60004972                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204840                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  76140                       # Simulator instruction rate (inst/s)
+host_tick_rate                               78688554                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208616                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                       12773                       # Number of instructions simulated
+system.physmem.bytes_read                       62144                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  39936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          971                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     4707165581                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                3024996213                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    4707165581                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index 7ee142626..7db48bf0e 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/sysexplr/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout
index 64331370b..38fdee473 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  9 2011 14:58:11
-gem5 started Jul  9 2011 15:02:19
-gem5 executing on nadc-0321
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:21
+gem5 executing on zizzer
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 10d7a8655..7b0904682 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000025                       # Number of seconds simulated
 sim_ticks                                    25058500                       # Number of ticks simulated
+final_tick                                   25058500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66853                       # Simulator instruction rate (inst/s)
-host_tick_rate                              110387436                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249432                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  55020                       # Simulator instruction rate (inst/s)
+host_tick_rate                               90849063                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212976                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+system.physmem.bytes_read                       27904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  19072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          436                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     1113554283                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 761099028                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1113554283                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            50118                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 6736c2ed4..6652fe60b 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -519,7 +521,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index bc80135e3..14970f00a 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 20 2011 13:07:22
-gem5 started Aug 20 2011 13:07:32
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:22
 gem5 executing on zizzer
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index ea9aaaf42..3a1cfc4e9 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000018                       # Number of seconds simulated
 sim_ticks                                    18114000                       # Number of ticks simulated
+final_tick                                   18114000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   2357                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2955469                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210004                       # Number of bytes of host memory used
-host_seconds                                     6.13                       # Real time elapsed on the host
+host_inst_rate                                  74785                       # Simulator instruction rate (inst/s)
+host_tick_rate                               93746300                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213808                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
+system.physmem.bytes_read                       30464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  21120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          476                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     1681793088                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1165948990                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1681793088                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            36229                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 15ddd6551..421dd8a46 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -85,7 +88,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index c90052363..df7964c68 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:21:33
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:24
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 070242574..389636d62 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000008                       # Number of seconds simulated
 sim_ticks                                     7618500                       # Number of ticks simulated
+final_tick                                    7618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 391175                       # Simulator instruction rate (inst/s)
-host_tick_rate                              196252250                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216204                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 296178                       # Simulator instruction rate (inst/s)
+host_tick_rate                              148615294                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 203776                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+system.physmem.bytes_read                       72223                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  60880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     9042                       # Number of bytes written to this memory
+system.physmem.num_reads                        17446                       # Number of read requests responded to by this memory
+system.physmem.num_writes                        1442                       # Number of write requests responded to by this memory
+system.physmem.num_other                            6                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9479950121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7991074358                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1186847805                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10666797926                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            15238                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index e5ac7d1dd..fb5a1cb83 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -188,7 +191,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 8aa153829..d982745c0 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:20:31
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:28
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index ad7479276..f52890637 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000042                       # Number of seconds simulated
 sim_ticks                                    41800000                       # Number of ticks simulated
+final_tick                                   41800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 434801                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1196840935                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225108                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 146106                       # Simulator instruction rate (inst/s)
+host_tick_rate                              402347608                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212484                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+system.physmem.bytes_read                       26624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          416                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      636937799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 425645933                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     636937799                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            83600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index b9ee6d3dc..bd95bae49 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -15,6 +15,8 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
@@ -28,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -314,7 +314,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -345,8 +345,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -378,7 +378,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -390,10 +390,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -539,12 +540,13 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -561,6 +563,7 @@ pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -577,6 +580,7 @@ pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -593,6 +597,7 @@ pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -609,6 +614,7 @@ pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -625,6 +631,7 @@ pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -641,6 +648,7 @@ pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -657,6 +665,7 @@ pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -673,6 +682,7 @@ pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -689,6 +699,7 @@ pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -705,6 +716,7 @@ pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -721,6 +733,7 @@ pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -737,6 +750,7 @@ pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -753,6 +767,7 @@ pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -769,6 +784,7 @@ pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -785,6 +801,7 @@ pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -801,6 +818,7 @@ pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -817,6 +835,7 @@ pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -833,6 +852,7 @@ pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -908,8 +928,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 0372a3b05..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -1,9 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 9887f002f..dbef4ddb7 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:17:36
-M5 started Apr 19 2011 12:18:19
-M5 executing on maize
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 04:22:39
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index b94a40430..c3dae4684 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,880 +1,891 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4662508                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292496                       # Number of bytes of host memory used
-host_seconds                                    13.55                       # Real time elapsed on the host
-host_tick_rate                           138080405600                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
 sim_ticks                                1870335522500                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses::0       188297                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_hits::0       172138                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       172138                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085817                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        16159                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        16159                       # number of LoadLockedReq misses
-system.cpu0.dcache.ReadReq_accesses::0        8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits::0            7298106                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7298106                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate::0      0.187444                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0          1683563                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1683563                       # number of ReadReq misses
-system.cpu0.dcache.StoreCondReq_accesses::0       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits::0        186635                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       186635                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003753                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0          703                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          703                       # number of StoreCondReq misses
-system.cpu0.dcache.WriteReq_accesses::0       5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits::0           5462265                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5462265                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate::0     0.049753                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0          285996                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       285996                       # number of WriteReq misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            12760371                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12760371                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.133711                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           1969559                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1969559                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_blocks::0           504.827058                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.985990                       # Average percentage of cache occupancy
-system.cpu0.dcache.overall_accesses::0       14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           12760371                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12760371                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.133711                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          1969559                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1969559                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1978962                       # number of replacements
-system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  771740                       # number of writebacks
-system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
-system.cpu0.dtb.data_acv                          251                       # DTB access violations
-system.cpu0.dtb.data_hits                    15091429                       # DTB hits
-system.cpu0.dtb.data_misses                      7805                       # DTB misses
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
-system.cpu0.dtb.read_acv                          152                       # DTB read access violations
-system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
-system.cpu0.dtb.read_misses                      7079                       # DTB read misses
-system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
-system.cpu0.dtb.write_acv                          99                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
-system.cpu0.dtb.write_misses                      726                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses::0       57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits::0           56345132                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate::0      0.015464                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           885000                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       885000                       # number of ReadReq misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0        57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0            56345132                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        56345132                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.015464                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            885000                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        885000                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_blocks::0           511.244754                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.998525                       # Average percentage of cache occupancy
-system.cpu0.icache.overall_accesses::0       57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0           56345132                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total       56345132                       # number of overall hits
-system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.015464                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           885000                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       885000                       # number of overall misses
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                884404                       # number of replacements
-system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                      95                       # number of writebacks
-system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
-system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
-system.cpu0.itb.fetch_misses                     3485                       # ITB misses
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  110      0.06%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3762      2.05%      2.11% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               168035     91.68%     93.82% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6150      3.36%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                183291                       # number of callpals executed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0                   71004     40.60%     40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 101705     58.16%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              174868                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               141425                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            17242445000      0.92%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1870335315000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.980748                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1157                      
-system.cpu0.kern.mode_good::user                 1158                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch::kernel             7091                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1158                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
-system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
-system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     14.16%     26.11% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.44%     26.55% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.44%     26.99% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      3.98%     30.97% # number of syscalls executed
-system.cpu0.kern.syscall::19                        8      3.54%     34.51% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.65%     37.17% # number of syscalls executed
-system.cpu0.kern.syscall::23                        2      0.88%     38.05% # number of syscalls executed
-system.cpu0.kern.syscall::24                        4      1.77%     39.82% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.10%     42.92% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.88%     43.81% # number of syscalls executed
-system.cpu0.kern.syscall::45                       37     16.37%     60.18% # number of syscalls executed
-system.cpu0.kern.syscall::47                        4      1.77%     61.95% # number of syscalls executed
-system.cpu0.kern.syscall::48                        8      3.54%     65.49% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.42%     69.91% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.44%     70.35% # number of syscalls executed
-system.cpu0.kern.syscall::59                        4      1.77%     72.12% # number of syscalls executed
-system.cpu0.kern.syscall::71                       30     13.27%     85.40% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.33%     86.73% # number of syscalls executed
-system.cpu0.kern.syscall::74                        8      3.54%     90.27% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.44%     90.71% # number of syscalls executed
-system.cpu0.kern.syscall::90                        2      0.88%     91.59% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.98%     95.58% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.88%     96.46% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.88%     97.35% # number of syscalls executed
-system.cpu0.kern.syscall::132                       2      0.88%     98.23% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
-system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
-system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles              57233843.686322                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
-system.cpu0.num_fp_insts                       299810                       # number of float instructions
-system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
-system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles              3683437089.313678                       # Number of idle cycles
-system.cpu0.num_insts                        57222076                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
-system.cpu0.num_int_insts                    53249924                       # number of integer instructions
-system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
-system.cpu0.num_load_insts                    9184477                       # Number of load instructions
-system.cpu0.num_mem_refs                     15135515                       # number of memory refs
-system.cpu0.num_store_insts                   5951038                       # Number of store instructions
-system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        15129                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.078511                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0         1289                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         1289                       # number of LoadLockedReq misses
-system.cpu1.dcache.ReadReq_accesses::0        1150965                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits::0            1109315                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1109315                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate::0      0.036187                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0            41650                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        41650                       # number of ReadReq misses
-system.cpu1.dcache.StoreCondReq_accesses::0        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_hits::0         15613                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        15613                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044784                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0          732                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          732                       # number of StoreCondReq misses
-system.cpu1.dcache.WriteReq_accesses::0        733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits::0            707444                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        707444                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate::0     0.035266                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0           25861                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        25861                       # number of WriteReq misses
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             1816759                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1816759                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.035829                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0             67511                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         67511                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_blocks::0           391.951263                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.765530                       # Average percentage of cache occupancy
-system.cpu1.dcache.overall_accesses::0        1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            1816759                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1816759                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.035829                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0            67511                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        67511                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                 62338                       # number of replacements
-system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   39996                       # number of writebacks
-system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
-system.cpu1.dtb.data_acv                          116                       # DTB access violations
-system.cpu1.dtb.data_hits                     1914885                       # DTB hits
-system.cpu1.dtb.data_misses                      3692                       # DTB misses
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
-system.cpu1.dtb.read_acv                           58                       # DTB read access violations
-system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
-system.cpu1.dtb.read_misses                      3277                       # DTB read misses
-system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
-system.cpu1.dtb.write_acv                          58                       # DTB write access violations
-system.cpu1.dtb.write_hits                     751446                       # DTB write hits
-system.cpu1.dtb.write_misses                      415                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses::0        5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits::0            5832136                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate::0      0.017459                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0           103630                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       103630                       # number of ReadReq misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                 56.293119                       # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0         5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0             5832136                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5832136                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.017459                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0            103630                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        103630                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_blocks::0           427.126317                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.834231                       # Average percentage of cache occupancy
-system.cpu1.icache.overall_accesses::0        5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0            5832136                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5832136                       # number of overall hits
-system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.017459                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0           103630                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       103630                       # number of overall misses
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                103091                       # number of replacements
-system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               427.126317                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 5832136                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                      15                       # number of writebacks
-system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
-system.cpu1.itb.fetch_acv                          57                       # ITB acv
-system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
-system.cpu1.itb.fetch_misses                     1539                       # ITB misses
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    8      0.02%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  470      1.46%      1.50% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      15      0.05%      1.54% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.57% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                26238     81.66%     83.22% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2576      8.02%     91.24% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.25% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     91.26% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.01%     91.26% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     91.27% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2607      8.11%     99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 158      0.49%     99.88% # number of callpals executed
-system.cpu1.kern.callpal::imb                      38      0.12%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 32131                       # number of callpals executed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count::0                   10328     33.46%     33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1907      6.18%     39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    110      0.36%     40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  18518     60.00%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               30863                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    10318     45.77%     45.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1907      8.46%     54.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                22543                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1859123008500     99.41%     99.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               14064500      0.00%     99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            10905353000      0.58%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1870124427000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.999032                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.551247                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel                612                      
-system.cpu1.kern.mode_good::user                  580                      
-system.cpu1.kern.mode_good::idle                   32                      
-system.cpu1.kern.mode_switch::kernel             1033                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                580                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel     0.592449                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.608089                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        1373917500      0.07%      0.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1868002549000     99.90%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
-system.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
-system.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
-system.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10     10.00%     25.00% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      6.00%     31.00% # number of syscalls executed
-system.cpu1.kern.syscall::19                        2      2.00%     33.00% # number of syscalls executed
-system.cpu1.kern.syscall::23                        2      2.00%     35.00% # number of syscalls executed
-system.cpu1.kern.syscall::24                        2      2.00%     37.00% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      4.00%     41.00% # number of syscalls executed
-system.cpu1.kern.syscall::45                       17     17.00%     58.00% # number of syscalls executed
-system.cpu1.kern.syscall::47                        2      2.00%     60.00% # number of syscalls executed
-system.cpu1.kern.syscall::48                        2      2.00%     62.00% # number of syscalls executed
-system.cpu1.kern.syscall::59                        3      3.00%     65.00% # number of syscalls executed
-system.cpu1.kern.syscall::71                       24     24.00%     89.00% # number of syscalls executed
-system.cpu1.kern.syscall::74                        8      8.00%     97.00% # number of syscalls executed
-system.cpu1.kern.syscall::90                        1      1.00%     98.00% # number of syscalls executed
-system.cpu1.kern.syscall::132                       2      2.00%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
-system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
-system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              5936690.922345                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
-system.cpu1.num_fp_insts                        28590                       # number of float instructions
-system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
-system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles              3734312190.077655                       # Number of idle cycles
-system.cpu1.num_insts                         5931958                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
-system.cpu1.num_int_insts                     5550578                       # number of integer instructions
-system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
-system.cpu1.num_load_insts                    1170888                       # Number of load instructions
-system.cpu1.num_mem_refs                      1926244                       # number of memory refs
-system.cpu1.num_store_insts                    755356                       # Number of store instructions
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_blocks::1                 0.435437                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.027215                       # Average percentage of cache occupancy
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41727                       # number of overall misses
-system.iocache.overall_misses::total            41727                       # number of overall misses
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.replacements                     41695                       # number of replacements
-system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     0.435437                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               281898                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                23952                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           305850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0                   164417                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    14126                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               178543                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0            0.416750                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.410237                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 117481                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   9826                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             127307                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0                2577422                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 141641                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2719063                       # number of ReadReq accesses(hits+misses)
+final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3272042                       # Simulator instruction rate (inst/s)
+host_tick_rate                            96902915749                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296264                       # Number of bytes of host memory used
+host_seconds                                    19.30                       # Real time elapsed on the host
+sim_insts                                    63154034                       # Number of instructions simulated
+system.physmem.bytes_read                    72297472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 995008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10452352                       # Number of bytes written to this memory
+system.physmem.num_reads                      1129648                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      163318                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       38654814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    531994                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5588490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      44243304                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                       1051788                       # number of replacements
+system.l2c.tagsinuse                     34117.721410                       # Cycle average of tags in use
+system.l2c.total_refs                         2341203                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                       1087985                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.151871                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 10019.673951                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   266.115685                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23831.931773                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.152888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.004061                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.363646                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::0                    1620505                       # number of ReadReq hits
 system.l2c.ReadReq_hits::1                     137130                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1757635                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0              0.371269                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.031848                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   956917                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4511                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               961428                       # number of ReadReq misses
-system.l2c.SCUpgradeReq_accesses::0                80                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               110                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           190                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.Writeback_hits::0                   811846                       # number of Writeback hits
+system.l2c.Writeback_hits::total               811846                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     134                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      39                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 173                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::0                    15                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::1                     9                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                24                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_rate::0         0.812500                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.918182                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_hits::0                   164417                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    14126                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               178543                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1784922                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      151256                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1936178                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1784922                       # number of overall hits
+system.l2c.overall_hits::1                     151256                       # number of overall hits
+system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::total                1936178                       # number of overall hits
+system.l2c.ReadReq_misses::0                   956917                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4511                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               961428                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  2441                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   567                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3008                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::0                  65                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::1                 101                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total             166                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0                 117481                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   9826                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             127307                       # number of ReadExReq misses
+system.l2c.demand_misses::0                   1074398                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     14337                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1088735                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                  1074398                       # number of overall misses
+system.l2c.overall_misses::1                    14337                       # number of overall misses
+system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::total              1088735                       # number of overall misses
+system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2577422                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 141641                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2719063                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               811846                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           811846                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::0                2575                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::1                 606                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3181                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0                     134                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                      39                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 173                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0           0.947961                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.935644                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  2441                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                   567                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3008                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0               811846                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           811846                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   811846                       # number of Writeback hits
-system.l2c.Writeback_hits::total               811846                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          2.151871                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.SCUpgradeReq_accesses::0                80                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1               110                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           190                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               281898                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                23952                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           305850                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::0                 2859320                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                  165593                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             3024913                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2        no_value                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1784922                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      151256                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1936178                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.375753                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.086580                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                   1074398                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     14337                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1088735                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                 10019.673951                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   266.115685                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23831.931773                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.152888                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.004061                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.363646                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2859320                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                 165593                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            3024913                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2       no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1784922                       # number of overall hits
-system.l2c.overall_hits::1                     151256                       # number of overall hits
-system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                1936178                       # number of overall hits
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.ReadReq_miss_rate::0              0.371269                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.031848                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.947961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.935644                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0         0.812500                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.918182                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.416750                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.410237                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.375753                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.086580                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::0              0.375753                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              0.086580                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                  1074398                       # number of overall misses
-system.l2c.overall_misses::1                    14337                       # number of overall misses
-system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total              1088735                       # number of overall misses
+system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2        no_value                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2       no_value                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          121798                       # number of writebacks
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          no_value                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2         no_value                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                       1051788                       # number of replacements
-system.l2c.sampled_refs                       1087985                       # Sample count of references to valid blocks.
+system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     34117.721410                       # Cycle average of tags in use
-system.l2c.total_refs                         2341203                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          121798                       # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41695                       # number of replacements
+system.iocache.tagsinuse                     0.435437                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.435437                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.027215                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41727                       # number of overall misses
+system.iocache.overall_misses::total            41727                       # number of overall misses
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41520                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
+system.cpu0.dtb.read_misses                      7079                       # DTB read misses
+system.cpu0.dtb.read_acv                          152                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
+system.cpu0.dtb.write_misses                      726                       # DTB write misses
+system.cpu0.dtb.write_acv                          99                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15091429                       # DTB hits
+system.cpu0.dtb.data_misses                      7805                       # DTB misses
+system.cpu0.dtb.data_acv                          251                       # DTB access violations
+system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
+system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
+system.cpu0.itb.fetch_misses                     3485                       # ITB misses
+system.cpu0.itb.fetch_acv                         127                       # ITB acv
+system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.num_insts                        57222076                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    53249924                       # number of integer instructions
+system.cpu0.num_fp_insts                       299810                       # number of float instructions
+system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     15135515                       # number of memory refs
+system.cpu0.num_load_insts                    9184477                       # Number of load instructions
+system.cpu0.num_store_insts                   5951038                       # Number of store instructions
+system.cpu0.num_idle_cycles              3683437089.313678                       # Number of idle cycles
+system.cpu0.num_busy_cycles              57233843.686322                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   71004     40.60%     40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 101705     58.16%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              174868                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               141425                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            17242445000      0.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1870335315000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.980748                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
+system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
+system.cpu0.kern.syscall::6                        32     14.16%     26.11% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.44%     26.55% # number of syscalls executed
+system.cpu0.kern.syscall::15                        1      0.44%     26.99% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      3.98%     30.97% # number of syscalls executed
+system.cpu0.kern.syscall::19                        8      3.54%     34.51% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.65%     37.17% # number of syscalls executed
+system.cpu0.kern.syscall::23                        2      0.88%     38.05% # number of syscalls executed
+system.cpu0.kern.syscall::24                        4      1.77%     39.82% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.10%     42.92% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.88%     43.81% # number of syscalls executed
+system.cpu0.kern.syscall::45                       37     16.37%     60.18% # number of syscalls executed
+system.cpu0.kern.syscall::47                        4      1.77%     61.95% # number of syscalls executed
+system.cpu0.kern.syscall::48                        8      3.54%     65.49% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.42%     69.91% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.44%     70.35% # number of syscalls executed
+system.cpu0.kern.syscall::59                        4      1.77%     72.12% # number of syscalls executed
+system.cpu0.kern.syscall::71                       30     13.27%     85.40% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.33%     86.73% # number of syscalls executed
+system.cpu0.kern.syscall::74                        8      3.54%     90.27% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.44%     90.71% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      0.88%     91.59% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      3.98%     95.58% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.88%     96.46% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.88%     97.35% # number of syscalls executed
+system.cpu0.kern.syscall::132                       2      0.88%     98.23% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
+system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  110      0.06%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3762      2.05%      2.11% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               168035     91.68%     93.82% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6150      3.36%     97.17% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     7      0.00%     97.18% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                183291                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7091                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1158                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1157                      
+system.cpu0.kern.mode_good::user                 1158                      
+system.cpu0.kern.mode_good::idle                    0                      
+system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu0.icache.replacements                884404                       # number of replacements
+system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           511.244754                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.998525                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0           56345132                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::0            56345132                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        56345132                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::0           56345132                       # number of overall hits
+system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::total       56345132                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::0           885000                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       885000                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::0            885000                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        885000                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::0           885000                       # number of overall misses
+system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::total       885000                       # number of overall misses
+system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::0       57230132                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0        57230132                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::0       57230132                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0      0.015464                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0       0.015464                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::0      0.015464                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                      95                       # number of writebacks
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements               1978962                       # number of replacements
+system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           504.827058                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.985990                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::0            7298106                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7298106                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0           5462265                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5462265                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0       172138                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       172138                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0        186635                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       186635                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::0            12760371                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12760371                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::0           12760371                       # number of overall hits
+system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12760371                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0          1683563                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1683563                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0          285996                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       285996                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::0        16159                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        16159                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0          703                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          703                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::0           1969559                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1969559                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0          1969559                       # number of overall misses
+system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1969559                       # number of overall misses
+system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0        8981669                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::0       5748261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0       188297                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0       187338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0        14729930                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       14729930                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0      0.187444                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0     0.049753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085817                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003753                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0       0.133711                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::0      0.133711                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                  771740                       # number of writebacks
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
+system.cpu1.dtb.read_misses                      3277                       # DTB read misses
+system.cpu1.dtb.read_acv                           58                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
+system.cpu1.dtb.write_hits                     751446                       # DTB write hits
+system.cpu1.dtb.write_misses                      415                       # DTB write misses
+system.cpu1.dtb.write_acv                          58                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
+system.cpu1.dtb.data_hits                     1914885                       # DTB hits
+system.cpu1.dtb.data_misses                      3692                       # DTB misses
+system.cpu1.dtb.data_acv                          116                       # DTB access violations
+system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
+system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
+system.cpu1.itb.fetch_misses                     1539                       # ITB misses
+system.cpu1.itb.fetch_acv                          57                       # ITB acv
+system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.num_insts                         5931958                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
+system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     5550578                       # number of integer instructions
+system.cpu1.num_fp_insts                        28590                       # number of float instructions
+system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      1926244                       # number of memory refs
+system.cpu1.num_load_insts                    1170888                       # Number of load instructions
+system.cpu1.num_store_insts                    755356                       # Number of store instructions
+system.cpu1.num_idle_cycles              3734312190.077655                       # Number of idle cycles
+system.cpu1.num_busy_cycles              5936690.922345                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   10328     33.46%     33.46% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1907      6.18%     39.64% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    110      0.36%     40.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  18518     60.00%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               30863                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    10318     45.77%     45.77% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1907      8.46%     54.23% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                22543                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1859123008500     99.41%     99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               14064500      0.00%     99.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            10905353000      0.58%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1870124427000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.999032                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.551247                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
+system.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
+system.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
+system.cpu1.kern.syscall::6                        10     10.00%     25.00% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      6.00%     31.00% # number of syscalls executed
+system.cpu1.kern.syscall::19                        2      2.00%     33.00% # number of syscalls executed
+system.cpu1.kern.syscall::23                        2      2.00%     35.00% # number of syscalls executed
+system.cpu1.kern.syscall::24                        2      2.00%     37.00% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      4.00%     41.00% # number of syscalls executed
+system.cpu1.kern.syscall::45                       17     17.00%     58.00% # number of syscalls executed
+system.cpu1.kern.syscall::47                        2      2.00%     60.00% # number of syscalls executed
+system.cpu1.kern.syscall::48                        2      2.00%     62.00% # number of syscalls executed
+system.cpu1.kern.syscall::59                        3      3.00%     65.00% # number of syscalls executed
+system.cpu1.kern.syscall::71                       24     24.00%     89.00% # number of syscalls executed
+system.cpu1.kern.syscall::74                        8      8.00%     97.00% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      1.00%     98.00% # number of syscalls executed
+system.cpu1.kern.syscall::132                       2      2.00%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
+system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    8      0.02%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  470      1.46%      1.50% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      15      0.05%      1.54% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.57% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                26238     81.66%     83.22% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2576      8.02%     91.24% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.25% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     91.26% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     2      0.01%     91.26% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     91.27% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2607      8.11%     99.39% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 158      0.49%     99.88% # number of callpals executed
+system.cpu1.kern.callpal::imb                      38      0.12%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::total                 32131                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1033                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                580                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                612                      
+system.cpu1.kern.mode_good::user                  580                      
+system.cpu1.kern.mode_good::idle                   32                      
+system.cpu1.kern.mode_switch_good::kernel     0.592449                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.608089                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        1373917500      0.07%      0.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1868002549000     99.90%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
+system.cpu1.icache.replacements                103091                       # number of replacements
+system.cpu1.icache.tagsinuse               427.126317                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 5832136                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 56.293119                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0           427.126317                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.834231                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::0            5832136                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::0             5832136                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         5832136                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::0            5832136                       # number of overall hits
+system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::total        5832136                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::0           103630                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       103630                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::0            103630                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        103630                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::0           103630                       # number of overall misses
+system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::total       103630                       # number of overall misses
+system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::0        5935766                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::0         5935766                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::0        5935766                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::0      0.017459                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::0       0.017459                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::0      0.017459                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                      15                       # number of writebacks
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                 62338                       # number of replacements
+system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0           391.951263                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.765530                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0            1109315                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1109315                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0            707444                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        707444                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        15129                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0         15613                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        15613                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0             1816759                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1816759                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0            1816759                       # number of overall hits
+system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1816759                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0            41650                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total        41650                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0           25861                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        25861                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0         1289                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         1289                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0          732                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          732                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0             67511                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         67511                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0            67511                       # number of overall misses
+system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        67511                       # number of overall misses
+system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0        1150965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0        733305                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0        16345                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0         1884270                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0        1884270                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0      0.036187                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0     0.035266                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.078511                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0       0.035829                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::0      0.035829                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                   39996                       # number of writebacks
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index ffa9d4df6..b72ae72cb 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -15,6 +15,8 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
@@ -28,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -205,7 +205,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -236,8 +236,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -269,7 +269,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -281,10 +281,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -430,12 +431,13 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -452,6 +454,7 @@ pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -468,6 +471,7 @@ pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -484,6 +488,7 @@ pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -500,6 +505,7 @@ pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -516,6 +522,7 @@ pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -532,6 +539,7 @@ pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -548,6 +556,7 @@ pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -564,6 +573,7 @@ pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -580,6 +590,7 @@ pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -596,6 +607,7 @@ pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -612,6 +624,7 @@ pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -628,6 +641,7 @@ pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -644,6 +658,7 @@ pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -660,6 +675,7 @@ pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -676,6 +692,7 @@ pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -692,6 +709,7 @@ pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -708,6 +726,7 @@ pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -724,6 +743,7 @@ pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -799,8 +819,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 0372a3b05..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
@@ -1,9 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 01b553cc1..9b658d14c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:17:36
-M5 started Apr 19 2011 12:18:17
-M5 executing on maize
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 04:22:39
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 85848a462..7f4c99b34 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,236 +1,267 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4724073                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 291084                       # Number of bytes of host memory used
-host_seconds                                    12.71                       # Real time elapsed on the host
-host_tick_rate                           143937379014                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
 sim_ticks                                1829332258000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0        183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0         9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0             7807782                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807782                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0       0.180671                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1721705                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721705                       # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0         199282                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0        6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0            5848212                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0      0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0           304362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   6.870767                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             13655994                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655994                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.129196                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            2026067                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026067                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0            511.997802                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0        15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            13655994                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655994                       # number of overall hits
-system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.129196                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           2026067                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026067                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                2042700                       # number of replacements
-system.cpu.dcache.sampled_refs                2043212                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14038433                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   825183                       # number of writebacks
-system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_hits                     16062925                       # DTB hits
-system.cpu.dtb.data_misses                      11471                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3300922                       # Simulator instruction rate (inst/s)
+host_tick_rate                           100577077281                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294216                       # Number of bytes of host memory used
+host_seconds                                    18.19                       # Real time elapsed on the host
+sim_insts                                    60038305                       # Number of instructions simulated
+system.physmem.bytes_read                    71650816                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 955904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10156864                       # Number of bytes written to this memory
+system.physmem.num_reads                      1119544                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      158701                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       39167743                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    522543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5552225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      44719968                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                       1045877                       # number of replacements
+system.l2c.tagsinuse                     33807.015903                       # Cycle average of tags in use
+system.l2c.total_refs                         2291835                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                       1077848                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.126306                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 10193.605493                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 23613.410409                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.155542                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.360312                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1699395                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1699395                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   825291                       # number of Writeback hits
+system.l2c.Writeback_hits::total               825291                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                       1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   1                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0                   185383                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185383                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1884778                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1884778                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1884778                       # number of overall hits
+system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::total                1884778                       # number of overall hits
+system.l2c.ReadReq_misses::0                   959629                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               959629                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 118859                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             118859                       # number of ReadExReq misses
+system.l2c.demand_misses::0                   1078488                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1078488                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                  1078488                       # number of overall misses
+system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::total              1078488                       # number of overall misses
+system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2659024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2659024                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               825291                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           825291                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2963266                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2963266                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2963266                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.360895                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.923077                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.390673                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.363952                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.363952                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
+system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1        no_value                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1       no_value                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          117189                       # number of writebacks
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          no_value                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         no_value                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41686                       # number of replacements
+system.iocache.tagsinuse                     1.225570                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 1.225570                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.076598                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41726                       # number of overall misses
+system.iocache.overall_misses::total            41726                       # number of overall misses
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41512                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                      9710427                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
+system.cpu.dtb.read_acv                           210                       # DTB read access violations
+system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
 system.cpu.dtb.write_hits                     6352498                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::0        60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0            59129922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0       0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0            920221                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920221                       # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  64.264250                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0         60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0             59129922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59129922                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.015324                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0             920221                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920221                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            511.215243                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0        60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0            59129922                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total        59129922                       # number of overall hits
-system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.015324                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0            920221                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        920221                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 919594                       # number of replacements
-system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                511.215243                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59129922                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                      108                       # number of writebacks
-system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
+system.cpu.dtb.write_acv                          157                       # DTB write access violations
+system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
+system.cpu.dtb.data_hits                     16062925                       # DTB hits
+system.cpu.dtb.data_misses                      11471                       # DTB misses
+system.cpu.dtb.data_acv                           367                       # DTB access violations
+system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
 system.cpu.itb.fetch_hits                     4974648                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                          184                       # ITB acv
+system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192180                       # number of callpals executed
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         60038305                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
+system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     55913521                       # number of integer instructions
+system.cpu.num_fp_insts                        324460                       # number of float instructions
+system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      16115709                       # number of memory refs
+system.cpu.num_load_insts                     9747513                       # Number of load instructions
+system.cpu.num_store_insts                    6368196                       # Number of store instructions
+system.cpu.num_idle_cycles               3598608979.180807                       # Number of idle cycles
+system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
@@ -250,20 +281,6 @@ system.cpu.kern.ipl_used::0                  0.981732                       # fr
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.402439                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801032773000     98.45%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -277,261 +294,255 @@ system.cpu.kern.syscall::23                         4      1.23%     37.12% # nu
 system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
 system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
 system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
-system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
-system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
-system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
-system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
-system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
-system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
-system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
-system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
-system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
-system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
-system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
-system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
-system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
-system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
-system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
-system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
-system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
-system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               3598608979.180807                       # Number of idle cycles
-system.cpu.num_insts                         60038305                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
-system.cpu.num_int_insts                     55913521                       # number of integer instructions
-system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
-system.cpu.num_load_insts                     9747513                       # Number of load instructions
-system.cpu.num_mem_refs                      16115709                       # number of memory refs
-system.cpu.num_store_insts                    6368196                       # Number of store instructions
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_blocks::1                 1.225570                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.076598                       # Average percentage of cache occupancy
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.replacements                     41686                       # number of replacements
-system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.225570                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               304242                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304242                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0                   185383                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185383                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0            0.390673                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 118859                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             118859                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0                2659024                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2659024                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0                    1699395                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1699395                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0              0.360895                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   959629                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               959629                       # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0                       1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0           0.923077                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                    12                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0               825291                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           825291                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   825291                       # number of Writeback hits
-system.l2c.Writeback_hits::total               825291                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          2.126306                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2963266                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2963266                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1        no_value                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1884778                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1884778                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.363952                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                   1078488                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1078488                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                 10193.605493                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23613.410409                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.155542                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.360312                       # Average percentage of cache occupancy
-system.l2c.overall_accesses::0                2963266                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1       no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1884778                       # number of overall hits
-system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1884778                       # number of overall hits
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.363952                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                  1078488                       # number of overall misses
-system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total              1078488                       # number of overall misses
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         no_value                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                       1045877                       # number of replacements
-system.l2c.sampled_refs                       1077848                       # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     33807.015903                       # Cycle average of tags in use
-system.l2c.total_refs                         2291835                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          117189                       # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
+system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
+system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
+system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
+system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
+system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
+system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
+system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
+system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
+system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
+system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
+system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
+system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
+system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
+system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
+system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
+system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
+system.cpu.kern.syscall::total                    326                       # number of syscalls executed
+system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
+system.cpu.kern.callpal::total                 192180                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1909                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   171                      
+system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.402439                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801032773000     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu.icache.replacements                 919594                       # number of replacements
+system.cpu.icache.tagsinuse                511.215243                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 59129922                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  64.264250                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            511.215243                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0            59129922                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0             59129922                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59129922                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0            59129922                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total        59129922                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0            920221                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920221                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0             920221                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920221                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0            920221                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        920221                       # number of overall misses
+system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0        60050143                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0         60050143                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0        60050143                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.015324                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.015324                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::0       0.015324                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                      108                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2042700                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038433                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2043212                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.870767                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.997802                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0             7807782                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807782                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            5848212                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        183141                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         199282                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             13655994                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655994                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            13655994                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655994                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           1721705                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721705                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0           304362                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0            2026067                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026067                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           2026067                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026067                       # number of overall misses
+system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         9529487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6152574                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         15682061                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        15682061                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.180671                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.129196                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0       0.129196                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   825183                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 8d055ed5f..1a4bf8750 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -15,6 +15,8 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
@@ -28,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -308,7 +308,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -339,8 +339,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -372,7 +372,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -384,10 +384,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -533,12 +534,13 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -555,6 +557,7 @@ pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -571,6 +574,7 @@ pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -587,6 +591,7 @@ pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -603,6 +608,7 @@ pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -619,6 +625,7 @@ pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -635,6 +642,7 @@ pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -651,6 +659,7 @@ pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -667,6 +676,7 @@ pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -683,6 +693,7 @@ pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -699,6 +710,7 @@ pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -715,6 +727,7 @@ pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -731,6 +744,7 @@ pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -747,6 +761,7 @@ pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -763,6 +778,7 @@ pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -779,6 +795,7 @@ pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -795,6 +812,7 @@ pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -811,6 +829,7 @@ pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -827,6 +846,7 @@ pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -902,8 +922,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 0372a3b05..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -1,9 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index a027f13fc..3af3fc1dd 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:17:36
-M5 started Apr 19 2011 12:17:43
-M5 executing on maize
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 04:23:09
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 562628000
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 58de64347..628ea2e3e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,1057 +1,1068 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2296983                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289272                       # Number of bytes of host memory used
-host_seconds                                    25.84                       # Real time elapsed on the host
-host_tick_rate                            75796433096                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    59355643                       # Number of instructions simulated
 sim_seconds                                  1.958647                       # Number of seconds simulated
 sim_ticks                                1958647095000                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses::0       193049                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       193049                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0       176505                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       176505                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    234949000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085698                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        16544                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        16544                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    185317000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.085698                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        16544                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0        8457107                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8457107                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0            7421006                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7421006                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   26570279500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0      0.122512                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0          1036101                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1036101                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23461938500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122512                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses        1036101                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    884470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0       192084                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       192084                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  7251.219512                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  4251.219512                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0        191674                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       191674                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency      2973000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.002134                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0          410                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          410                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency      1743000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.002134                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses          410                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0       5851669                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5851669                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0           5560133                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5560133                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency   9109954000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0     0.049821                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0          291536                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       291536                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency   8235346000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049821                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        291536                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1242107000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  9.970149                       # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        14308776                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14308776                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            12981139                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12981139                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    35680233500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.092785                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           1327637                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1327637                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  31697284500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.092785                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1327637                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_blocks::0           503.524900                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.983447                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.overall_accesses::0       14308776                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           12981139                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12981139                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   35680233500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.092785                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          1327637                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1327637                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  31697284500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.092785                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1327637                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2126577000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1338438                       # number of replacements
-system.cpu0.dcache.sampled_refs               1338837                       # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               502.524901                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                13348404                       # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  786441                       # number of writebacks
-system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
-system.cpu0.dtb.data_acv                          344                       # DTB access violations
-system.cpu0.dtb.data_hits                    14678366                       # DTB hits
-system.cpu0.dtb.data_misses                      8256                       # DTB misses
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
-system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8633623                       # DTB read hits
-system.cpu0.dtb.read_misses                      7443                       # DTB read misses
-system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
-system.cpu0.dtb.write_acv                         134                       # DTB write access violations
-system.cpu0.dtb.write_hits                    6044743                       # DTB write hits
-system.cpu0.dtb.write_misses                      813                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses::0       54081252                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     54081252                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0           53165471                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       53165471                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   13429132500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0      0.016933                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           915781                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       915781                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency  10681093500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.016933                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         915781                       # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 58.062522                       # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0        54081252                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     54081252                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 14664.130944                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0            53165471                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        53165471                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    13429132500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.016933                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            915781                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        915781                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency  10681093500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0     0.016933                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          915781                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_blocks::0           508.800486                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.993751                       # Average percentage of cache occupancy
-system.cpu0.icache.overall_accesses::0       54081252                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 14664.130944                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0           53165471                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total       53165471                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   13429132500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.016933                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           915781                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       915781                       # number of overall misses
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency  10681093500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0     0.016933                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         915781                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                915147                       # number of replacements
-system.cpu0.icache.sampled_refs                915659                       # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               508.800486                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                53165471                       # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           36696092000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                      55                       # number of writebacks
-system.cpu0.idle_fraction                    0.939737                       # Percentage of idle cycles
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                3856928                       # ITB accesses
-system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_hits                    3853057                       # ITB hits
-system.cpu0.itb.fetch_misses                     3871                       # ITB misses
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               172198     91.50%     93.64% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6678      3.55%     97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4751      2.52%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                188203                       # number of callpals executed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    202972                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6380                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0                   72739     40.62%     40.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1975      1.10%     41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 104211     58.20%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              179062                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    71372     49.27%     49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1975      1.36%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   71366     49.27%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               144850                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1899667899000     97.02%     97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               79058000      0.00%     97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              565985500      0.03%     97.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                4729500      0.00%     97.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            57694185000      2.95%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1958011857000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981207                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684822                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1283                      
-system.cpu0.kern.mode_good::user                 1283                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch::kernel             7302                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
-system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
-system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
-system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles              235989726.444158                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts      6237040                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
-system.cpu0.num_fp_insts                       293967                       # number of float instructions
-system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
-system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles              3680034047.555842                       # Number of idle cycles
-system.cpu0.num_insts                        54072652                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
-system.cpu0.num_int_insts                    50043234                       # number of integer instructions
-system.cpu0.num_int_register_reads           68528072                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          37080372                       # number of times the integer registers were written
-system.cpu0.num_load_insts                    8664914                       # Number of load instructions
-system.cpu0.num_mem_refs                     14724357                       # number of memory refs
-system.cpu0.num_store_insts                   6059443                       # Number of store instructions
-system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0        11784                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        11784                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     13079000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.076923                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0          982                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total          982                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10133000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.076923                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses          982                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0        1040274                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1040274                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0            1003161                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1003161                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency     533263000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0      0.035676                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0            37113                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        37113                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency    421922000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035676                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses          37113                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     11413500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0        12031                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        12031                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9704.950495                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0         11526                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        11526                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency      6416000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.041975                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0          505                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          505                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency      4901000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.041975                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses          505                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0        637320                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       637320                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0            616899                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        616899                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency    556796000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0     0.032042                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0           20421                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        20421                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency    495533000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.032042                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         20421                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    298050500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 30.762530                       # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         1677594                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1677594                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             1620060                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1620060                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     1090059000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.034296                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0             57534                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         57534                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency    917455000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.034296                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses           57534                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_blocks::0           389.521271                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.760784                       # Average percentage of cache occupancy
-system.cpu1.dcache.overall_accesses::0        1677594                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            1620060                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1620060                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    1090059000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.034296                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0            57534                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        57534                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency    917455000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.034296                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses          57534                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    309464000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                 52960                       # number of replacements
-system.cpu1.dcache.sampled_refs                 53472                       # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 1644934                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1942411783000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   29784                       # number of writebacks
-system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
-system.cpu1.dtb.data_acv                           29                       # DTB access violations
-system.cpu1.dtb.data_hits                     1701325                       # DTB hits
-system.cpu1.dtb.data_misses                      3333                       # DTB misses
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_hits                     1050117                       # DTB read hits
-system.cpu1.dtb.read_misses                      2992                       # DTB read misses
-system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
-system.cpu1.dtb.write_acv                          29                       # DTB write access violations
-system.cpu1.dtb.write_hits                     651208                       # DTB write hits
-system.cpu1.dtb.write_misses                      341                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses::0        5286354                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      5286354                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0            5199349                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5199349                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    1260607500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0      0.016458                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0            87005                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total        87005                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency    999558500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.016458                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses          87005                       # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                 59.783935                       # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0         5286354                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      5286354                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14488.908683                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0             5199349                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5199349                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     1260607500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.016458                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0             87005                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total         87005                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency    999558500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0     0.016458                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses           87005                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_blocks::0           419.807616                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.819937                       # Average percentage of cache occupancy
-system.cpu1.icache.overall_accesses::0        5286354                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14488.908683                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0            5199349                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5199349                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    1260607500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.016458                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0            87005                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total        87005                       # number of overall misses
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency    999558500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0     0.016458                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses          87005                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                 86457                       # number of replacements
-system.cpu1.icache.sampled_refs                 86969                       # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               419.807616                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 5199349                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1942711132000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                      14                       # number of writebacks
-system.cpu1.idle_fraction                    0.995135                       # Percentage of idle cycles
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                1494654                       # ITB accesses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_hits                    1493438                       # ITB hits
-system.cpu1.itb.fetch_misses                     1216                       # ITB misses
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                24309     82.25%     83.46% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 29554                       # number of callpals executed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     36191                       # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce                    2318                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count::0                    9289     32.15%     32.15% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     88      0.30%     39.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  17551     60.74%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               28897                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                     9279     45.20%     45.20% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      88      0.43%     55.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                    9191     44.78%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                20527                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1917878582000     97.92%     97.92% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              507844000      0.03%     97.94% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               54239000      0.00%     97.95% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            40205672000      2.05%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1958646337000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.523674                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel                477                      
-system.cpu1.kern.mode_good::user                  464                      
-system.cpu1.kern.mode_good::idle                   13                      
-system.cpu1.kern.mode_switch::kernel              804                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2064                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel     0.593284                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.006298                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.599582                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        3571416000      0.18%      0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1745054000      0.09%      0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1953329865000     99.73%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
-system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
-system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
-system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              19057169.001990                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts       510974                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
-system.cpu1.num_fp_insts                        34031                       # number of float instructions
-system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
-system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles              3898237020.998010                       # Number of idle cycles
-system.cpu1.num_insts                         5282991                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
-system.cpu1.num_int_insts                     4948310                       # number of integer instructions
-system.cpu1.num_int_register_reads            6886066                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           3732878                       # number of times the integer registers were written
-system.cpu1.num_load_insts                    1056124                       # Number of load instructions
-system.cpu1.num_mem_refs                      1710778                       # number of memory refs
-system.cpu1.num_store_insts                    654654                       # Number of store instructions
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115247.114943                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency          20052998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency     11004998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses                174                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137701.766606                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5721783806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3560928000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137608.129320                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5741836804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3571932998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses               41726                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_blocks::1                 0.563721                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.035233                       # Average percentage of cache occupancy
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137608.129320                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5741836804                       # number of overall miss cycles
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3571932998                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses              41726                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.replacements                     41694                       # number of replacements
-system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1751545158000                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               287834                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                18765                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           306599                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 54743.487656                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911                       # average ReadExReq mshr miss latency
+final_tick                               1958647095000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1643366                       # Simulator instruction rate (inst/s)
+host_tick_rate                            54228566310                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293036                       # Number of bytes of host memory used
+host_seconds                                    36.12                       # Real time elapsed on the host
+sim_insts                                    59355643                       # Number of instructions simulated
+system.physmem.bytes_read                    30050624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 971200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10333120                       # Number of bytes written to this memory
+system.physmem.num_reads                       469541                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      161455                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       15342541                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    495852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5275642                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      20618183                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        393576                       # number of replacements
+system.l2c.tagsinuse                     34487.800710                       # Cycle average of tags in use
+system.l2c.total_refs                         2371449                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        427769                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.543761                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                   10882116000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 10867.929163                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   199.983935                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23419.887612                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.165831                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.003052                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.357359                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1659395                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     119191                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1778586                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   816294                       # number of Writeback hits
+system.l2c.Writeback_hits::total               816294                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      53                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 225                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0                    18                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                    19                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                37                       # number of SCUpgradeReq hits
 system.l2c.ReadExReq_hits::0                   170288                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::1                    12569                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               182857                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6434878000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.408381                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.330189                       # miss rate for ReadExReq accesses
+system.l2c.demand_hits::0                     1829683                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      131760                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1961443                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1829683                       # number of overall hits
+system.l2c.overall_hits::1                     131760                       # number of overall hits
+system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::total                1961443                       # number of overall hits
+system.l2c.ReadReq_misses::0                   302827                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     1953                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               304780                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  2453                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   495                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2948                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0                  15                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                  74                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total              89                       # number of SCUpgradeReq misses
 system.l2c.ReadExReq_misses::0                 117546                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::1                   6196                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             123742                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     4949974000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.429908                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       6.594298                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               123742                       # number of ReadExReq MSHR misses
+system.l2c.demand_misses::0                    420373                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                      8149                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                428522                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   420373                       # number of overall misses
+system.l2c.overall_misses::1                     8149                       # number of overall misses
+system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::total               428522                       # number of overall misses
+system.l2c.ReadReq_miss_latency           15853640000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency            3024000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency           416000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          6434878000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            22288518000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           22288518000                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::0                1962222                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::1                 121144                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2083366                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               816294                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           816294                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                2625                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                 548                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3173                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0                33                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1                93                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           126                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               287834                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                18765                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           306599                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2250056                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  139909                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2389965                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2250056                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 139909                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2389965                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.154329                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.016121                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.934476                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.903285                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0         0.454545                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.795699                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.408381                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.330189                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.186828                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.058245                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.186828                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.058245                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::0   52352.135047                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1   8117583.205325                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1659395                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     119191                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1778586                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           15853640000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.154329                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.016121                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   302827                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     1953                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               304780                       # number of ReadReq misses
+system.l2c.UpgradeReq_avg_miss_latency::0  1232.776192                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  6109.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1  5621.621622                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 54743.487656                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    53020.812469                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    2735123.082587                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   53020.812469                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   2735123.082587                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          119935                       # number of writebacks
 system.l2c.ReadReq_mshr_hits                       11                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                 304769                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                2948                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses                89                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               123742                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  428511                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 428511                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.ReadReq_mshr_miss_latency      12195855000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     117981000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency      3560000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4949974000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       17145829000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency      17145829000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    802314500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1391411500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   2193726000                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::0         0.155318                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1         2.515758                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 304769                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    802314500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0                33                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1                93                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           126                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1  5621.621622                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_hits::0                    18                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                    19                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                37                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency           416000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0         0.454545                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.795699                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0                  15                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                  74                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total              89                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency      3560000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     2.696970                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     0.956989                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses                89                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0                2625                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                 548                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3173                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0  1232.776192                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1  6109.090909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                     172                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                      53                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 225                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency            3024000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.934476                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.903285                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  2453                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                   495                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2948                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency     117981000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate::0      1.123048                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1      5.379562                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                2948                       # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1391411500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               816294                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           816294                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   816294                       # number of Writeback hits
-system.l2c.Writeback_hits::total               816294                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.543761                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2250056                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  139909                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2389965                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    53020.812469                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    2735123.082587                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40012.576107                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1829683                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      131760                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1961443                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            22288518000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.186828                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.058245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    420373                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                      8149                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                428522                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       17145829000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_rate::0     2.696970                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1     0.956989                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.429908                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       6.594298                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::0          0.190445                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1          3.062784                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  428511                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                 10867.929163                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   199.983935                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23419.887612                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.165831                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.003052                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.357359                       # Average percentage of cache occupancy
-system.l2c.overall_accesses::0                2250056                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 139909                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2389965                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   53020.812469                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   2735123.082587                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.576107                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1829683                       # number of overall hits
-system.l2c.overall_hits::1                     131760                       # number of overall hits
-system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                1961443                       # number of overall hits
-system.l2c.overall_miss_latency           22288518000                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.186828                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.058245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   420373                       # number of overall misses
-system.l2c.overall_misses::1                     8149                       # number of overall misses
-system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               428522                       # number of overall misses
-system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      17145829000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate::0         0.190445                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1         3.062784                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 428511                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2193726000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        393576                       # number of replacements
-system.l2c.sampled_refs                        427769                       # Sample count of references to valid blocks.
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40012.576107                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40012.576107                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     34487.800710                       # Cycle average of tags in use
-system.l2c.total_refs                         2371449                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                   10882116000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          119935                       # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41694                       # number of replacements
+system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1751545158000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.563721                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.035233                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41726                       # number of overall misses
+system.iocache.overall_misses::total            41726                       # number of overall misses
+system.iocache.ReadReq_miss_latency          20052998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5721783806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5741836804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5741836804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115247.114943                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137701.766606                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137608.129320                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137608.129320                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41520                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.ReadReq_mshr_misses                174                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses               41726                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              41726                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.ReadReq_mshr_miss_latency     11004998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3560928000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571932998                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571932998                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                     8633623                       # DTB read hits
+system.cpu0.dtb.read_misses                      7443                       # DTB read misses
+system.cpu0.dtb.read_acv                          210                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
+system.cpu0.dtb.write_hits                    6044743                       # DTB write hits
+system.cpu0.dtb.write_misses                      813                       # DTB write misses
+system.cpu0.dtb.write_acv                         134                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
+system.cpu0.dtb.data_hits                    14678366                       # DTB hits
+system.cpu0.dtb.data_misses                      8256                       # DTB misses
+system.cpu0.dtb.data_acv                          344                       # DTB access violations
+system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
+system.cpu0.itb.fetch_hits                    3853057                       # ITB hits
+system.cpu0.itb.fetch_misses                     3871                       # ITB misses
+system.cpu0.itb.fetch_acv                         184                       # ITB acv
+system.cpu0.itb.fetch_accesses                3856928                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.num_insts                        54072652                       # Number of instructions executed
+system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6237040                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    50043234                       # number of integer instructions
+system.cpu0.num_fp_insts                       293967                       # number of float instructions
+system.cpu0.num_int_register_reads           68528072                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          37080372                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     14724357                       # number of memory refs
+system.cpu0.num_load_insts                    8664914                       # Number of load instructions
+system.cpu0.num_store_insts                   6059443                       # Number of store instructions
+system.cpu0.num_idle_cycles              3680034047.555842                       # Number of idle cycles
+system.cpu0.num_busy_cycles              235989726.444158                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.939737                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                    6380                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    202972                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   72739     40.62%     40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1975      1.10%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 104211     58.20%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              179062                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    71372     49.27%     49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1975      1.36%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   71366     49.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               144850                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1899667899000     97.02%     97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               79058000      0.00%     97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              565985500      0.03%     97.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                4729500      0.00%     97.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            57694185000      2.95%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1958011857000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981207                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684822                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
+system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
+system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
+system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
+system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               172198     91.50%     93.64% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6678      3.55%     97.19% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4751      2.52%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
+system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                188203                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7302                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1283                      
+system.cpu0.kern.mode_good::user                 1283                      
+system.cpu0.kern.mode_good::idle                    0                      
+system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu0.icache.replacements                915147                       # number of replacements
+system.cpu0.icache.tagsinuse               508.800486                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                53165471                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                915659                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 58.062522                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           36696092000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           508.800486                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.993751                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0           53165471                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       53165471                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::0            53165471                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        53165471                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::0           53165471                       # number of overall hits
+system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::total       53165471                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::0           915781                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       915781                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::0            915781                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        915781                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::0           915781                       # number of overall misses
+system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::total       915781                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency   13429132500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency    13429132500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency   13429132500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::0       54081252                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     54081252                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0        54081252                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     54081252                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::0       54081252                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0      0.016933                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0       0.016933                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::0      0.016933                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::0 14664.130944                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 14664.130944                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                      55                       # number of writebacks
+system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses         915781                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses          915781                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses         915781                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency  10681093500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency  10681093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency  10681093500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.016933                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::0     0.016933                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::0     0.016933                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements               1338438                       # number of replacements
+system.cpu0.dcache.tagsinuse               502.524901                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13348404                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1338837                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.970149                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           503.524900                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.983447                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::0            7421006                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7421006                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0           5560133                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5560133                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0       176505                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       176505                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0        191674                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       191674                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::0            12981139                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12981139                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::0           12981139                       # number of overall hits
+system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12981139                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0          1036101                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1036101                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0          291536                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       291536                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::0        16544                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        16544                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0          410                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          410                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::0           1327637                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1327637                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0          1327637                       # number of overall misses
+system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1327637                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency   26570279500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency   9109954000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency    234949000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency      2973000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency    35680233500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency   35680233500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0        8457107                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8457107                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::0       5851669                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5851669                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0       193049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       193049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0       192084                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       192084                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0        14308776                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14308776                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       14308776                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0      0.122512                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0     0.049821                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.002134                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0       0.092785                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::0      0.092785                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  7251.219512                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                  786441                       # number of writebacks
+system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses        1036101                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses        291536                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses        16544                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses          410                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1327637                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses        1327637                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23461938500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8235346000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    185317000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency      1743000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency  31697284500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency  31697284500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    884470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1242107000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2126577000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122512                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049821                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.085698                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.002134                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.092785                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.092785                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  4251.219512                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                     1050117                       # DTB read hits
+system.cpu1.dtb.read_misses                      2992                       # DTB read misses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
+system.cpu1.dtb.write_hits                     651208                       # DTB write hits
+system.cpu1.dtb.write_misses                      341                       # DTB write misses
+system.cpu1.dtb.write_acv                          29                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
+system.cpu1.dtb.data_hits                     1701325                       # DTB hits
+system.cpu1.dtb.data_misses                      3333                       # DTB misses
+system.cpu1.dtb.data_acv                           29                       # DTB access violations
+system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
+system.cpu1.itb.fetch_hits                    1493438                       # ITB hits
+system.cpu1.itb.fetch_misses                     1216                       # ITB misses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_accesses                1494654                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.num_insts                         5282991                       # Number of instructions executed
+system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
+system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       510974                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     4948310                       # number of integer instructions
+system.cpu1.num_fp_insts                        34031                       # number of float instructions
+system.cpu1.num_int_register_reads            6886066                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           3732878                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      1710778                       # number of memory refs
+system.cpu1.num_load_insts                    1056124                       # Number of load instructions
+system.cpu1.num_store_insts                    654654                       # Number of store instructions
+system.cpu1.num_idle_cycles              3898237020.998010                       # Number of idle cycles
+system.cpu1.num_busy_cycles              19057169.001990                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.995135                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                    2318                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     36191                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                    9289     32.15%     32.15% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                     88      0.30%     39.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  17551     60.74%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               28897                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                     9279     45.20%     45.20% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                      88      0.43%     55.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                    9191     44.78%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                20527                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1917878582000     97.92%     97.92% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              507844000      0.03%     97.94% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               54239000      0.00%     97.95% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            40205672000      2.05%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1958646337000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.523674                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
+system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
+system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
+system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
+system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                24309     82.25%     83.46% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
+system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::total                 29554                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel              804                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2064                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                477                      
+system.cpu1.kern.mode_good::user                  464                      
+system.cpu1.kern.mode_good::idle                   13                      
+system.cpu1.kern.mode_switch_good::kernel     0.593284                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle      0.006298                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.599582                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        3571416000      0.18%      0.18% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1745054000      0.09%      0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1953329865000     99.73%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
+system.cpu1.icache.replacements                 86457                       # number of replacements
+system.cpu1.icache.tagsinuse               419.807616                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 5199349                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                 86969                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 59.783935                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1942711132000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0           419.807616                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.819937                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::0            5199349                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5199349                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::0             5199349                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         5199349                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::0            5199349                       # number of overall hits
+system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::total        5199349                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::0            87005                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total        87005                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::0             87005                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total         87005                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::0            87005                       # number of overall misses
+system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::total        87005                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency    1260607500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency     1260607500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency    1260607500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::0        5286354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      5286354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::0         5286354                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      5286354                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::0        5286354                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::0      0.016458                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::0       0.016458                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::0      0.016458                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::0 14488.908683                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0 14488.908683                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                      14                       # number of writebacks
+system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses          87005                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses           87005                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses          87005                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency    999558500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency    999558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency    999558500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.016458                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::0     0.016458                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::0     0.016458                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                 52960                       # number of replacements
+system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1644934                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                 53472                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 30.762530                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1942411783000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0           389.521271                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.760784                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0            1003161                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1003161                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0            616899                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        616899                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0        11784                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        11784                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0         11526                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        11526                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0             1620060                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1620060                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0            1620060                       # number of overall hits
+system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1620060                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0            37113                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total        37113                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0           20421                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        20421                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0          982                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total          982                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0          505                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          505                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0             57534                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         57534                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0            57534                       # number of overall misses
+system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        57534                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency     533263000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency    556796000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency     13079000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency      6416000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency     1090059000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency    1090059000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0        1040274                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1040274                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0        637320                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       637320                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0        12031                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        12031                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0         1677594                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      1677594                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0        1677594                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0      0.035676                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0     0.032042                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.041975                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0       0.034296                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::0      0.034296                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                   29784                       # number of writebacks
+system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses          37113                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses         20421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses          982                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses          505                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses           57534                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses          57534                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency    421922000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency    495533000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10133000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency      4901000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency    917455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency    917455000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     11413500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    298050500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency    309464000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035676                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.032042                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.076923                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.041975                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.034296                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.034296                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9704.950495                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 80db30395..54195aa23 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -15,6 +15,8 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
@@ -28,20 +30,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -202,7 +202,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -233,8 +233,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
 
 [system.l2c]
 type=BaseCache
@@ -266,7 +266,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
 
 [system.membus]
 type=Bus
@@ -278,10 +278,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -427,12 +428,13 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -449,6 +451,7 @@ pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -465,6 +468,7 @@ pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -481,6 +485,7 @@ pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -497,6 +502,7 @@ pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -513,6 +519,7 @@ pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -529,6 +536,7 @@ pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -545,6 +553,7 @@ pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -561,6 +570,7 @@ pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -577,6 +587,7 @@ pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -593,6 +604,7 @@ pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -609,6 +621,7 @@ pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -625,6 +638,7 @@ pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -641,6 +655,7 @@ pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -657,6 +672,7 @@ pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -673,6 +689,7 @@ pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -689,6 +706,7 @@ pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -705,6 +723,7 @@ pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -721,6 +740,7 @@ pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -796,8 +816,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
 pio=system.iobus.port[26]
 
 [system.tsunami.io]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 0372a3b05..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -1,9 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index aee40b816..826f2c28b 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:17:36
-M5 started Apr 19 2011 12:17:43
-M5 executing on maize
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 04:22:43
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 397168bed..ac9598c08 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,635 +1,646 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2410973                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 287860                       # Number of bytes of host memory used
-host_seconds                                    23.28                       # Real time elapsed on the host
-host_tick_rate                            82268225536                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56137087                       # Number of instructions simulated
 sim_seconds                                  1.915549                       # Number of seconds simulated
 sim_ticks                                1915548867000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0       200226                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200226                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        183025                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183025                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    245980000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085908                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        17201                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17201                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    194377000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.085908                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17201                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         8876646                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8876646                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             7807536                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807536                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    27121920500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.120441                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1069110                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069110                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  23914545000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.120441                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1069110                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    862763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       199203                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199203                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0         199203                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199203                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0        6152889                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152889                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            5848554                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848554                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    9228484000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.049462                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0           304335                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   8315479000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.049462                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         304335                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1199607500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  10.094968                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15029535                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15029535                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26466.589124                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             13656090                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13656090                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     36350404500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.091383                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            1373445                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373445                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  32230024000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.091383                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1373445                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0            511.984023                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999969                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0        15029535                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26466.589124                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            13656090                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13656090                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    36350404500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.091383                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           1373445                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373445                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  32230024000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.091383                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1373445                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2062370500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1390115                       # number of replacements
-system.cpu.dcache.sampled_refs                1390627                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14038335                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               84029000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   826586                       # number of writebacks
-system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_hits                     15409957                       # DTB hits
-system.cpu.dtb.data_misses                      11452                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      9057511                       # DTB read hits
-system.cpu.dtb.read_misses                      10312                       # DTB read misses
-system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6352446                       # DTB write hits
-system.cpu.dtb.write_misses                      1140                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::0        56148907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56148907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0            55220553                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55220553                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    13616370500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.016534                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0            928354                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928354                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency  10830625500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.016534                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          928354                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  59.492469                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0         56148907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56148907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14667.218001                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0             55220553                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55220553                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     13616370500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.016534                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0             928354                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         928354                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  10830625500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.016534                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           928354                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            508.721464                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.993597                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0        56148907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14667.218001                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0            55220553                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total        55220553                       # number of overall hits
-system.cpu.icache.overall_miss_latency    13616370500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.016534                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0            928354                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        928354                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  10830625500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.016534                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          928354                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 927683                       # number of replacements
-system.cpu.icache.sampled_refs                 928194                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                508.721464                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55220553                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle            36307428000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                       85                       # number of writebacks
-system.cpu.idle_fraction                     0.936531                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 4978517                       # ITB accesses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_hits                     4973520                       # ITB hits
-system.cpu.itb.fetch_misses                      4997                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4173      2.16%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175927     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192868                       # number of callpals executed
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211932                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74887     40.89%     40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1931      1.05%     42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106197     57.98%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183146                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73520     49.31%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1931      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73520     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149102                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857816228500     96.99%     96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                79988500      0.00%     96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               554693000      0.03%     97.02% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             57097199000      2.98%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1915548109000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981746                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692298                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel                1906                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   168                      
-system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2092                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.322887                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.403193                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        45253274000      2.36%      2.36% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5124228000      0.27%      2.63% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1865170605000     97.37%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
-system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
-system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
-system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
-system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
-system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
-system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
-system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
-system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
-system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
-system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
-system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
-system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
-system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
-system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
-system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
-system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
-system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
-system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
-system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
-system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
-system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
-system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
-system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
-system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
-system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
-system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
-system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
-system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
-system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
-system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
-system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.not_idle_fraction                 0.063469                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               243154546.001873                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      6464616                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                 324192                       # Number of float alu accesses
-system.cpu.num_fp_insts                        324192                       # number of float instructions
-system.cpu.num_fp_register_reads               163510                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166384                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1482242                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               3587943187.998127                       # Number of idle cycles
-system.cpu.num_insts                         56137087                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              52011214                       # Number of integer alu accesses
-system.cpu.num_int_insts                     52011214                       # number of integer instructions
-system.cpu.num_int_register_reads            71259077                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38485860                       # number of times the integer registers were written
-system.cpu.num_load_insts                     9094324                       # Number of load instructions
-system.cpu.num_mem_refs                      15462519                       # number of memory refs
-system.cpu.num_store_insts                    6368195                       # Number of store instructions
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115265.884393                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency          19940998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency     10944998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137714.208847                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5722300806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3561447990                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6166.863307                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137621.133709                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5742241804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3572392988                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_blocks::1                 1.340325                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.083770                       # Average percentage of cache occupancy
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137621.133709                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5742241804                       # number of overall miss cycles
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3572392988                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.replacements                     41685                       # number of replacements
-system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1750545944000                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               304172                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304172                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52003.930884                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884                       # average ReadExReq mshr miss latency
+final_tick                               1915548867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1659827                       # Simulator instruction rate (inst/s)
+host_tick_rate                            56637748152                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290988                       # Number of bytes of host memory used
+host_seconds                                    33.82                       # Real time elapsed on the host
+sim_insts                                    56137087                       # Number of instructions simulated
+system.physmem.bytes_read                    29663360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 943040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10122368                       # Number of bytes written to this memory
+system.physmem.num_reads                       463490                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      158162                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       15485567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    492308                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5284317                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      20769884                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        389289                       # number of replacements
+system.l2c.tagsinuse                     34352.038344                       # Cycle average of tags in use
+system.l2c.total_refs                         2311163                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        421794                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.479364                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    6937912000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 11241.373247                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 23110.665097                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.171530                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.352641                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1710461                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1710461                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   826671                       # number of Writeback hits
+system.l2c.Writeback_hits::total               826671                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                       6                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::0                   185878                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               185878                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6151753000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.388905                       # miss rate for ReadExReq accesses
+system.l2c.demand_hits::0                     1896339                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1896339                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1896339                       # number of overall hits
+system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::total                1896339                       # number of overall hits
+system.l2c.ReadReq_misses::0                   304138                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               304138                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                     7                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::0                 118294                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             118294                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     4732225000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.388905                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               118294                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                2014599                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2014599                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52016.540189                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1710461                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1710461                       # number of ReadReq hits
+system.l2c.demand_misses::0                    422432                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                422432                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   422432                       # number of overall misses
+system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::total               422432                       # number of overall misses
 system.l2c.ReadReq_miss_latency           15820206500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.150967                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   304138                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               304138                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency      12170545000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.150967                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 304138                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    772673000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                       6                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_miss_latency             248000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.538462                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                     7                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency        320000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.538462                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                   7                       # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1083819500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadExReq_miss_latency          6151753000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            21971959500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           21971959500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2014599                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2014599                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::0               826671                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           826671                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   826671                       # number of Writeback hits
-system.l2c.Writeback_hits::total               826671                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.479364                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               304172                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304172                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::0                 2318771                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2318771                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52013.009194                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40012.996175                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1896339                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1896339                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            21971959500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.182179                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    422432                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                422432                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       16902770000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.182179                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  422432                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                 11241.373247                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23110.665097                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.171530                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.352641                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2318771                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52013.009194                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.996175                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1896339                       # number of overall hits
-system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1896339                       # number of overall hits
-system.l2c.overall_miss_latency           21971959500                       # number of overall miss cycles
+system.l2c.ReadReq_miss_rate::0              0.150967                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.538462                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.388905                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.182179                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::0              0.182179                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   422432                       # number of overall misses
-system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               422432                       # number of overall misses
+system.l2c.ReadReq_avg_miss_latency::0   52016.540189                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52003.930884                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    52013.009194                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52013.009194                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          116650                       # number of writebacks
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                 304138                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                   7                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               118294                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  422432                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 422432                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency      12170545000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency        320000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4732225000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       16902770000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency      16902770000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    772673000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1083819500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   1856492500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.150967                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.538462                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.388905                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.182179                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::0         0.182179                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 422432                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1856492500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        389289                       # number of replacements
-system.l2c.sampled_refs                        421794                       # Sample count of references to valid blocks.
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40012.996175                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40012.996175                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     34352.038344                       # Cycle average of tags in use
-system.l2c.total_refs                         2311163                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                    6937912000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          116650                       # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41685                       # number of replacements
+system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1750545944000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 1.340325                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.083770                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
+system.iocache.ReadReq_miss_latency          19940998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5722300806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5742241804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5742241804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115265.884393                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137714.208847                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137621.133709                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137621.133709                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6166.863307                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41512                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.ReadReq_mshr_miss_latency     10944998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561447990                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572392988                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572392988                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                      9057511                       # DTB read hits
+system.cpu.dtb.read_misses                      10312                       # DTB read misses
+system.cpu.dtb.read_acv                           210                       # DTB read access violations
+system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
+system.cpu.dtb.write_hits                     6352446                       # DTB write hits
+system.cpu.dtb.write_misses                      1140                       # DTB write misses
+system.cpu.dtb.write_acv                          157                       # DTB write access violations
+system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
+system.cpu.dtb.data_hits                     15409957                       # DTB hits
+system.cpu.dtb.data_misses                      11452                       # DTB misses
+system.cpu.dtb.data_acv                           367                       # DTB access violations
+system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
+system.cpu.itb.fetch_hits                     4973520                       # ITB hits
+system.cpu.itb.fetch_misses                      4997                       # ITB misses
+system.cpu.itb.fetch_acv                          184                       # ITB acv
+system.cpu.itb.fetch_accesses                 4978517                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         56137087                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              52011214                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324192                       # Number of float alu accesses
+system.cpu.num_func_calls                     1482242                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6464616                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52011214                       # number of integer instructions
+system.cpu.num_fp_insts                        324192                       # number of float instructions
+system.cpu.num_int_register_reads            71259077                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38485860                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163510                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166384                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15462519                       # number of memory refs
+system.cpu.num_load_insts                     9094324                       # Number of load instructions
+system.cpu.num_store_insts                    6368195                       # Number of store instructions
+system.cpu.num_idle_cycles               3587943187.998127                       # Number of idle cycles
+system.cpu.num_busy_cycles               243154546.001873                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.063469                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.936531                       # Percentage of idle cycles
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211932                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74887     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1931      1.05%     42.02% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106197     57.98%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183146                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73520     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1931      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73520     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149102                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1857816228500     96.99%     96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                79988500      0.00%     96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               554693000      0.03%     97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             57097199000      2.98%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1915548109000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981746                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692298                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
+system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
+system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
+system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
+system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
+system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
+system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
+system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
+system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
+system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
+system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
+system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
+system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
+system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
+system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
+system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
+system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
+system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
+system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
+system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
+system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
+system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
+system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
+system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
+system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
+system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
+system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
+system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
+system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
+system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
+system.cpu.kern.syscall::total                    326                       # number of syscalls executed
+system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4173      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
+system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175927     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
+system.cpu.kern.callpal::total                 192868                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2092                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1906                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   168                      
+system.cpu.kern.mode_switch_good::kernel     0.322887                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.403193                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        45253274000      2.36%      2.36% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5124228000      0.27%      2.63% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1865170605000     97.37%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
 system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
 system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu.icache.replacements                 927683                       # number of replacements
+system.cpu.icache.tagsinuse                508.721464                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55220553                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 928194                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  59.492469                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            36307428000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            508.721464                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.993597                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0            55220553                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55220553                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0             55220553                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55220553                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0            55220553                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total        55220553                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0            928354                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        928354                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0             928354                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         928354                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0            928354                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        928354                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency    13616370500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency     13616370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency    13616370500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0        56148907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56148907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0         56148907                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56148907                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0        56148907                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.016534                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.016534                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::0       0.016534                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14667.218001                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14667.218001                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                       85                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          928354                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           928354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          928354                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency  10830625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency  10830625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency  10830625500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.016534                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.016534                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.016534                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1390115                       # number of replacements
+system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038335                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1390627                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.094968                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               84029000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.984023                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999969                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0             7807536                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807536                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            5848554                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848554                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        183025                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183025                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         199203                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199203                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             13656090                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13656090                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            13656090                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13656090                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           1069110                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069110                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0           304335                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0        17201                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17201                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0            1373445                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373445                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           1373445                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373445                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    27121920500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    9228484000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency    245980000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     36350404500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    36350404500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         8876646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8876646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6152889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       200226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       199203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         15029535                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15029535                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        15029535                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.120441                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.049462                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.091383                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0       0.091383                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 26466.589124                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 26466.589124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   826586                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1069110                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17201                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1373445                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1373445                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  23914545000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8315479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    194377000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  32230024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  32230024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    862763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1199607500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency   2062370500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.120441                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.049462                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.085908                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.091383                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.091383                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 9933a8e22..84e5e8c3f 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
 boot_cpu_frequency=500
-boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
-memories=system.nvmem system.physmem
+memories=system.physmem system.nvmem
 midr_regval=890224640
+num_work_ids=16
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -31,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -63,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -332,7 +331,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -363,8 +362,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -396,7 +395,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -408,7 +407,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -470,7 +469,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -524,9 +523,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -541,7 +540,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -552,7 +551,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -569,7 +568,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -591,7 +590,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -601,7 +600,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -611,7 +610,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -625,7 +624,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -639,7 +638,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -678,7 +677,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -699,7 +698,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -709,7 +708,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -719,7 +718,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -729,7 +728,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -739,7 +738,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -790,7 +789,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -800,7 +799,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -810,7 +809,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -820,7 +819,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
@@ -841,6 +840,7 @@ port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
 
 [system.vncserver]
 type=VncServer
+frame_capture=false
 number=0
 port=5900
 
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 38da5afa6..417579719 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 18 2011 16:54:46
-gem5 started Aug 18 2011 17:16:56
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 04:25:02
+gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2411694099500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 7f6e2a888..2ca0aa5cb 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.411694                       # Number of seconds simulated
 sim_ticks                                2411694099500                       # Number of ticks simulated
+final_tick                               2411694099500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1186264                       # Simulator instruction rate (inst/s)
-host_tick_rate                            35957520604                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 417168                       # Number of bytes of host memory used
-host_seconds                                    67.07                       # Real time elapsed on the host
+host_inst_rate                                2039542                       # Simulator instruction rate (inst/s)
+host_tick_rate                            61821688958                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 378872                       # Number of bytes of host memory used
+host_seconds                                    39.01                       # Real time elapsed on the host
 sim_insts                                    79563488                       # Number of instructions simulated
+system.nvmem.bytes_read                            68                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                       68                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                             17                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                               28                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                          28                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                              28                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   123270308                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1011392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10185232                       # Number of bytes written to this memory
+system.physmem.num_reads                     14146769                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      869038                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       51113575                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    419370                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4223269                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      55336844                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127720                       # number of replacements
 system.l2c.tagsinuse                     25547.920863                       # Cycle average of tags in use
 system.l2c.total_refs                         1498989                       # Total number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index f7597645c..5b5bd9164 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
 boot_cpu_frequency=500
-boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 memories=system.nvmem system.physmem
 midr_regval=890224640
+num_work_ids=16
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -31,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -63,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -205,7 +204,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -236,8 +235,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -269,7 +268,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -281,7 +280,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -343,7 +342,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -397,9 +396,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -414,7 +413,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -425,7 +424,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -442,7 +441,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -464,7 +463,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -474,7 +473,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -484,7 +483,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -498,7 +497,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -512,7 +511,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -551,7 +550,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -572,7 +571,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -582,7 +581,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -592,7 +591,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -602,7 +601,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -612,7 +611,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -663,7 +662,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -673,7 +672,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -683,7 +682,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -693,7 +692,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
@@ -714,6 +713,7 @@ port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side s
 
 [system.vncserver]
 type=VncServer
+frame_capture=false
 number=0
 port=5900
 
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 832aec59f..e355498ce 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 18 2011 16:54:46
-gem5 started Aug 18 2011 17:16:56
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 04:24:55
+gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2332316587000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index c4ace942b..e3050fa31 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.332317                       # Number of seconds simulated
 sim_ticks                                2332316587000                       # Number of ticks simulated
+final_tick                               2332316587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1407778                       # Simulator instruction rate (inst/s)
-host_tick_rate                            42901571145                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 417476                       # Number of bytes of host memory used
-host_seconds                                    54.36                       # Real time elapsed on the host
+host_inst_rate                                2072038                       # Simulator instruction rate (inst/s)
+host_tick_rate                            63144661085                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379208                       # Number of bytes of host memory used
+host_seconds                                    36.94                       # Real time elapsed on the host
 sim_insts                                    76532931                       # Number of instructions simulated
+system.nvmem.bytes_read                            20                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                       20                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                              5                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                                9                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                           9                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                               9                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   122663536                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 941280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  9577800                       # Number of bytes written to this memory
+system.physmem.num_reads                     14137126                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      856485                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       52593004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    403582                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4106561                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      56699565                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        116822                       # number of replacements
 system.l2c.tagsinuse                     24240.388378                       # Cycle average of tags in use
 system.l2c.total_refs                         1520830                       # Total number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 7186b34ef..82d6c82a5 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
 boot_cpu_frequency=500
-boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.nvmem system.physmem
+memories=system.physmem system.nvmem
 midr_regval=890224640
+num_work_ids=16
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -31,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -63,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -326,7 +325,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -357,8 +356,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -390,7 +389,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -402,7 +401,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -464,7 +463,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -518,9 +517,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -535,7 +534,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -546,7 +545,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -563,7 +562,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -585,7 +584,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -595,7 +594,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -605,7 +604,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -619,7 +618,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -633,7 +632,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -672,7 +671,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -693,7 +692,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -703,7 +702,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -713,7 +712,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -723,7 +722,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -733,7 +732,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -784,7 +783,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -794,7 +793,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -804,7 +803,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -814,7 +813,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
@@ -835,6 +834,7 @@ port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
 
 [system.vncserver]
 type=VncServer
+frame_capture=false
 number=0
 port=5900
 
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index d4218de20..2f40c0e53 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 18 2011 16:54:46
-gem5 started Aug 18 2011 17:16:56
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 04:25:02
+gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2669611225000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 4e104d3a4..6f6f084e3 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.669611                       # Number of seconds simulated
 sim_ticks                                2669611225000                       # Number of ticks simulated
+final_tick                               2669611225000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 491804                       # Simulator instruction rate (inst/s)
-host_tick_rate                            16743499108                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 418920                       # Number of bytes of host memory used
-host_seconds                                   159.44                       # Real time elapsed on the host
+host_inst_rate                                 842154                       # Simulator instruction rate (inst/s)
+host_tick_rate                            28671225175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 380676                       # Number of bytes of host memory used
+host_seconds                                    93.11                       # Real time elapsed on the host
 sim_insts                                    78413959                       # Number of instructions simulated
+system.nvmem.bytes_read                            68                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                       68                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                             17                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                               25                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                          25                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                              25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   134334820                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1003520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10194256                       # Number of bytes written to this memory
+system.physmem.num_reads                     15523876                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      869239                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       50319994                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    375905                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       3818629                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      54138623                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127749                       # number of replacements
 system.l2c.tagsinuse                     26172.513439                       # Cycle average of tags in use
 system.l2c.total_refs                         1540412                       # Total number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 8c21a92dd..b4466ea53 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
 boot_cpu_frequency=500
-boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 memories=system.nvmem system.physmem
 midr_regval=890224640
+num_work_ids=16
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -31,20 +32,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[7]
 
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
 
 [system.cf0]
 type=IdeDisk
@@ -63,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -202,7 +201,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -233,8 +232,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
 
 [system.l2c]
 type=BaseCache
@@ -266,7 +265,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
 
 [system.membus]
 type=Bus
@@ -278,7 +277,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -340,7 +339,7 @@ pio_addr=268451840
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
 
 [system.realview.cf_ctrl]
 type=IdeController
@@ -394,9 +393,9 @@ pci_func=0
 pio_latency=1000
 platform=system.realview
 system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -411,7 +410,7 @@ pio_latency=10000
 platform=system.realview
 system=system
 vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
 pio=system.iobus.port[5]
 
 [system.realview.dmac_fake]
@@ -422,7 +421,7 @@ pio_addr=268632064
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
 
 [system.realview.flash_fake]
 type=IsaFake
@@ -439,7 +438,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
 
 [system.realview.gic]
 type=Gic
@@ -461,7 +460,7 @@ pio_addr=268513280
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.realview.gpio1_fake]
 type=AmbaFake
@@ -471,7 +470,7 @@ pio_addr=268517376
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.realview.gpio2_fake]
 type=AmbaFake
@@ -481,7 +480,7 @@ pio_addr=268521472
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
 
 [system.realview.kmi0]
 type=Pl050
@@ -495,7 +494,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -509,7 +508,7 @@ pio_latency=1000
 platform=system.realview
 system=system
 vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -548,7 +547,7 @@ pio_addr=268455936
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -569,7 +568,7 @@ pio_addr=268529664
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
 
 [system.realview.sci_fake]
 type=AmbaFake
@@ -579,7 +578,7 @@ pio_addr=268492800
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
 
 [system.realview.smc_fake]
 type=AmbaFake
@@ -589,7 +588,7 @@ pio_addr=269357056
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -599,7 +598,7 @@ pio_addr=268439552
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.realview.ssp_fake]
 type=AmbaFake
@@ -609,7 +608,7 @@ pio_addr=268488704
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
 
 [system.realview.timer0]
 type=Sp804
@@ -660,7 +659,7 @@ pio_addr=268476416
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -670,7 +669,7 @@ pio_addr=268480512
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -680,7 +679,7 @@ pio_addr=268484608
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -690,7 +689,7 @@ pio_addr=268500992
 pio_latency=1000
 platform=system.realview
 system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.terminal]
 type=Terminal
@@ -711,6 +710,7 @@ port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side s
 
 [system.vncserver]
 type=VncServer
+frame_capture=false
 number=0
 port=5900
 
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 8eb08f81f..661533caf 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 18 2011 16:54:46
-gem5 started Aug 18 2011 17:16:56
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 04:25:02
+gem5 executing on zizzer
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2591441692000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 6e7850295..543720998 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -2,12 +2,32 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.591442                       # Number of seconds simulated
 sim_ticks                                2591441692000                       # Number of ticks simulated
+final_tick                               2591441692000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 610490                       # Simulator instruction rate (inst/s)
-host_tick_rate                            20960550015                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 417836                       # Number of bytes of host memory used
-host_seconds                                   123.63                       # Real time elapsed on the host
+host_inst_rate                                 852555                       # Simulator instruction rate (inst/s)
+host_tick_rate                            29271571690                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379496                       # Number of bytes of host memory used
+host_seconds                                    88.53                       # Real time elapsed on the host
 sim_insts                                    75477515                       # Number of instructions simulated
+system.nvmem.bytes_read                            20                       # Number of bytes read from this memory
+system.nvmem.bytes_inst_read                       20                       # Number of instructions bytes read from this memory
+system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
+system.nvmem.num_reads                              5                       # Number of read requests responded to by this memory
+system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
+system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
+system.nvmem.bw_read                                8                       # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read                           8                       # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total                               8                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read                   133655408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 949920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  9634312                       # Number of bytes written to this memory
+system.physmem.num_reads                     15513098                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      857428                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       51575696                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    366560                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       3717742                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      55293438                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        117809                       # number of replacements
 system.l2c.tagsinuse                     24928.376904                       # Cycle average of tags in use
 system.l2c.total_refs                         1535240                       # Total number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index bea7090e9..91a089b4b 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_cpu_frequency=500
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 memories=system.physmem
@@ -31,6 +31,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[3]
 
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
@@ -52,16 +53,13 @@ oem_table_id=
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
+master=system.iobus.port[0]
+slave=system.membus.port[1]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -208,8 +206,8 @@ pio_addr=2305843009213693952
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
@@ -620,6 +618,17 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
+[system.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.iobus]
 type=Bus
 block_size=64
@@ -629,7 +638,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -660,8 +669,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[21]
+mem_side=system.membus.port[4]
 
 [system.l2c]
 type=BaseCache
@@ -693,7 +702,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[5]
 
 [system.membus]
 type=Bus
@@ -705,7 +714,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -745,7 +754,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.pc.com_1]
 type=Uart8250
@@ -755,7 +764,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -786,7 +795,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -803,7 +812,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -820,7 +829,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -837,7 +846,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.pc.i_dont_exist]
 type=IsaFake
@@ -854,7 +863,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.pc.pciconfig]
 type=PciConfigAll
@@ -888,7 +897,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[1]
+pio=system.iobus.port[2]
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
@@ -899,7 +908,7 @@ pio_addr=9223372036854775808
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[2]
+pio=system.iobus.port[3]
 
 [system.pc.south_bridge.ide]
 type=IdeController
@@ -954,9 +963,9 @@ pci_func=0
 pio_latency=1000
 platform=system.pc
 system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
+config=system.iobus.port[5]
+dma=system.iobus.port[6]
+pio=system.iobus.port[4]
 
 [system.pc.south_bridge.ide.disks0]
 type=IdeDisk
@@ -975,7 +984,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -995,7 +1004,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1084,8 +1093,8 @@ pio_addr=4273995776
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
+int_port=system.iobus.port[13]
+pio=system.iobus.port[12]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1098,7 +1107,7 @@ pio_addr=0
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[4]
+pio=system.iobus.port[7]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1116,7 +1125,7 @@ pio_latency=1000
 platform=system.pc
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.port[5]
+pio=system.iobus.port[8]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1131,7 +1140,7 @@ pio_latency=1000
 platform=system.pc
 slave=Null
 system=system
-pio=system.iobus.port[6]
+pio=system.iobus.port[9]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1144,7 +1153,7 @@ pio_addr=9223372036854775872
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[7]
+pio=system.iobus.port[10]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1156,7 +1165,7 @@ pio_addr=9223372036854775905
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[8]
+pio=system.iobus.port[11]
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index bd3613cfe..23cf47db2 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 20:47:38
-gem5 started Jan  9 2012 21:03:15
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled Jan 23 2012 04:12:17
+gem5 started Jan 23 2012 04:24:46
+gem5 executing on zizzer
+command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index dc005fb66..324bf8929 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.112043                       # Number of seconds simulated
 sim_ticks                                5112043255000                       # Number of ticks simulated
+final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2860366                       # Simulator instruction rate (inst/s)
-host_tick_rate                            35739722021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 375540                       # Number of bytes of host memory used
-host_seconds                                   143.04                       # Real time elapsed on the host
+host_inst_rate                                2850135                       # Simulator instruction rate (inst/s)
+host_tick_rate                            35611898535                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353172                       # Number of bytes of host memory used
+host_seconds                                   143.55                       # Real time elapsed on the host
 sim_insts                                   409133277                       # Number of instructions simulated
+system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 972736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 12232896                       # Number of bytes written to this memory
+system.physmem.num_reads                       243261                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      191139                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3045495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    190283                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2392956                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5438452                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        164044                       # number of replacements
 system.l2c.tagsinuse                     36842.944085                       # Cycle average of tags in use
 system.l2c.total_refs                         3332458                       # Total number of references to valid blocks.
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 3130a22aa..e3a339662 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_cpu_frequency=500
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -31,6 +31,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[3]
 
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
@@ -52,16 +53,13 @@ oem_table_id=
 [system.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
+master=system.iobus.port[0]
+slave=system.membus.port[1]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -205,8 +203,8 @@ pio_addr=2305843009213693952
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
@@ -617,6 +615,17 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
+[system.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.iobus]
 type=Bus
 block_size=64
@@ -626,7 +635,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -657,8 +666,8 @@ tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[21]
+mem_side=system.membus.port[4]
 
 [system.l2c]
 type=BaseCache
@@ -690,7 +699,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[5]
 
 [system.membus]
 type=Bus
@@ -702,7 +711,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -742,7 +751,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
 
 [system.pc.com_1]
 type=Uart8250
@@ -752,7 +761,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -783,7 +792,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -800,7 +809,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -817,7 +826,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -834,7 +843,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
 
 [system.pc.i_dont_exist]
 type=IsaFake
@@ -851,7 +860,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
 
 [system.pc.pciconfig]
 type=PciConfigAll
@@ -885,7 +894,7 @@ pio_latency=1000
 platform=system.pc
 system=system
 time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[1]
+pio=system.iobus.port[2]
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
@@ -896,7 +905,7 @@ pio_addr=9223372036854775808
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[2]
+pio=system.iobus.port[3]
 
 [system.pc.south_bridge.ide]
 type=IdeController
@@ -951,9 +960,9 @@ pci_func=0
 pio_latency=1000
 platform=system.pc
 system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
+config=system.iobus.port[5]
+dma=system.iobus.port[6]
+pio=system.iobus.port[4]
 
 [system.pc.south_bridge.ide.disks0]
 type=IdeDisk
@@ -972,7 +981,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -992,7 +1001,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1081,8 +1090,8 @@ pio_addr=4273995776
 pio_latency=1000
 platform=system.pc
 system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
+int_port=system.iobus.port[13]
+pio=system.iobus.port[12]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1095,7 +1104,7 @@ pio_addr=0
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[4]
+pio=system.iobus.port[7]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1113,7 +1122,7 @@ pio_latency=1000
 platform=system.pc
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.port[5]
+pio=system.iobus.port[8]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1128,7 +1137,7 @@ pio_latency=1000
 platform=system.pc
 slave=Null
 system=system
-pio=system.iobus.port[6]
+pio=system.iobus.port[9]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1141,7 +1150,7 @@ pio_addr=9223372036854775872
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[7]
+pio=system.iobus.port[10]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1153,7 +1162,7 @@ pio_addr=9223372036854775905
 pio_latency=1000
 platform=system.pc
 system=system
-pio=system.iobus.port[8]
+pio=system.iobus.port[11]
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index ec51a2abf..5dde537a2 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  9 2012 20:47:38
-gem5 started Jan  9 2012 21:05:49
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Jan 23 2012 04:12:17
+gem5 started Jan 23 2012 04:24:49
+gem5 executing on zizzer
+command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 3c6185134..c4a248e5e 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.195470                       # Number of seconds simulated
 sim_ticks                                5195470393000                       # Number of ticks simulated
+final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1858401                       # Simulator instruction rate (inst/s)
-host_tick_rate                            36414646229                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 372180                       # Number of bytes of host memory used
-host_seconds                                   142.68                       # Real time elapsed on the host
+host_inst_rate                                1681123                       # Simulator instruction rate (inst/s)
+host_tick_rate                            32940960656                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 349824                       # Number of bytes of host memory used
+host_seconds                                   157.72                       # Real time elapsed on the host
 sim_insts                                   265147881                       # Number of instructions simulated
+system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 974400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10427072                       # Number of bytes written to this memory
+system.physmem.num_reads                       215064                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      162923                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2649249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    187548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2006954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       4656204                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        136133                       # number of replacements
 system.l2c.tagsinuse                     31389.895470                       # Cycle average of tags in use
 system.l2c.total_refs                         3363370                       # Total number of references to valid blocks.
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 9d8c34c47..eb497bb90 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.cpu0]
 type=DerivO3CPU
@@ -458,7 +460,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -1802,7 +1804,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0]
+port=system.l2c.mem_side system.physmem.port[0] system.system_port
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 709d070a3..0491d5141 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 21 2011 16:13:49
-gem5 started Nov 21 2011 20:51:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:31
+gem5 executing on zizzer
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index faa6a7461..191a42060 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000104                       # Number of seconds simulated
 sim_ticks                                   104317500                       # Number of ticks simulated
+final_tick                                  104317500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97517                       # Simulator instruction rate (inst/s)
-host_tick_rate                                9983124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222460                       # Number of bytes of host memory used
-host_seconds                                    10.45                       # Real time elapsed on the host
+host_inst_rate                                 132902                       # Simulator instruction rate (inst/s)
+host_tick_rate                               13605540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226920                       # Number of bytes of host memory used
+host_seconds                                     7.67                       # Real time elapsed on the host
 sim_insts                                     1018993                       # Number of instructions simulated
+system.physmem.bytes_read                       41984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  28224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          656                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      402463633                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 270558631                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     402463633                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu0.numCycles                          208636                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index ecad4bd59..65fcae2f7 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[2]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -493,7 +496,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0]
+port=system.l2c.mem_side system.physmem.port[0] system.system_port
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 6a0f61930..8daa6c894 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:20:42
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:32
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 3e195d951..0cc0a830c 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000088                       # Number of seconds simulated
 sim_ticks                                    87713500                       # Number of ticks simulated
+final_tick                                   87713500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1078389                       # Simulator instruction rate (inst/s)
-host_tick_rate                              139642648                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1152620                       # Number of bytes of host memory used
-host_seconds                                     0.63                       # Real time elapsed on the host
+host_inst_rate                                1650324                       # Simulator instruction rate (inst/s)
+host_tick_rate                              213702670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1140448                       # Number of bytes of host memory used
+host_seconds                                     0.41                       # Real time elapsed on the host
 sim_insts                                      677340                       # Number of instructions simulated
+system.physmem.bytes_read                       35776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  22272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          559                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      407873360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                 253917584                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     407873360                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 2570db111..ae7e021b5 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[1]
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -127,7 +130,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -481,7 +484,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.l2c.mem_side system.physmem.port[0]
+port=system.l2c.mem_side system.system_port system.physmem.port[0]
 
 [system.physmem]
 type=PhysicalMemory
@@ -491,7 +494,7 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.port[2]
 
 [system.toL2Bus]
 type=Bus
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 6949b715b..6f90c0dd1 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May  1 2011 16:25:10
-M5 started May  1 2011 16:26:16
-M5 executing on u200439-lin.austin.arm.com
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 04:24:33
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index e12a86eb8..0ce3fe3af 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -2,12 +2,22 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000262                       # Number of seconds simulated
 sim_ticks                                   262298000                       # Number of ticks simulated
+final_tick                                  262298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 557035                       # Simulator instruction rate (inst/s)
-host_tick_rate                              220601847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235124                       # Number of bytes of host memory used
-host_seconds                                     1.19                       # Real time elapsed on the host
+host_inst_rate                                1158712                       # Simulator instruction rate (inst/s)
+host_tick_rate                              458877844                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222944                       # Number of bytes of host memory used
+host_seconds                                     0.57                       # Real time elapsed on the host
 sim_insts                                      662307                       # Number of instructions simulated
+system.physmem.bytes_read                       36608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  22656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                          572                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      139566447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  86375039                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     139566447                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu0.numCycles                          524596                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index c172a6305..b96bfd745 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu0]
 type=MemTest
@@ -229,6 +232,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -237,6 +241,7 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -278,6 +283,7 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -286,6 +292,7 @@ start_index_bit=6
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -327,6 +334,7 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -335,6 +343,7 @@ start_index_bit=6
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -376,6 +385,7 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -384,6 +394,7 @@ start_index_bit=6
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -425,6 +436,7 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -433,6 +445,7 @@ start_index_bit=6
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -474,6 +487,7 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -482,6 +496,7 @@ start_index_bit=6
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -523,6 +538,7 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -531,6 +547,7 @@ start_index_bit=6
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -572,6 +589,7 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -580,6 +598,7 @@ start_index_bit=6
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -618,6 +637,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -631,11 +651,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -895,8 +915,14 @@ hot_lines=false
 num_of_sequencers=8
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index 39b93ed95..83d47d194 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jun/30/2011 15:33:35
+Real time: Jan/23/2012 04:26:12
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 376
-Elapsed_time_in_minutes: 6.26667
-Elapsed_time_in_hours: 0.104444
-Elapsed_time_in_days: 0.00435185
+Elapsed_time_in_seconds: 251
+Elapsed_time_in_minutes: 4.18333
+Elapsed_time_in_hours: 0.0697222
+Elapsed_time_in_days: 0.00290509
 
-Virtual_time_in_seconds: 376.16
-Virtual_time_in_minutes: 6.26933
-Virtual_time_in_hours:   0.104489
-Virtual_time_in_days:    0.0043537
+Virtual_time_in_seconds: 250.81
+Virtual_time_in_minutes: 4.18017
+Virtual_time_in_hours:   0.0696694
+Virtual_time_in_days:    0.00290289
 
 Ruby_current_time: 22570074
 Ruby_start_time: 0
 Ruby_cycles: 22570074
 
-mbytes_resident: 38.7617
-mbytes_total: 350.738
-resident_ratio: 0.110515
+mbytes_resident: 41.8906
+mbytes_total: 339.688
+resident_ratio: 0.123321
 
 ruby_cycles_executed: [ 22570075 22570075 22570075 22570075 22570075 22570075 22570075 22570075 ]
 
@@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 20 count: 3083256 average: 0.208137 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 376
+user_time: 250
 system_time: 0
-page_reclaims: 11076
+page_reclaims: 11074
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 208
 
 Network Stats
 -------------
@@ -339,12 +339,16 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 76861
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76861
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.1254%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.8746%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76861    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -467,12 +471,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 76155
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76155
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   64.9005%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   35.0995%
+
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   76155    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -483,12 +491,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 75468
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 75468
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   65.2581%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   34.7419%
+
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   75468    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -499,12 +511,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 75945
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 75945
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7745%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2255%
+
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   75945    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -515,12 +531,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 75521
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 75521
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.0945%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.9055%
+
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   75521    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -531,12 +551,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 75953
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 75953
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.1521%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.8479%
+
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   75953    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -547,12 +571,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 75611
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 75611
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.7128%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.2872%
+
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   75611    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -563,20 +591,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 76345
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76345
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.6264%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.3736%
+
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76345    100%
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 0
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_misses: 607517
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 607517
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   64.962%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   35.038%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   607517    100%
 
  --- L2Cache ---
  - Event Counts -
@@ -870,4 +906,5 @@ M_DWRI  Fetch [0 ] 0
 M_DWRI  Data [0 ] 0
 M_DWRI  Memory_Ack [0 ] 0
 M_DWRI  DMA_READ [0 ] 0
-M_DWRI  DMA_WRITE
\ No newline at end of file
+M_DWRI  DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index f9f7ece6e..20caf030d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 30 2011 15:26:55
-gem5 started Jun 30 2011 15:27:19
-gem5 executing on SC2B0622
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:22:01
+gem5 executing on zizzer
 command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index 83df7bbab..bb265760e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -2,10 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.022570                       # Number of seconds simulated
 sim_ticks                                    22570074                       # Number of ticks simulated
+final_tick                                   22570074                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  60026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 359160                       # Number of bytes of host memory used
-host_seconds                                   376.01                       # Real time elapsed on the host
+host_tick_rate                                  89999                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347844                       # Number of bytes of host memory used
+host_seconds                                   250.78                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          53615                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index 7275a3b0b..e0267adf3 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu0]
 type=MemTest
@@ -226,6 +229,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -234,6 +238,7 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -273,6 +278,7 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -281,6 +287,7 @@ start_index_bit=6
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -320,6 +327,7 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -328,6 +336,7 @@ start_index_bit=6
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -367,6 +376,7 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -375,6 +385,7 @@ start_index_bit=6
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -414,6 +425,7 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -422,6 +434,7 @@ start_index_bit=6
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -461,6 +474,7 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -469,6 +483,7 @@ start_index_bit=6
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -508,6 +523,7 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -516,6 +532,7 @@ start_index_bit=6
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -555,6 +572,7 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -563,6 +581,7 @@ start_index_bit=6
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -600,6 +619,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -613,11 +633,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -877,8 +897,14 @@ hot_lines=false
 num_of_sequencers=8
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index 13f2004d5..78fcf4ec9 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jun/30/2011 15:16:36
+Real time: Jan/23/2012 04:26:05
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 350
-Elapsed_time_in_minutes: 5.83333
-Elapsed_time_in_hours: 0.0972222
-Elapsed_time_in_days: 0.00405093
+Elapsed_time_in_seconds: 233
+Elapsed_time_in_minutes: 3.88333
+Elapsed_time_in_hours: 0.0647222
+Elapsed_time_in_days: 0.00269676
 
-Virtual_time_in_seconds: 350.08
-Virtual_time_in_minutes: 5.83467
-Virtual_time_in_hours:   0.0972444
-Virtual_time_in_days:    0.00405185
+Virtual_time_in_seconds: 232.61
+Virtual_time_in_minutes: 3.87683
+Virtual_time_in_hours:   0.0646139
+Virtual_time_in_days:    0.00269225
 
 Ruby_current_time: 19400856
 Ruby_start_time: 0
 Ruby_cycles: 19400856
 
-mbytes_resident: 38.9531
-mbytes_total: 350.996
-resident_ratio: 0.11099
+mbytes_resident: 42.1172
+mbytes_total: 339.848
+resident_ratio: 0.12393
 
 ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ]
 
@@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 350
+user_time: 232
 system_time: 0
-page_reclaims: 11132
+page_reclaims: 11111
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 192
 
 Network Stats
 -------------
@@ -1790,4 +1790,5 @@ MD  PUTO [0 ] 0
 MD  PUTO_SHARERS [0 ] 0
 MD  DMA_READ [0 ] 0
 MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK
\ No newline at end of file
+MD  DMA_ACK [0 ] 0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 695aa9c74..b246a2d4a 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 30 2011 15:10:22
-gem5 started Jun 30 2011 15:10:46
-gem5 executing on SC2B0622
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
 command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index b7a70d7a6..ec3afa4a7 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -2,10 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.019401                       # Number of seconds simulated
 sim_ticks                                    19400856                       # Number of ticks simulated
+final_tick                                   19400856                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  55434                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 359424                       # Number of bytes of host memory used
-host_seconds                                   349.98                       # Real time elapsed on the host
+host_tick_rate                                  83409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348008                       # Number of bytes of host memory used
+host_seconds                                   232.60                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                           98844                       # number of read accesses completed
 system.cpu0.num_writes                          53478                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index 0f765d7ae..84c75eb68 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu0]
 type=MemTest
@@ -235,6 +238,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -243,6 +247,7 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -288,6 +293,7 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -296,6 +302,7 @@ start_index_bit=6
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -341,6 +348,7 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -349,6 +357,7 @@ start_index_bit=6
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -394,6 +403,7 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -402,6 +412,7 @@ start_index_bit=6
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -447,6 +458,7 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -455,6 +467,7 @@ start_index_bit=6
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -500,6 +513,7 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -508,6 +522,7 @@ start_index_bit=6
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -553,6 +568,7 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -561,6 +577,7 @@ start_index_bit=6
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -606,6 +623,7 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -614,6 +632,7 @@ start_index_bit=6
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -653,6 +672,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
 size=512
@@ -666,11 +686,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -930,8 +950,14 @@ hot_lines=false
 num_of_sequencers=8
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index c2742878d..5b7a6fff2 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jun/30/2011 15:40:53
+Real time: Jan/23/2012 04:24:27
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 176
-Elapsed_time_in_minutes: 2.93333
-Elapsed_time_in_hours: 0.0488889
-Elapsed_time_in_days: 0.00203704
+Elapsed_time_in_seconds: 120
+Elapsed_time_in_minutes: 2
+Elapsed_time_in_hours: 0.0333333
+Elapsed_time_in_days: 0.00138889
 
-Virtual_time_in_seconds: 175.47
-Virtual_time_in_minutes: 2.9245
-Virtual_time_in_hours:   0.0487417
-Virtual_time_in_days:    0.0020309
+Virtual_time_in_seconds: 119.35
+Virtual_time_in_minutes: 1.98917
+Virtual_time_in_hours:   0.0331528
+Virtual_time_in_days:    0.00138137
 
 Ruby_current_time: 19658320
 Ruby_start_time: 0
 Ruby_cycles: 19658320
 
-mbytes_resident: 38.5312
-mbytes_total: 350.477
-resident_ratio: 0.109951
+mbytes_resident: 41.6445
+mbytes_total: 339.402
+resident_ratio: 0.1227
 
 ruby_cycles_executed: [ 19658321 19658321 19658321 19658321 19658321 19658321 19658321 19658321 ]
 
@@ -125,13 +125,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 175
+user_time: 119
 system_time: 0
-page_reclaims: 11261
+page_reclaims: 10999
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 208
 
 Network Stats
 -------------
@@ -1399,4 +1399,5 @@ DR_L  Tokens [0 ] 0
 DR_L  Request_Timeout [0 ] 0
 DR_L  DMA_READ [0 ] 0
 DR_L  DMA_WRITE [0 ] 0
-DR_L  DMA_WRITE_All_Tokens
\ No newline at end of file
+DR_L  DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index f3e44a721..0dc21efd5 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 30 2011 15:37:32
-gem5 started Jun 30 2011 15:37:57
-gem5 executing on SC2B0622
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:27
+gem5 executing on zizzer
 command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 96d2626d3..d79a41535 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -2,10 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.019658                       # Number of seconds simulated
 sim_ticks                                    19658320                       # Number of ticks simulated
+final_tick                                   19658320                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 112174                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 358892                       # Number of bytes of host memory used
-host_seconds                                   175.25                       # Real time elapsed on the host
+host_tick_rate                                 164666                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347552                       # Number of bytes of host memory used
+host_seconds                                   119.38                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          53504                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index b9ae49cc3..74320f307 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem system.funcmem
 num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu0]
 type=MemTest
@@ -717,11 +718,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -959,8 +960,14 @@ hot_lines=false
 num_of_sequencers=8
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index 351f626be..9f2e0a2cf 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/10/2012 12:44:02
+Real time: Jan/23/2012 04:23:36
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 112
-Elapsed_time_in_minutes: 1.86667
-Elapsed_time_in_hours: 0.0311111
-Elapsed_time_in_days: 0.0012963
+Elapsed_time_in_seconds: 107
+Elapsed_time_in_minutes: 1.78333
+Elapsed_time_in_hours: 0.0297222
+Elapsed_time_in_days: 0.00123843
 
-Virtual_time_in_seconds: 111.5
-Virtual_time_in_minutes: 1.85833
-Virtual_time_in_hours:   0.0309722
-Virtual_time_in_days:    0.00129051
+Virtual_time_in_seconds: 107.49
+Virtual_time_in_minutes: 1.7915
+Virtual_time_in_hours:   0.0298583
+Virtual_time_in_days:    0.0012441
 
-Ruby_current_time: 19129228
+Ruby_current_time: 19076439
 Ruby_start_time: 0
-Ruby_cycles: 19129228
+Ruby_cycles: 19076439
 
-mbytes_resident: 37.8594
-mbytes_total: 362.402
-resident_ratio: 0.104489
+mbytes_resident: 41.2852
+mbytes_total: 339.078
+resident_ratio: 0.121757
 
-ruby_cycles_executed: [ 19129229 19129229 19129229 19129229 19129229 19129229 19129229 19129229 ]
+ruby_cycles_executed: [ 19076440 19076440 19076440 19076440 19076440 19076440 19076440 19076440 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -66,35 +66,35 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 614830 average: 15.9984 | standard deviation: 0.127016 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 614710 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 613136 average: 15.9984 | standard deviation: 0.127191 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 613016 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 18400 count: 614702 average: 3982.61 | standard deviation: 2992.13 | 1914 7044 12490 16512 15889 18736 21128 22310 19250 16973 18228 17272 14440 12720 11919 11264 9796 9053 8574 7249 7243 6931 6893 6397 5679 6057 6153 5744 5637 5473 5792 5538 5524 5879 5303 5590 5887 6113 6011 5470 6192 6473 6248 6357 6359 6725 6660 6739 7291 6595 6853 7000 7480 7136 6581 7014 7149 6614 6533 6018 6336 6070 5893 5695 4978 4966 4720 4574 4042 3444 3609 3407 3036 2737 2400 2393 2037 1944 1791 1453 1461 1289 1239 1059 857 864 803 682 596 520 465 370 374 339 249 229 191 202 184 132 137 127 101 94 70 60 65 39 36 36 32 20 22 32 9 8 11 11 9 6 12 5 5 3 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 18400 count: 399338 average: 3984.32 | standard deviation: 2993.07 | 1293 4556 8079 10724 10277 12230 13719 14584 12466 11028 11779 11190 9428 8274 7711 7272 6322 5923 5519 4696 4662 4567 4416 4173 3768 3938 3924 3726 3668 3559 3700 3595 3595 3843 3447 3665 3876 3934 3968 3574 4048 4230 3998 4144 4226 4388 4372 4351 4686 4318 4387 4504 4824 4620 4208 4525 4646 4303 4241 3942 4160 3962 3811 3657 3286 3189 3052 3011 2667 2246 2369 2174 1966 1804 1563 1542 1288 1284 1181 970 934 826 851 676 572 564 527 421 387 353 302 249 249 226 159 151 122 120 123 77 95 90 59 60 45 45 47 23 25 19 19 12 10 23 5 4 6 7 6 4 8 4 3 3 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 18030 count: 215364 average: 3979.43 | standard deviation: 2990.39 | 621 2488 4411 5788 5612 6506 7409 7726 6784 5945 6449 6082 5012 4446 4208 3992 3474 3130 3055 2553 2581 2364 2477 2224 1911 2119 2229 2018 1969 1914 2092 1943 1929 2036 1856 1925 2011 2179 2043 1896 2144 2243 2250 2213 2133 2337 2288 2388 2605 2277 2466 2496 2656 2516 2373 2489 2503 2311 2292 2076 2176 2108 2082 2038 1692 1777 1668 1563 1375 1198 1240 1233 1070 933 837 851 749 660 610 483 527 463 388 383 285 300 276 261 209 167 163 121 125 113 90 78 69 82 61 55 42 37 42 34 25 15 18 16 11 17 13 8 12 9 4 4 5 4 3 2 4 1 2 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 128 max: 18400 count: 613008 average: 3982.62 | standard deviation: 2991.98 | 1907 7027 12453 16474 15845 18678 21073 22250 19210 16951 18183 17228 14390 12685 11884 11226 9753 9022 8545 7231 7216 6897 6866 6372 5663 6032 6139 5722 5632 5450 5777 5524 5508 5866 5290 5574 5878 6096 5990 5454 6175 6454 6237 6342 6339 6710 6642 6724 7271 6583 6832 6981 7466 7120 6561 7001 7133 6599 6513 6004 6322 6050 5882 5678 4966 4956 4706 4560 4034 3440 3593 3395 3030 2731 2397 2387 2033 1938 1786 1447 1457 1286 1233 1057 851 860 801 681 595 518 463 364 372 338 248 228 189 201 182 131 136 127 99 93 70 60 65 38 36 35 32 20 22 32 9 8 11 11 9 6 12 5 5 3 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 18400 count: 398225 average: 3984.55 | standard deviation: 2993.11 | 1287 4543 8056 10700 10250 12192 13683 14543 12441 11010 11748 11157 9395 8251 7689 7248 6295 5900 5500 4685 4642 4548 4399 4155 3756 3922 3916 3709 3663 3546 3691 3588 3583 3833 3439 3656 3870 3923 3953 3565 4037 4215 3989 4135 4211 4379 4361 4340 4671 4313 4374 4490 4818 4610 4195 4518 4637 4291 4226 3932 4150 3950 3804 3644 3279 3180 3044 3000 2663 2244 2358 2167 1961 1801 1561 1538 1287 1283 1178 965 932 823 847 675 567 561 527 421 387 352 301 246 248 226 159 150 121 119 121 77 94 90 59 60 45 45 47 23 25 18 19 12 10 23 5 4 6 7 6 4 8 4 3 3 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 18030 count: 214783 average: 3979.04 | standard deviation: 2989.88 | 620 2484 4397 5774 5595 6486 7390 7707 6769 5941 6435 6071 4995 4434 4195 3978 3458 3122 3045 2546 2574 2349 2467 2217 1907 2110 2223 2013 1969 1904 2086 1936 1925 2033 1851 1918 2008 2173 2037 1889 2138 2239 2248 2207 2128 2331 2281 2384 2600 2270 2458 2491 2648 2510 2366 2483 2496 2308 2287 2072 2172 2100 2078 2034 1687 1776 1662 1560 1371 1196 1235 1228 1069 930 836 849 746 655 608 482 525 463 386 382 284 299 274 260 208 166 162 118 124 112 89 78 68 82 61 54 42 37 40 33 25 15 18 15 11 17 13 8 12 9 4 4 5 4 3 2 4 1 2 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 133 average:     2 | standard deviation: 0 | 0 0 133 ]
-miss_latency_L2Cache: [binsize: 64 max: 6752 count: 563 average: 510.815 | standard deviation: 605.328 | 140 23 36 31 29 33 25 30 22 38 18 13 12 14 11 19 4 8 4 7 4 5 2 1 4 1 1 3 3 5 3 3 1 2 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 18400 count: 594120 average: 4003.79 | standard deviation: 2989.88 | 0 6288 11765 15680 15030 18066 20545 21710 18726 16571 17865 16936 14178 12478 11639 11012 9579 8867 8371 7049 7048 6737 6685 6232 5493 5911 5956 5559 5443 5302 5572 5383 5365 5701 5105 5394 5665 5945 5794 5261 5978 6245 6035 6145 6135 6512 6439 6522 7046 6336 6613 6777 7274 6916 6374 6811 6947 6451 6334 5838 6133 5925 5724 5551 4850 4840 4613 4467 3950 3351 3519 3329 2973 2680 2343 2347 1990 1902 1763 1420 1427 1265 1215 1038 838 843 785 667 584 514 457 362 366 333 242 225 186 201 180 130 135 124 98 94 67 59 64 38 36 35 30 19 22 32 9 8 10 11 9 5 12 5 4 2 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 128 max: 15824 count: 19886 average: 3474.77 | standard deviation: 2989.85 | 1618 689 663 777 799 639 557 570 512 391 354 333 257 238 272 246 214 184 202 199 195 194 208 165 185 146 196 185 194 171 220 155 158 178 198 196 222 168 217 209 214 228 213 212 224 213 221 217 245 259 240 223 205 220 207 203 202 163 199 180 203 145 169 144 128 126 107 107 92 93 90 78 63 57 57 46 47 42 28 33 34 24 24 21 19 21 18 15 12 6 8 8 8 6 7 4 5 1 4 2 2 3 3 0 3 1 1 1 0 1 2 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15681 count: 19858 average: 3294.08 | standard deviation: 2973.13 | 2401 789 781 887 699 566 528 485 416 305 282 260 243 202 195 228 167 178 197 169 200 185 206 145 164 171 203 192 183 160 192 163 182 213 176 211 215 209 201 181 236 224 213 244 216 220 207 217 246 221 241 234 220 216 202 188 200 186 188 162 184 140 147 144 111 92 98 97 81 79 88 73 44 46 45 38 39 33 31 22 36 23 16 13 15 14 11 12 12 5 5 9 6 3 5 4 3 2 2 2 0 2 2 2 2 2 1 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3227 count: 19858 average: 155.74 | standard deviation: 323.185 | 14126 352 258 301 235 217 214 193 257 201 194 199 172 274 199 186 177 173 167 106 89 89 79 113 83 76 64 91 100 74 65 66 55 64 37 43 33 25 31 28 30 28 23 17 21 21 21 14 11 15 16 13 2 16 10 6 9 9 14 9 7 5 4 1 3 2 2 0 0 2 1 0 3 2 5 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 39 count: 19858 average: 24.6141 | standard deviation: 1.15269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14566 121 4592 47 162 198 137 14 11 6 0 2 1 0 0 1 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 15 count: 19858 average: 1.76186 | standard deviation: 1.57127 | 4563 5054 5189 3095 640 542 633 35 49 30 20 5 1 1 0 1 ]
+miss_latency_L2Cache: [binsize: 64 max: 6752 count: 560 average: 508.952 | standard deviation: 604.29 | 140 23 35 31 29 33 25 30 22 37 18 13 12 14 11 19 4 8 4 7 4 5 2 1 4 1 1 3 2 5 3 3 1 2 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 18400 count: 592476 average: 4003.78 | standard deviation: 2989.72 | 0 6272 11730 15642 14987 18010 20490 21655 18688 16550 17820 16892 14128 12443 11607 10974 9537 8836 8342 7031 7021 6704 6659 6208 5479 5886 5943 5537 5438 5279 5557 5370 5349 5688 5094 5380 5656 5930 5773 5245 5961 6226 6024 6130 6115 6498 6422 6507 7027 6324 6593 6758 7260 6900 6355 6799 6932 6436 6315 5825 6120 5905 5713 5534 4838 4830 4600 4453 3942 3347 3503 3317 2967 2674 2340 2341 1986 1896 1758 1415 1423 1262 1209 1036 832 839 783 666 583 512 455 356 364 332 241 224 184 200 178 129 134 124 96 93 67 59 64 37 36 34 30 19 22 32 9 8 10 11 9 5 12 5 4 2 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 128 max: 15824 count: 19839 average: 3475.24 | standard deviation: 2990.25 | 1611 689 661 777 799 637 557 565 510 390 354 333 257 238 270 246 213 184 202 199 195 193 207 164 183 146 195 185 194 171 220 154 158 178 196 194 222 166 217 209 214 228 213 212 224 212 220 217 244 259 239 223 205 220 206 202 201 163 198 179 202 145 169 144 128 126 106 107 92 93 90 78 63 57 57 46 47 42 28 32 34 24 24 21 19 21 18 15 12 6 8 8 8 6 7 4 5 1 4 2 2 3 3 0 3 1 1 1 0 1 2 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15681 count: 19811 average: 3294.71 | standard deviation: 2973.49 | 2393 788 778 887 698 565 526 482 416 304 282 259 243 202 195 228 166 178 196 169 200 184 205 143 162 171 202 192 182 160 192 162 182 213 175 210 215 208 201 181 236 224 212 244 216 218 207 216 246 221 241 234 219 215 202 187 199 186 187 162 183 140 147 144 111 92 97 97 81 79 88 73 44 46 45 38 39 33 31 21 36 23 16 13 15 14 11 12 12 5 5 9 6 3 5 4 3 2 2 2 0 2 2 2 2 2 1 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3227 count: 19811 average: 155.584 | standard deviation: 322.971 | 14095 352 257 301 235 217 214 193 254 201 193 196 172 273 199 186 177 173 167 105 89 89 79 112 83 76 63 90 100 74 65 66 55 64 37 43 32 25 31 28 30 28 23 17 20 21 21 14 11 15 16 13 2 16 9 6 9 9 14 9 7 5 4 1 3 2 2 0 0 2 1 0 3 2 5 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 39 count: 19811 average: 24.6142 | standard deviation: 1.1529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14531 121 4581 47 162 197 137 14 11 6 0 2 1 0 0 1 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 15 count: 19811 average: 1.76145 | standard deviation: 1.57115 | 4554 5044 5173 3088 639 541 631 34 49 30 20 5 1 1 0 1 ]
 imcomplete_wCC_Times: 28
-miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18051 count: 594120 average: 3281.74 | standard deviation: 2955.22 | 70915 24061 22485 26839 20864 17583 15751 15347 11377 8651 8866 8376 7098 6392 6188 6335 5844 5688 5995 5148 5493 5406 5729 5236 4904 5474 5677 5276 5294 5230 5687 5306 5544 5949 5507 5825 5899 6456 6280 5788 6493 6783 6606 6801 6509 7149 6995 6970 7338 6522 6865 6751 6975 6391 5739 6040 6136 5568 5202 4825 4915 4299 4091 3958 3278 3193 2978 2814 2503 2209 2089 1919 1708 1485 1349 1302 1116 983 929 762 676 640 625 473 398 444 343 272 272 225 183 158 130 128 119 92 112 80 74 64 52 40 17 28 22 12 18 12 19 14 9 9 10 4 6 3 4 9 3 1 2 2 2 4 0 3 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_dir_initial_forward_request: [binsize: 16 max: 3183 count: 594120 average: 11.5723 | standard deviation: 55.3785 | 590603 289 44 73 70 75 38 102 87 47 78 59 67 83 44 68 38 61 59 29 47 29 45 48 25 45 29 41 35 27 55 30 62 61 46 66 36 65 72 30 61 32 65 51 30 43 18 39 41 14 23 22 26 39 12 19 11 22 24 16 32 13 22 30 11 19 10 26 25 12 24 10 17 19 7 15 9 17 14 5 11 8 12 10 5 13 2 4 9 3 7 3 4 7 7 9 0 6 9 5 3 3 5 7 4 7 3 3 4 2 3 0 1 3 3 3 2 2 6 7 2 1 1 3 0 0 3 2 2 3 2 0 0 1 0 1 2 1 4 0 1 2 2 2 1 2 2 2 1 0 0 1 0 1 1 4 1 1 0 0 1 0 1 2 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 44 count: 594120 average: 24.8307 | standard deviation: 1.27614 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 381219 4947 183412 1522 7686 8318 5658 619 334 251 69 48 31 2 1 0 2 0 0 0 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4704 count: 594120 average: 685.644 | standard deviation: 462.597 | 0 0 0 14505 19454 17157 18632 21836 25332 21411 20516 20005 22296 24193 19296 17974 16634 16790 17488 13769 13634 13397 14499 15945 13165 13170 12959 14154 14461 10808 9503 8069 7842 7793 6041 5729 5422 5551 5820 4543 4542 4418 4789 4771 3559 3168 2848 2806 2691 2046 1922 1832 1861 1938 1548 1493 1390 1485 1485 1031 1022 860 944 857 675 579 560 607 596 451 494 416 404 478 307 324 254 259 253 203 193 173 174 163 112 124 127 108 111 94 80 75 54 61 54 42 41 40 45 38 24 28 24 18 16 12 10 20 7 7 4 5 8 7 6 7 4 8 8 4 3 1 2 2 4 2 2 0 1 1 0 1 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18051 count: 592476 average: 3281.72 | standard deviation: 2955.08 | 70738 24002 22428 26767 20802 17537 15706 15298 11350 8629 8834 8349 7073 6369 6165 6306 5814 5671 5976 5128 5478 5387 5706 5221 4890 5461 5662 5263 5277 5218 5675 5295 5531 5934 5491 5800 5887 6442 6263 5774 6483 6771 6588 6782 6489 7137 6981 6950 7319 6513 6851 6728 6955 6376 5730 6024 6115 5555 5189 4810 4902 4288 4077 3946 3271 3184 2971 2807 2494 2203 2085 1914 1703 1482 1343 1299 1108 980 926 758 674 638 624 469 397 443 342 270 271 222 182 157 129 127 119 91 112 77 74 63 52 40 17 28 22 12 18 12 19 14 9 9 10 4 6 3 4 9 3 1 2 2 2 4 0 3 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 16 max: 3183 count: 592476 average: 11.5725 | standard deviation: 55.3766 | 588970 287 43 73 70 75 38 101 87 46 78 59 67 83 44 68 38 61 59 29 47 28 45 46 25 45 29 41 35 27 55 30 62 61 46 66 36 65 72 30 61 32 65 51 30 43 18 39 41 14 23 22 26 39 12 19 11 22 24 16 32 13 22 30 10 19 10 26 25 12 24 10 17 19 7 15 8 17 14 5 11 8 12 10 5 13 2 4 9 3 7 3 4 6 7 9 0 6 9 5 3 3 5 7 4 7 3 3 4 2 3 0 1 3 3 3 2 2 6 7 2 1 1 3 0 0 3 2 2 3 2 0 0 1 0 1 2 1 4 0 1 2 2 2 1 2 2 2 1 0 0 1 0 1 1 4 1 1 0 0 1 0 1 2 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 44 count: 592476 average: 24.8308 | standard deviation: 1.27632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 380177 4933 182882 1518 7662 8302 5647 616 334 251 69 48 31 2 1 0 2 0 0 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4704 count: 592476 average: 685.659 | standard deviation: 462.491 | 0 0 0 14464 19382 17090 18564 21773 25259 21342 20460 19953 22247 24131 19251 17928 16594 16740 17436 13730 13612 13360 14457 15897 13132 13130 12935 14117 14423 10787 9485 8050 7825 7770 6022 5721 5406 5541 5804 4526 4531 4411 4773 4755 3548 3161 2840 2801 2682 2038 1914 1826 1855 1934 1543 1490 1384 1482 1482 1029 1018 859 937 852 670 579 559 605 593 449 492 416 403 476 305 323 254 257 252 203 193 173 174 161 112 123 126 106 110 94 80 75 54 61 54 42 40 40 44 38 24 28 24 18 16 12 10 20 7 7 4 5 8 7 6 6 4 8 8 4 3 1 2 2 4 2 2 0 1 1 0 1 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 imcomplete_dir_Times: 0
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 95 average:     2 | standard deviation: 0 | 0 0 95 ]
-miss_latency_LD_L2Cache: [binsize: 32 max: 3352 count: 371 average: 490.28 | standard deviation: 558.933 | 88 17 6 9 14 11 12 9 9 11 6 12 6 5 10 6 6 6 14 13 3 6 4 6 3 6 2 5 5 5 0 12 2 0 2 2 1 1 2 1 1 2 0 3 0 1 0 1 2 1 0 1 1 0 0 3 1 0 2 1 0 2 0 2 0 1 0 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_Directory: [binsize: 128 max: 18400 count: 385874 average: 4005.47 | standard deviation: 2990.64 | 0 4056 7628 10185 9716 11799 13351 14190 12136 10766 11544 10977 9253 8118 7530 7094 6181 5799 5395 4567 4540 4430 4274 4067 3645 3840 3797 3603 3549 3439 3549 3492 3491 3721 3315 3545 3726 3827 3835 3445 3896 4083 3868 4004 4068 4243 4229 4205 4528 4161 4239 4357 4684 4481 4075 4394 4519 4193 4111 3819 4025 3866 3715 3561 3202 3100 2988 2933 2604 2182 2315 2128 1924 1763 1524 1510 1254 1256 1160 945 909 810 833 661 560 551 515 411 382 349 295 244 243 220 154 148 120 119 119 76 95 88 57 60 44 44 46 23 25 18 19 12 10 23 5 4 6 7 6 3 8 4 3 2 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15824 count: 12998 average: 3485.28 | standard deviation: 2996.01 | 1078 454 413 512 522 412 352 372 324 257 229 211 171 152 177 174 138 122 123 128 122 137 142 106 122 98 126 123 119 120 151 103 104 122 132 120 150 107 133 129 152 147 130 140 158 145 143 146 158 157 148 147 140 139 133 131 127 110 130 123 135 96 96 96 84 89 64 78 63 64 54 46 42 41 39 32 34 28 21 25 25 16 18 15 12 13 12 10 5 4 7 5 6 6 5 3 2 1 4 1 0 2 2 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L2Cache: [binsize: 32 max: 3352 count: 370 average: 491.168 | standard deviation: 559.428 | 88 17 6 9 14 10 12 9 9 11 6 12 6 5 10 6 6 6 14 13 3 6 4 6 3 6 2 5 5 5 0 12 2 0 2 2 1 1 2 1 1 2 0 3 0 1 0 1 2 1 0 1 1 0 0 3 1 0 2 1 0 2 0 2 0 1 0 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 128 max: 18400 count: 384794 average: 4005.68 | standard deviation: 2990.67 | 0 4044 7606 10161 9689 11763 13315 14152 12112 10749 11513 10944 9220 8095 7509 7070 6155 5776 5376 4556 4520 4412 4258 4050 3634 3824 3789 3586 3544 3426 3540 3485 3479 3711 3307 3538 3720 3817 3820 3436 3885 4068 3859 3995 4053 4235 4219 4194 4514 4156 4227 4343 4678 4471 4063 4388 4511 4181 4097 3810 4015 3854 3708 3548 3195 3091 2980 2922 2600 2180 2304 2121 1919 1760 1522 1506 1253 1255 1157 940 907 807 829 660 555 548 515 411 382 348 294 241 242 220 154 147 119 118 117 76 94 88 57 60 44 44 46 23 25 17 19 12 10 23 5 4 6 7 6 3 8 4 3 2 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15824 count: 12966 average: 3486.33 | standard deviation: 2996.66 | 1072 454 412 512 522 410 352 369 323 256 229 211 171 152 176 174 137 122 123 128 122 136 141 105 121 98 126 123 119 120 151 103 104 122 132 118 150 106 133 129 152 147 130 140 158 144 142 146 157 157 147 147 140 139 132 130 126 110 129 122 135 96 96 96 84 89 64 78 63 64 54 46 42 41 39 32 34 28 21 25 25 16 18 15 12 13 12 10 5 4 7 5 6 6 5 3 2 1 4 1 0 2 2 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 38 average:     2 | standard deviation: 0 | 0 0 38 ]
-miss_latency_ST_L2Cache: [binsize: 64 max: 6752 count: 192 average: 550.495 | standard deviation: 685.986 | 35 8 11 10 9 15 14 14 10 11 9 3 3 7 1 7 2 4 2 4 1 2 1 0 1 0 0 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 128 max: 18030 count: 208246 average: 4000.67 | standard deviation: 2988.48 | 0 2232 4137 5495 5314 6267 7194 7520 6590 5805 6321 5959 4925 4360 4109 3918 3398 3068 2976 2482 2508 2307 2411 2165 1848 2071 2159 1956 1894 1863 2023 1891 1874 1980 1790 1849 1939 2118 1959 1816 2082 2162 2167 2141 2067 2269 2210 2317 2518 2175 2374 2420 2590 2435 2299 2417 2428 2258 2223 2019 2108 2059 2009 1990 1648 1740 1625 1534 1346 1169 1204 1201 1049 917 819 837 736 646 603 475 518 455 382 377 278 292 270 256 202 165 162 118 123 113 88 77 66 82 61 54 40 36 41 34 23 15 18 15 11 17 11 7 12 9 4 4 4 4 3 2 4 1 1 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15717 count: 6888 average: 3454.94 | standard deviation: 2978.32 | 540 235 250 265 277 227 205 198 188 134 125 122 86 86 95 72 76 62 79 71 73 57 66 59 63 48 70 62 75 51 69 52 54 56 66 76 72 61 84 80 62 81 83 72 66 68 78 71 87 102 92 76 65 81 74 72 75 53 69 57 68 49 73 48 44 37 43 29 29 29 36 32 21 16 18 14 13 14 7 8 9 8 6 6 7 8 6 5 7 2 1 3 2 0 2 1 3 0 0 1 2 1 1 0 2 0 0 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L2Cache: [binsize: 64 max: 6752 count: 190 average: 543.584 | standard deviation: 683.521 | 35 8 11 10 9 15 14 14 10 10 9 3 3 7 1 7 2 4 2 4 1 2 1 0 1 0 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 18030 count: 207682 average: 4000.27 | standard deviation: 2987.96 | 0 2228 4124 5481 5298 6247 7175 7503 6576 5801 6307 5948 4908 4348 4098 3904 3382 3060 2966 2475 2501 2292 2401 2158 1845 2062 2154 1951 1894 1853 2017 1885 1870 1977 1787 1842 1936 2113 1953 1809 2076 2158 2165 2135 2062 2263 2203 2313 2513 2168 2366 2415 2582 2429 2292 2411 2421 2255 2218 2015 2105 2051 2005 1986 1643 1739 1620 1531 1342 1167 1199 1196 1048 914 818 835 733 641 601 475 516 455 380 376 277 291 268 255 201 164 161 115 122 112 87 77 65 82 61 53 40 36 39 33 23 15 18 14 11 17 11 7 12 9 4 4 4 4 3 2 4 1 1 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15717 count: 6873 average: 3454.33 | standard deviation: 2978.21 | 539 235 249 265 277 227 205 196 187 134 125 122 86 86 94 72 76 62 79 71 73 57 66 59 62 48 69 62 75 51 69 51 54 56 64 76 72 60 84 80 62 81 83 72 66 68 78 71 87 102 92 76 65 81 74 72 75 53 69 57 67 49 73 48 44 37 42 29 29 29 36 32 21 16 18 14 13 14 7 7 9 8 6 6 7 8 6 5 7 2 1 3 2 0 2 1 3 0 0 1 2 1 1 0 2 0 0 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -124,242 +124,242 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 111
+user_time: 107
 system_time: 0
-page_reclaims: 10681
+page_reclaims: 10917
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 200
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 1842177 14737416
-total_msg_count_Response_Data: 1842009 132624648
-total_msg_count_Response_Control: 12834456 102675648
-total_msg_count_Writeback_Data: 638355 45961560
-total_msg_count_Writeback_Control: 4574040 36592320
-total_msg_count_Broadcast_Control: 9210045 73680360
-total_msg_count_Unblock_Control: 1842045 14736360
-total_msgs: 32783127 total_bytes: 421008312
+total_msg_count_Request_Control: 1837086 14696688
+total_msg_count_Response_Data: 1836936 132259392
+total_msg_count_Response_Control: 12798939 102391512
+total_msg_count_Writeback_Data: 636630 45837360
+total_msg_count_Writeback_Control: 4561293 36490344
+total_msg_count_Broadcast_Control: 9184575 73476600
+total_msg_count_Unblock_Control: 1836972 14695776
+total_msgs: 32692431 total_bytes: 419847672
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 3.77789
-  links_utilized_percent_switch_0_link_0: 4.7773 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 2.77847 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 3.77725
+  links_utilized_percent_switch_0_link_0: 4.77637 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.77814 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_0_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Data: 76290 5492880 [ 0 0 0 0 76290 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 531541 4252328 [ 0 0 0 0 531541 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 71850 574800 [ 0 0 0 71850 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Broadcast_Control: 537716 4301728 [ 0 0 0 537716 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 76294 610352 [ 0 0 76294 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 2509 180648 [ 0 0 0 0 2509 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 535210 4281680 [ 0 0 0 0 535210 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 26116 1880352 [ 0 0 0 0 0 26116 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 117581 940648 [ 0 0 71850 0 0 45731 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Unblock_Control: 76291 610328 [ 0 0 0 0 0 76291 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 76057 5476104 [ 0 0 0 0 76057 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 529924 4239392 [ 0 0 0 0 529924 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 71629 573032 [ 0 0 0 71629 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 536252 4290016 [ 0 0 0 536252 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 76060 608480 [ 0 0 76060 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 2500 180000 [ 0 0 0 0 2500 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 533753 4270024 [ 0 0 0 0 533753 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 26039 1874808 [ 0 0 0 0 0 26039 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 117218 937744 [ 0 0 71629 0 0 45589 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 76058 608464 [ 0 0 0 0 0 76058 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.7653
-  links_utilized_percent_switch_1_link_0: 4.75571 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 2.77489 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 3.76513
+  links_utilized_percent_switch_1_link_0: 4.75543 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.77484 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_1_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Data: 75768 5455296 [ 0 0 0 0 75768 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 527899 4223192 [ 0 0 0 0 527899 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 71411 571288 [ 0 0 0 71411 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Broadcast_Control: 538238 4305904 [ 0 0 0 538238 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 75771 606168 [ 0 0 75771 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 2543 183096 [ 0 0 0 0 2543 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 535695 4285560 [ 0 0 0 0 535695 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 26086 1878192 [ 0 0 0 0 0 26086 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 116734 933872 [ 0 0 71411 0 0 45323 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Unblock_Control: 75770 606160 [ 0 0 0 0 0 75770 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 75553 5439816 [ 0 0 0 0 75553 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 526391 4211128 [ 0 0 0 0 526391 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 71208 569664 [ 0 0 0 71208 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 536756 4294048 [ 0 0 0 536756 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 75555 604440 [ 0 0 75555 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 2534 182448 [ 0 0 0 0 2534 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 534222 4273776 [ 0 0 0 0 534222 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 26016 1873152 [ 0 0 0 0 0 26016 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 116398 931184 [ 0 0 71208 0 0 45190 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 75555 604440 [ 0 0 0 0 0 75555 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 3.80482
-  links_utilized_percent_switch_2_link_0: 4.80949 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 2.80015 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 3.80471
+  links_utilized_percent_switch_2_link_0: 4.80919 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.80023 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_2_link_0_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 77050 5547600 [ 0 0 0 0 77050 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 536881 4295048 [ 0 0 0 0 536881 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 72745 581960 [ 0 0 0 72745 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Broadcast_Control: 536954 4295632 [ 0 0 0 536954 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 77053 616424 [ 0 0 77053 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 2530 182160 [ 0 0 0 0 2530 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 534427 4275416 [ 0 0 0 0 534427 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 26813 1930536 [ 0 0 0 0 0 26813 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Control: 118676 949408 [ 0 0 72745 0 0 45931 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Unblock_Control: 77051 616408 [ 0 0 0 0 0 77051 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 76831 5531832 [ 0 0 0 0 76831 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 535348 4282784 [ 0 0 0 0 535348 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 535476 4283808 [ 0 0 0 535476 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 76833 614664 [ 0 0 76833 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2524 181728 [ 0 0 0 0 2524 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 532955 4263640 [ 0 0 0 0 532955 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 26745 1925640 [ 0 0 0 0 0 26745 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 118326 946608 [ 0 0 72536 0 0 45790 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 76832 614656 [ 0 0 0 0 0 76832 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 3.79764
-  links_utilized_percent_switch_3_link_0: 4.80131 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 2.79397 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 3.7982
+  links_utilized_percent_switch_3_link_0: 4.80209 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.79431 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_3_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Data: 76848 5533056 [ 0 0 0 0 76848 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 535559 4284472 [ 0 0 0 0 535559 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 72563 580504 [ 0 0 0 72563 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Broadcast_Control: 537150 4297200 [ 0 0 0 537150 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 76853 614824 [ 0 0 76853 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 2432 175104 [ 0 0 0 0 2432 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 534719 4277752 [ 0 0 0 0 534719 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 26687 1921464 [ 0 0 0 0 0 26687 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Control: 118434 947472 [ 0 0 72563 0 0 45871 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Unblock_Control: 76854 614832 [ 0 0 0 0 0 76854 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 76656 5519232 [ 0 0 0 0 76656 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 534204 4273632 [ 0 0 0 0 534204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 72377 579016 [ 0 0 0 72377 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 535646 4285168 [ 0 0 0 535646 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 76659 613272 [ 0 0 76659 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 2425 174600 [ 0 0 0 0 2425 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 533222 4265776 [ 0 0 0 0 533222 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 26624 1916928 [ 0 0 0 0 0 26624 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Control: 118125 945000 [ 0 0 72377 0 0 45748 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 76662 613296 [ 0 0 0 0 0 76662 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 3.80564
-  links_utilized_percent_switch_4_link_0: 4.81386 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 2.79743 bw: 16000 base_latency: 1
+links_utilized_percent_switch_4: 3.80549
+  links_utilized_percent_switch_4_link_0: 4.81362 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.79737 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_4_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Data: 77157 5555304 [ 0 0 0 0 77157 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Control: 537662 4301296 [ 0 0 0 0 537662 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 72784 582272 [ 0 0 0 72784 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Broadcast_Control: 536846 4294768 [ 0 0 0 536846 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 77161 617288 [ 0 0 77161 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 2451 176472 [ 0 0 0 0 2451 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 534395 4275160 [ 0 0 0 0 534395 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 26739 1925208 [ 0 0 0 0 0 26739 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Control: 118829 950632 [ 0 0 72784 0 0 46045 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Unblock_Control: 77157 617256 [ 0 0 0 0 0 77157 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 76939 5539608 [ 0 0 0 0 76939 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 536135 4289080 [ 0 0 0 0 536135 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 72578 580624 [ 0 0 0 72578 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 535367 4282936 [ 0 0 0 535367 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 76942 615536 [ 0 0 76942 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 2449 176328 [ 0 0 0 0 2449 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 532918 4263344 [ 0 0 0 0 532918 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 26660 1919520 [ 0 0 0 0 0 26660 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 118496 947968 [ 0 0 72578 0 0 45918 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 76939 615512 [ 0 0 0 0 0 76939 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 3.81066
-  links_utilized_percent_switch_5_link_0: 4.81794 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 2.80338 bw: 16000 base_latency: 1
+links_utilized_percent_switch_5: 3.81067
+  links_utilized_percent_switch_5_link_0: 4.81781 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.80353 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_5_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 538294 4306352 [ 0 0 0 0 538294 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 72924 583392 [ 0 0 0 72924 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Broadcast_Control: 536745 4293960 [ 0 0 0 536745 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 77259 618072 [ 0 0 77259 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 2540 182880 [ 0 0 0 0 2540 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 534211 4273688 [ 0 0 0 0 534211 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 26887 1935864 [ 0 0 0 0 0 26887 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Control: 118960 951680 [ 0 0 72924 0 0 46036 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Unblock_Control: 77257 618056 [ 0 0 0 0 0 77257 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 77040 5546880 [ 0 0 0 0 77040 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 536788 4294304 [ 0 0 0 0 536788 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 72718 581744 [ 0 0 0 72718 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 535263 4282104 [ 0 0 0 535263 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 77043 616344 [ 0 0 77043 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 2536 182592 [ 0 0 0 0 2536 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 532733 4261864 [ 0 0 0 0 532733 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 26819 1930968 [ 0 0 0 0 0 26819 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Control: 118616 948928 [ 0 0 72718 0 0 45898 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 77041 616328 [ 0 0 0 0 0 77041 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 3.79483
-  links_utilized_percent_switch_6_link_0: 4.79668 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 2.79299 bw: 16000 base_latency: 1
+links_utilized_percent_switch_6: 3.79476
+  links_utilized_percent_switch_6_link_0: 4.79677 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.79275 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_6_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Data: 76749 5525928 [ 0 0 0 0 76749 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 534680 4277440 [ 0 0 0 0 534680 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 72458 579664 [ 0 0 0 72458 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Broadcast_Control: 537253 4298024 [ 0 0 0 537253 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 76752 614016 [ 0 0 76752 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 2416 173952 [ 0 0 0 0 2416 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 534839 4278712 [ 0 0 0 0 534839 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 26694 1921968 [ 0 0 0 0 0 26694 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Control: 118222 945776 [ 0 0 72458 0 0 45764 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Unblock_Control: 76750 614000 [ 0 0 0 0 0 76750 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 76540 5510880 [ 0 0 0 0 76540 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 533216 4265728 [ 0 0 0 0 533216 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 72261 578088 [ 0 0 0 72261 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 535763 4286104 [ 0 0 0 535763 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 76544 612352 [ 0 0 76544 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 2407 173304 [ 0 0 0 0 2407 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 533360 4266880 [ 0 0 0 0 533360 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 26611 1915992 [ 0 0 0 0 0 26611 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Control: 117909 943272 [ 0 0 72261 0 0 45648 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 76541 612328 [ 0 0 0 0 0 76541 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 3.79875
-  links_utilized_percent_switch_7_link_0: 4.80193 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 2.79556 bw: 16000 base_latency: 1
+links_utilized_percent_switch_7: 3.79942
+  links_utilized_percent_switch_7_link_0: 4.80286 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.79599 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_7_link_0_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Data: 76885 5535720 [ 0 0 0 0 76885 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 535636 4285088 [ 0 0 0 0 535636 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 72424 579392 [ 0 0 0 72424 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Broadcast_Control: 537119 4296952 [ 0 0 0 537119 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 76888 615104 [ 0 0 76888 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 2462 177264 [ 0 0 0 0 2462 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 534656 4277248 [ 0 0 0 0 534656 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 26763 1926936 [ 0 0 0 0 0 26763 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Control: 118085 944680 [ 0 0 72424 0 0 45661 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Unblock_Control: 76885 615080 [ 0 0 0 0 0 76885 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 76696 5522112 [ 0 0 0 0 76696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 534307 4274456 [ 0 0 0 0 534307 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 72244 577952 [ 0 0 0 72244 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 535612 4284896 [ 0 0 0 535612 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 76698 613584 [ 0 0 76698 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 2461 177192 [ 0 0 0 0 2461 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 533150 4265200 [ 0 0 0 0 533150 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 26696 1922112 [ 0 0 0 0 0 26696 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 117792 942336 [ 0 0 72244 0 0 45548 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 76696 613568 [ 0 0 0 0 0 76696 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 13.8909
-  links_utilized_percent_switch_8_link_0: 10.6869 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 17.095 bw: 16000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 614031 4912248 [ 0 0 614031 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 212785 15320520 [ 0 0 0 0 0 212785 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Control: 945521 7564168 [ 0 0 579159 0 0 366362 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Unblock_Control: 614015 4912120 [ 0 0 0 0 0 614015 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 13.891
+  links_utilized_percent_switch_8_link_0: 10.6871 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 17.0948 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 612334 4898672 [ 0 0 612334 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 212210 15279120 [ 0 0 0 0 0 212210 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Control: 942880 7543040 [ 0 0 577551 0 0 365329 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Unblock_Control: 612324 4898592 [ 0 0 0 0 0 612324 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_8_link_1_Request_Control: 28 224 [ 0 0 0 28 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 594120 42776640 [ 0 0 0 0 594120 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 579159 4633272 [ 0 0 0 579159 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Broadcast_Control: 614003 4912024 [ 0 0 0 614003 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 592476 42658272 [ 0 0 0 0 592476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 577551 4620408 [ 0 0 0 577551 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Broadcast_Control: 612305 4898440 [ 0 0 0 612305 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 9
 switch_9_outlinks: 9
-links_utilized_percent_switch_9: 5.45123
-  links_utilized_percent_switch_9_link_0: 4.7773 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 4.75571 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_2: 4.80949 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_3: 4.80131 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_4: 4.81386 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_5: 4.81795 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_6: 4.79668 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_7: 4.80193 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_9_link_8: 10.6869 bw: 16000 base_latency: 1
+links_utilized_percent_switch_9: 5.45125
+  links_utilized_percent_switch_9_link_0: 4.77637 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 4.75543 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 4.80919 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 4.80209 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 4.81362 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 4.81782 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 4.79677 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 4.80286 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 10.6871 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_9_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Data: 76290 5492880 [ 0 0 0 0 76290 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Control: 531541 4252328 [ 0 0 0 0 531541 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 71850 574800 [ 0 0 0 71850 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Broadcast_Control: 537716 4301728 [ 0 0 0 537716 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Data: 76057 5476104 [ 0 0 0 0 76057 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 529924 4239392 [ 0 0 0 0 529924 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 71629 573032 [ 0 0 0 71629 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Broadcast_Control: 536252 4290016 [ 0 0 0 536252 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_1_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 75768 5455296 [ 0 0 0 0 75768 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Control: 527899 4223192 [ 0 0 0 0 527899 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 71411 571288 [ 0 0 0 71411 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Broadcast_Control: 538238 4305904 [ 0 0 0 538238 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 75553 5439816 [ 0 0 0 0 75553 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 526391 4211128 [ 0 0 0 0 526391 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 71208 569664 [ 0 0 0 71208 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Broadcast_Control: 536756 4294048 [ 0 0 0 536756 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_2_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Data: 77050 5547600 [ 0 0 0 0 77050 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Control: 536881 4295048 [ 0 0 0 0 536881 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Writeback_Control: 72745 581960 [ 0 0 0 72745 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Broadcast_Control: 536954 4295632 [ 0 0 0 536954 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 76831 5531832 [ 0 0 0 0 76831 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Control: 535348 4282784 [ 0 0 0 0 535348 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Broadcast_Control: 535476 4283808 [ 0 0 0 535476 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_3_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Data: 76848 5533056 [ 0 0 0 0 76848 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Control: 535559 4284472 [ 0 0 0 0 535559 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Writeback_Control: 72563 580504 [ 0 0 0 72563 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Broadcast_Control: 537150 4297200 [ 0 0 0 537150 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 76656 5519232 [ 0 0 0 0 76656 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Control: 534204 4273632 [ 0 0 0 0 534204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 72377 579016 [ 0 0 0 72377 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Broadcast_Control: 535646 4285168 [ 0 0 0 535646 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_4_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Data: 77157 5555304 [ 0 0 0 0 77157 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Control: 537662 4301296 [ 0 0 0 0 537662 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Writeback_Control: 72784 582272 [ 0 0 0 72784 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Broadcast_Control: 536846 4294768 [ 0 0 0 536846 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 76939 5539608 [ 0 0 0 0 76939 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Control: 536135 4289080 [ 0 0 0 0 536135 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 72578 580624 [ 0 0 0 72578 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Broadcast_Control: 535367 4282936 [ 0 0 0 535367 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_5_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Control: 538294 4306352 [ 0 0 0 0 538294 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Writeback_Control: 72924 583392 [ 0 0 0 72924 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Broadcast_Control: 536745 4293960 [ 0 0 0 536745 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 77040 5546880 [ 0 0 0 0 77040 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Control: 536788 4294304 [ 0 0 0 0 536788 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 72718 581744 [ 0 0 0 72718 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Broadcast_Control: 535263 4282104 [ 0 0 0 535263 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_6_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Data: 76749 5525928 [ 0 0 0 0 76749 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Control: 534680 4277440 [ 0 0 0 0 534680 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Writeback_Control: 72458 579664 [ 0 0 0 72458 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Broadcast_Control: 537253 4298024 [ 0 0 0 537253 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 76540 5510880 [ 0 0 0 0 76540 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Control: 533216 4265728 [ 0 0 0 0 533216 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 72261 578088 [ 0 0 0 72261 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Broadcast_Control: 535763 4286104 [ 0 0 0 535763 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_9_link_7_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Data: 76885 5535720 [ 0 0 0 0 76885 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Control: 535636 4285088 [ 0 0 0 0 535636 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Writeback_Control: 72424 579392 [ 0 0 0 72424 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Broadcast_Control: 537119 4296952 [ 0 0 0 537119 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Request_Control: 614031 4912248 [ 0 0 614031 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Data: 212785 15320520 [ 0 0 0 0 0 212785 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Control: 945521 7564168 [ 0 0 579159 0 0 366362 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Unblock_Control: 614015 4912120 [ 0 0 0 0 0 614015 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 76696 5522112 [ 0 0 0 0 76696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Control: 534307 4274456 [ 0 0 0 0 534307 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 72244 577952 [ 0 0 0 72244 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Broadcast_Control: 535612 4284896 [ 0 0 0 535612 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Request_Control: 612334 4898672 [ 0 0 612334 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Data: 212210 15279120 [ 0 0 0 0 0 212210 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Control: 942880 7543040 [ 0 0 577551 0 0 365329 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Unblock_Control: 612324 4898592 [ 0 0 0 0 0 612324 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -370,67 +370,67 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 76356
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76356
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 76122
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76122
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.3727%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.6273%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.3648%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.6352%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76356    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76122    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 76356
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76356
+  system.l1_cntrl0.L2cacheMemory_total_misses: 76122
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76122
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   65.3727%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   34.6273%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   65.3648%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   34.6352%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   76356    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   76122    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [50226 50162 49933 49936 49950 49466 49962 49958 ] 399593
+Load [50083 50012 49809 49808 49791 49324 49816 49826 ] 398469
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [27060 27258 26937 27082 26459 26444 27221 27049 ] 215510
-L2_Replacement [77144 77245 76740 76875 76282 75759 77037 76837 ] 613919
-L1_to_L2 [841564 837430 840967 837780 832569 831317 842943 837009 ] 6701579
-Trigger_L2_to_L1D [75 87 65 65 62 86 68 85 ] 593
+Store [26984 27191 26853 27019 26384 26370 27145 26987 ] 214933
+L2_Replacement [76925 77030 76532 76686 76048 75543 76816 76643 ] 612223
+L1_to_L2 [839245 835114 838734 835659 830150 829067 840556 834819 ] 6683344
+Trigger_L2_to_L1D [75 86 65 64 62 86 67 85 ] 590
 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-Complete_L2_to_L1 [75 87 65 65 62 86 68 85 ] 593
-Other_GETX [188117 187930 188238 188102 188720 188737 187986 188143 ] 1505973
-Other_GETS [348729 348815 349015 349017 348996 349501 348968 349007 ] 2792048
+Complete_L2_to_L1 [75 86 65 64 62 86 67 85 ] 590
+Other_GETX [187618 187421 187747 187591 188220 188236 187485 187630 ] 1501948
+Other_GETS [347749 347842 348016 348021 348032 348520 347991 348016 ] 2784187
 Merged_GETS [2 8 4 1 3 2 5 3 ] 28
 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 Invalidate [0 0 0 0 0 0 0 0 ] 0
-Ack [537613 538244 534612 535568 531478 527832 536832 535493 ] 4277672
-Shared_Ack [49 50 68 68 63 67 49 66 ] 480
-Data [2928 2931 2904 2930 2916 2838 2791 2896 ] 23134
-Shared_Data [1033 1064 1027 1109 1056 1055 1027 1034 ] 8405
-Exclusive_Data [73196 73261 72818 72846 72318 71875 73232 72918 ] 582464
-Writeback_Ack [72784 72924 72458 72424 71850 71411 72745 72563 ] 579159
+Ack [536086 536738 533148 534239 529862 526324 535299 534139 ] 4265835
+Shared_Ack [49 50 68 68 62 67 49 65 ] 478
+Data [2914 2924 2897 2923 2909 2833 2780 2891 ] 23071
+Shared_Data [1030 1060 1025 1106 1054 1053 1025 1032 ] 8385
+Exclusive_Data [72995 73056 72618 72667 72094 71667 73026 72733 ] 580856
+Writeback_Ack [72578 72718 72261 72244 71629 71208 72536 72377 ] 577551
 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
-All_acks [1074 1108 1087 1167 1109 1111 1066 1090 ] 8812
-All_acks_no_sharers [76083 76148 75663 75718 75181 74657 75984 75759 ] 605193
+All_acks [1071 1104 1085 1164 1106 1109 1064 1088 ] 8791
+All_acks_no_sharers [75868 75937 75456 75532 74951 74444 75767 75569 ] 603524
 Flush_line [0 0 0 0 0 0 0 0 ] 0
 Block_Ack [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
-I  Load [50137 50050 49851 49850 49875 49369 49898 49855 ] 398885
+I  Load [49994 49900 49727 49723 49716 49227 49752 49723 ] 397762
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [27017 27205 26899 27035 26418 26400 27149 26992 ] 215115
-I  L2_Replacement [1480 1454 1402 1469 1495 1454 1505 1429 ] 11688
-I  L1_to_L2 [324 304 306 328 333 308 317 322 ] 2542
+I  Store [26941 27139 26815 26972 26343 26326 27075 26930 ] 214541
+I  L2_Replacement [1480 1453 1399 1468 1490 1446 1500 1426 ] 11662
+I  L1_to_L2 [324 304 306 328 332 308 317 321 ] 2540
 I  Trigger_L2_to_L1D [3 1 1 1 1 1 3 4 ] 15
 I  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-I  Other_GETX [187219 187022 187382 187188 187800 187877 187064 187266 ] 1498818
-I  Other_GETS [347074 347104 347370 347357 347306 347716 347261 347378 ] 2778566
+I  Other_GETX [186720 186513 186893 186678 187305 187379 186564 186756 ] 1494808
+I  Other_GETS [346096 346135 346378 346362 346346 346741 346289 346392 ] 2770739
 I  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 I  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Invalidate [0 0 0 0 0 0 0 0 ] 0
@@ -439,12 +439,12 @@ I  Flush_line [0 0 0 0 0 0 0 0 ] 0
 S  Load [0 2 0 0 0 1 0 1 ] 4
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
 S  Store [0 0 0 1 0 0 0 0 ] 1
-S  L2_Replacement [2880 2867 2880 2982 2937 2894 2787 2845 ] 23072
-S  L1_to_L2 [2918 2897 2902 3011 2962 2913 2816 2865 ] 23284
+S  L2_Replacement [2867 2858 2872 2974 2929 2889 2780 2840 ] 23009
+S  L1_to_L2 [2906 2888 2894 3004 2954 2908 2809 2860 ] 23223
 S  Trigger_L2_to_L1D [6 7 1 2 1 2 5 4 ] 28
 S  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
 S  Other_GETX [39 33 28 34 30 24 30 21 ] 239
-S  Other_GETS [57 52 56 63 61 71 65 55 ] 480
+S  Other_GETS [57 52 56 62 61 71 65 54 ] 478
 S  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 S  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Invalidate [0 0 0 0 0 0 0 0 ] 0
@@ -453,12 +453,12 @@ S  Flush_line [0 0 0 0 0 0 0 0 ] 0
 O  Load [0 0 0 1 0 0 0 0 ] 1
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
 O  Store [0 0 0 0 0 0 0 0 ] 0
-O  L2_Replacement [985 1088 1013 1004 1016 1086 1017 993 ] 8202
-O  L1_to_L2 [217 230 240 228 212 238 237 220 ] 1822
+O  L2_Replacement [983 1086 1008 1004 1012 1085 1016 989 ] 8183
+O  L1_to_L2 [216 230 238 228 211 237 236 218 ] 1814
 O  Trigger_L2_to_L1D [1 1 2 1 0 2 0 1 ] 8
 O  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
 O  Other_GETX [9 7 8 5 5 7 6 4 ] 51
-O  Other_GETS [9 12 16 12 12 11 23 13 ] 108
+O  Other_GETS [9 12 15 12 12 11 23 13 ] 107
 O  Merged_GETS [1 2 2 0 2 2 0 1 ] 10
 O  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 O  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
@@ -468,12 +468,12 @@ O  Flush_line [0 0 0 0 0 0 0 0 ] 0
 M  Load [5 8 8 10 6 5 8 9 ] 59
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
 M  Store [1 2 5 2 2 1 5 4 ] 22
-M  L2_Replacement [45635 45519 45374 45234 45296 44789 45455 45429 ] 362731
-M  L1_to_L2 [46902 46843 46611 46507 46580 46124 46732 46661 ] 372960
-M  Trigger_L2_to_L1D [38 50 37 37 44 53 36 52 ] 347
+M  L2_Replacement [45508 45383 45265 45118 45154 44656 45314 45309 ] 361707
+M  L1_to_L2 [46773 46703 46498 46388 46430 45989 46595 46538 ] 371914
+M  Trigger_L2_to_L1D [38 49 37 36 44 53 36 52 ] 345
 M  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-M  Other_GETX [567 512 529 570 567 540 578 537 ] 4400
-M  Other_GETS [993 1090 1020 1008 1020 1093 1018 996 ] 8238
+M  Other_GETX [567 512 528 570 562 538 578 536 ] 4391
+M  Other_GETS [991 1088 1015 1008 1016 1092 1017 992 ] 8219
 M  Merged_GETS [0 0 1 0 0 0 2 0 ] 3
 M  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 M  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
@@ -483,12 +483,12 @@ M  Flush_line [0 0 0 0 0 0 0 0 ] 0
 MM  Load [6 5 1 6 4 0 6 3 ] 31
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MM  Store [1 2 3 3 2 1 2 2 ] 16
-MM  L2_Replacement [26164 26317 26071 26186 25538 25536 26273 26141 ] 208226
-MM  L1_to_L2 [26864 27064 26752 26872 26263 26268 27008 26860 ] 213951
-MM  Trigger_L2_to_L1D [27 28 24 24 16 28 24 24 ] 195
+MM  L2_Replacement [26087 26250 25988 26122 25463 25467 26206 26079 ] 207662
+MM  L1_to_L2 [26787 26996 26667 26807 26189 26193 26932 26797 ] 213368
+MM  Trigger_L2_to_L1D [27 28 24 24 16 28 23 24 ] 194
 MM  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-MM  Other_GETX [279 354 287 298 312 281 304 309 ] 2424
-MM  Other_GETS [589 550 551 563 583 603 591 563 ] 4593
+MM  Other_GETX [279 354 286 297 312 280 303 307 ] 2418
+MM  Other_GETS [589 548 550 563 583 598 587 563 ] 4581
 MM  Merged_GETS [1 6 1 1 1 0 3 2 ] 15
 MM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
@@ -513,31 +513,31 @@ OR  Store [0 1 1 0 0 0 0 1 ] 3
 OR  L1_to_L2 [2 0 10 1 0 0 0 0 ] 13
 OR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
-MR  Load [25 33 30 25 28 33 19 36 ] 229
+MR  Load [25 33 30 24 28 33 19 36 ] 228
 MR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MR  Store [13 17 7 12 16 20 17 16 ] 118
+MR  Store [13 16 7 12 16 20 17 16 ] 117
 MR  L1_to_L2 [45 115 67 80 92 100 100 102 ] 701
 MR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MMR  Load [18 19 13 12 12 23 10 14 ] 121
 MMR  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MMR  Store [9 9 11 12 4 5 14 10 ] 74
-MMR  L1_to_L2 [37 47 30 35 16 52 58 39 ] 314
+MMR  Store [9 9 11 12 4 5 13 10 ] 73
+MMR  L1_to_L2 [37 47 30 35 16 52 56 39 ] 312
 MMR  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
 IM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IM  L1_to_L2 [267178 264984 265366 266693 262467 263874 265817 265929 ] 2122308
+IM  L1_to_L2 [266453 264275 264595 266098 261822 263121 264961 265204 ] 2116529
 IM  Other_GETX [0 1 0 3 2 4 1 1 ] 12
 IM  Other_GETS [1 0 0 4 0 1 1 0 ] 7
 IM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 IM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IM  Ack [185758 186865 184602 185732 181665 181521 186523 185609 ] 1478275
-IM  Data [1034 1091 1023 1019 1005 973 995 1062 ] 8202
-IM  Exclusive_Data [25982 26114 25876 26016 25413 25428 26155 25932 ] 206916
+IM  Ack [185233 186408 184012 185296 181158 181006 186013 185175 ] 1474301
+IM  Data [1029 1089 1021 1016 1004 971 989 1060 ] 8179
+IM  Exclusive_Data [25911 26049 25793 25954 25340 25355 26087 25871 ] 206360
 IM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
@@ -577,53 +577,53 @@ ISM  Store [0 0 0 0 0 0 0 0 ] 0
 ISM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 ISM  L1_to_L2 [0 0 0 0 0 0 1 0 ] 1
 ISM  Ack [6 24 17 40 25 16 21 28 ] 177
-ISM  All_acks_no_sharers [1038 1093 1023 1021 1005 974 998 1063 ] 8215
+ISM  All_acks_no_sharers [1033 1091 1021 1018 1004 972 992 1061 ] 8192
 ISM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 M_W  Load [0 0 0 0 0 0 0 0 ] 0
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 M_W  Store [0 0 0 0 0 0 0 0 ] 0
 M_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_to_L2 [495 483 546 484 441 445 521 480 ] 3895
-M_W  Ack [1722 1778 1846 1696 1767 1619 1591 1608 ] 13627
-M_W  All_acks_no_sharers [47214 47146 46942 46830 46905 46447 47077 46986 ] 375547
+M_W  L1_to_L2 [481 483 546 484 441 445 521 480 ] 3881
+M_W  Ack [1712 1778 1845 1689 1766 1619 1591 1607 ] 13607
+M_W  All_acks_no_sharers [47084 47007 46825 46713 46754 46312 46939 46862 ] 374496
 M_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MM_W  Load [0 0 0 0 0 0 0 0 ] 0
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MM_W  Store [0 0 0 0 0 0 0 0 ] 0
 MM_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MM_W  L1_to_L2 [676 844 599 687 621 569 726 718 ] 5440
-MM_W  Ack [2536 2677 2767 2603 2413 2420 2608 2494 ] 20518
-MM_W  All_acks_no_sharers [25982 26114 25876 26016 25413 25428 26155 25932 ] 206916
+MM_W  L1_to_L2 [676 844 597 676 621 562 720 718 ] 5414
+MM_W  Ack [2530 2673 2765 2593 2405 2418 2604 2494 ] 20482
+MM_W  All_acks_no_sharers [25911 26049 25793 25954 25340 25355 26087 25871 ] 206360
 MM_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
 IS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IS  L1_to_L2 [494798 492535 496530 491719 491353 489381 497477 491607 ] 3945400
+IS  L1_to_L2 [493437 491159 495278 490401 489823 488117 496177 490336 ] 3934728
 IS  Other_GETX [4 0 4 4 3 2 2 0 ] 19
 IS  Other_GETS [3 1 1 5 8 2 5 0 ] 25
 IS  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 IS  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IS  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IS  Ack [344545 343618 342316 342229 342600 339194 343073 342768 ] 2740343
-IS  Shared_Ack [45 47 66 60 60 63 46 59 ] 446
-IS  Data [1890 1838 1881 1909 1911 1864 1793 1833 ] 14919
-IS  Shared_Data [1033 1064 1027 1109 1056 1055 1027 1034 ] 8405
-IS  Exclusive_Data [47214 47147 46942 46830 46905 46447 47077 46986 ] 375548
+IS  Ack [343571 342587 341454 341364 341509 338211 342059 341851 ] 2732606
+IS  Shared_Ack [45 47 66 60 59 63 46 59 ] 445
+IS  Data [1881 1833 1876 1905 1905 1861 1788 1830 ] 14879
+IS  Shared_Data [1030 1060 1025 1106 1054 1053 1025 1032 ] 8385
+IS  Exclusive_Data [47084 47007 46825 46713 46754 46312 46939 46862 ] 374496
 IS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SS  Load [0 0 0 0 0 0 0 0 ] 0
 SS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SS  Store [0 0 0 0 0 0 0 0 ] 0
 SS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-SS  L1_to_L2 [745 788 789 851 1045 751 868 853 ] 6690
-SS  Ack [3018 3262 3057 3254 3008 3055 2995 2972 ] 24621
-SS  Shared_Ack [4 3 2 8 3 4 3 7 ] 34
-SS  All_acks [1074 1108 1087 1167 1109 1111 1066 1090 ] 8812
-SS  All_acks_no_sharers [1849 1794 1821 1851 1858 1808 1754 1777 ] 14512
+SS  L1_to_L2 [745 782 789 848 1035 741 868 853 ] 6661
+SS  Ack [3006 3248 3048 3243 2999 3047 2990 2970 ] 24551
+SS  Shared_Ack [4 3 2 8 3 4 3 6 ] 33
+SS  All_acks [1071 1104 1085 1164 1106 1109 1064 1088 ] 8791
+SS  All_acks_no_sharers [1840 1789 1816 1847 1853 1805 1749 1774 ] 14473
 SS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 OI  Load [0 0 0 0 0 0 0 0 ] 0
@@ -637,7 +637,7 @@ OI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 OI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-OI  Writeback_Ack [988 1094 1014 1009 1022 1090 1021 995 ] 8233
+OI  Writeback_Ack [986 1092 1009 1009 1018 1089 1020 991 ] 8214
 OI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MI  Load [10 11 12 9 7 10 6 12 ] 77
@@ -651,7 +651,7 @@ MI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack [71796 71829 71444 71415 70827 70319 71723 71563 ] 570916
+MI  Writeback_Ack [71592 71625 71252 71235 70610 70117 71515 71381 ] 569327
 MI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 II  Load [0 0 0 0 0 0 0 0 ] 0
@@ -693,15 +693,15 @@ MT  Load [10 17 12 12 13 12 8 17 ] 101
 MT  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MT  Store [5 7 2 7 8 8 10 11 ] 58
 MT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MT  L1_to_L2 [154 168 108 143 148 156 141 241 ] 1259
-MT  Complete_L2_to_L1 [38 50 37 37 44 53 36 52 ] 347
+MT  L1_to_L2 [154 160 108 140 148 156 141 241 ] 1248
+MT  Complete_L2_to_L1 [38 49 37 36 44 53 36 52 ] 345
 
 MMT  Load [9 10 3 6 3 10 2 5 ] 48
 MMT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MMT  Store [4 3 3 4 2 2 9 3 ] 30
+MMT  Store [4 3 3 4 2 2 8 3 ] 29
 MMT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MMT  L1_to_L2 [171 79 60 102 32 107 97 95 ] 743
-MMT  Complete_L2_to_L1 [27 28 24 24 16 28 24 24 ] 195
+MMT  L1_to_L2 [171 79 60 102 32 107 95 95 ] 741
+MMT  Complete_L2_to_L1 [27 28 24 24 16 28 23 24 ] 194
 
 MI_F  Load [0 0 0 0 0 0 0 0 ] 0
 MI_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -799,28 +799,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 75857
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 75857
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 75641
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 75641
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.1594%
-  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.8406%
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.1578%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.8422%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   75857    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   75641    100%
 
 Cache Stats: system.l1_cntrl1.L2cacheMemory
-  system.l1_cntrl1.L2cacheMemory_total_misses: 75857
-  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 75857
+  system.l1_cntrl1.L2cacheMemory_total_misses: 75641
+  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 75641
   system.l1_cntrl1.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.1594%
-  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.8406%
+  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.1578%
+  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.8422%
 
-  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   75857    100%
+  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   75641    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -831,28 +831,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 77121
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 77121
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 76900
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76900
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.7463%
-  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.2537%
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.7425%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.2575%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   77121    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76900    100%
 
 Cache Stats: system.l1_cntrl2.L2cacheMemory
-  system.l1_cntrl2.L2cacheMemory_total_misses: 77121
-  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 77121
+  system.l1_cntrl2.L2cacheMemory_total_misses: 76900
+  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76900
   system.l1_cntrl2.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L2cacheMemory_request_type_LD:   64.7463%
-  system.l1_cntrl2.L2cacheMemory_request_type_ST:   35.2537%
+  system.l1_cntrl2.L2cacheMemory_request_type_LD:   64.7425%
+  system.l1_cntrl2.L2cacheMemory_request_type_ST:   35.2575%
 
-  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   77121    100%
+  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   76900    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -863,28 +863,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 76938
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76938
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 76744
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76744
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.873%
-  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.127%
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.865%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.135%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76938    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76744    100%
 
 Cache Stats: system.l1_cntrl3.L2cacheMemory
-  system.l1_cntrl3.L2cacheMemory_total_misses: 76938
-  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76938
+  system.l1_cntrl3.L2cacheMemory_total_misses: 76744
+  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76744
   system.l1_cntrl3.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.873%
-  system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.127%
+  system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.865%
+  system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.135%
 
-  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   76938    100%
+  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   76744    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -895,28 +895,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 77236
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77236
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 77017
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77017
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.9788%
-  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.0212%
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.9779%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.0221%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   77236    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   77017    100%
 
 Cache Stats: system.l1_cntrl4.L2cacheMemory
-  system.l1_cntrl4.L2cacheMemory_total_misses: 77236
-  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77236
+  system.l1_cntrl4.L2cacheMemory_total_misses: 77017
+  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77017
   system.l1_cntrl4.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L2cacheMemory_request_type_LD:   64.9788%
-  system.l1_cntrl4.L2cacheMemory_request_type_ST:   35.0212%
+  system.l1_cntrl4.L2cacheMemory_request_type_LD:   64.9779%
+  system.l1_cntrl4.L2cacheMemory_request_type_ST:   35.0221%
 
-  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   77236    100%
+  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   77017    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -927,28 +927,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 77346
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77346
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 77129
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77129
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.7829%
-  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.2171%
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.7707%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.2293%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   77346    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   77129    100%
 
 Cache Stats: system.l1_cntrl5.L2cacheMemory
-  system.l1_cntrl5.L2cacheMemory_total_misses: 77346
-  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77346
+  system.l1_cntrl5.L2cacheMemory_total_misses: 77129
+  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77129
   system.l1_cntrl5.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L2cacheMemory_request_type_LD:   64.7829%
-  system.l1_cntrl5.L2cacheMemory_request_type_ST:   35.2171%
+  system.l1_cntrl5.L2cacheMemory_request_type_LD:   64.7707%
+  system.l1_cntrl5.L2cacheMemory_request_type_ST:   35.2293%
 
-  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   77346    100%
+  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   77129    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -959,28 +959,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 76817
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76817
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 76609
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76609
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.9544%
-  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.0456%
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.9689%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.0311%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76817    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76609    100%
 
 Cache Stats: system.l1_cntrl6.L2cacheMemory
-  system.l1_cntrl6.L2cacheMemory_total_misses: 76817
-  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76817
+  system.l1_cntrl6.L2cacheMemory_total_misses: 76609
+  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76609
   system.l1_cntrl6.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L2cacheMemory_request_type_LD:   64.9544%
-  system.l1_cntrl6.L2cacheMemory_request_type_ST:   35.0456%
+  system.l1_cntrl6.L2cacheMemory_request_type_LD:   64.9689%
+  system.l1_cntrl6.L2cacheMemory_request_type_ST:   35.0311%
 
-  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   76817    100%
+  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   76609    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -991,28 +991,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 76953
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76953
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 76762
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76762
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.8331%
-  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.1669%
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.8276%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.1724%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76953    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76762    100%
 
 Cache Stats: system.l1_cntrl7.L2cacheMemory
-  system.l1_cntrl7.L2cacheMemory_total_misses: 76953
-  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76953
+  system.l1_cntrl7.L2cacheMemory_total_misses: 76762
+  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76762
   system.l1_cntrl7.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.8331%
-  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.1669%
+  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.8276%
+  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.1724%
 
-  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   76953    100%
+  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   76762    100%
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -1023,42 +1023,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
 
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 806930
-  memory_reads: 594122
-  memory_writes: 212776
-  memory_refreshes: 39853
-  memory_total_request_delays: 51498750
-  memory_delays_per_request: 63.8206
-  memory_delays_in_input_queue: 643231
-  memory_delays_behind_head_of_bank_queue: 21064894
-  memory_delays_stalled_at_head_of_bank_queue: 29790625
-  memory_stalls_for_bank_busy: 4493474
+  memory_total_requests: 804704
+  memory_reads: 592481
+  memory_writes: 212202
+  memory_refreshes: 39743
+  memory_total_request_delays: 51359262
+  memory_delays_per_request: 63.8238
+  memory_delays_in_input_queue: 641361
+  memory_delays_behind_head_of_bank_queue: 21004692
+  memory_delays_stalled_at_head_of_bank_queue: 29713209
+  memory_stalls_for_bank_busy: 4481481
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 7575671
-  memory_stalls_for_arbitration: 6083551
-  memory_stalls_for_bus: 8248278
+  memory_stalls_for_anti_starvation: 7557465
+  memory_stalls_for_arbitration: 6067058
+  memory_stalls_for_bus: 8226319
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 2039991
-  memory_stalls_for_read_read_turnaround: 1349660
-  accesses_per_bank: 25394  25147  25249  25452  25456  25358  25579  25279  25469  25293  25305  25375  25044  25055  25245  25044  25128  25227  25252  25145  25222  25167  25232  25093  25055  24752  25158  24793  25021  25318  25415  25208  
+  memory_stalls_for_read_write_turnaround: 2034883
+  memory_stalls_for_read_read_turnaround: 1346003
+  accesses_per_bank: 25333  25087  25174  25408  25390  25300  25486  25224  25408  25202  25227  25301  24969  24999  25175  24978  25048  25162  25177  25055  25180  25093  25154  25003  25003  24677  25093  24719  24960  25241  25333  25145  
 
  --- Directory ---
  - Event Counts -
-GETX [218369 ] 218369
-GETS [404869 ] 404869
-PUT [579376 ] 579376
+GETX [217788 ] 217788
+GETS [403728 ] 403728
+PUT [577768 ] 577768
 Unblock [10 ] 10
-UnblockS [23324 ] 23324
-UnblockM [590681 ] 590681
-Writeback_Clean [8134 ] 8134
+UnblockS [23264 ] 23264
+UnblockM [589050 ] 589050
+Writeback_Clean [8115 ] 8115
 Writeback_Dirty [99 ] 99
-Writeback_Exclusive_Clean [358228 ] 358228
-Writeback_Exclusive_Dirty [212686 ] 212686
+Writeback_Exclusive_Clean [357214 ] 357214
+Writeback_Exclusive_Dirty [212111 ] 212111
 Pf_Replacement [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [594120 ] 594120
-Memory_Ack [212774 ] 212774
+Memory_Data [592476 ] 592476
+Memory_Ack [212202 ] 212202
 Ack [0 ] 0
 Shared_Ack [0 ] 0
 Shared_Data [0 ] 0
@@ -1073,16 +1073,16 @@ PUTF [0 ] 0
 
  - Transitions -
 NX  GETX [54 ] 54
-NX  GETS [108 ] 108
-NX  PUT [8243 ] 8243
+NX  GETS [107 ] 107
+NX  PUT [8224 ] 8224
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
 NX  GETF [0 ] 0
 
-NO  GETX [6834 ] 6834
-NO  GETS [12862 ] 12862
-NO  PUT [570916 ] 570916
+NO  GETX [6819 ] 6819
+NO  GETS [12831 ] 12831
+NO  PUT [569327 ] 569327
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
@@ -1096,16 +1096,16 @@ S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
 S  GETF [0 ] 0
 
-O  GETX [8154 ] 8154
-O  GETS [14919 ] 14919
+O  GETX [8131 ] 8131
+O  GETS [14879 ] 14879
 O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  GETF [0 ] 0
 
-E  GETX [200097 ] 200097
-E  GETS [370975 ] 370975
+E  GETX [199560 ] 199560
+E  GETS [369924 ] 369924
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
@@ -1147,8 +1147,8 @@ NO_R  GETF [0 ] 0
 NO_B  GETX [18 ] 18
 NO_B  GETS [28 ] 28
 NO_B  PUT [217 ] 217
-NO_B  UnblockS [8362 ] 8362
-NO_B  UnblockM [590650 ] 590650
+NO_B  UnblockS [8342 ] 8342
+NO_B  UnblockM [589019 ] 589019
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
@@ -1187,22 +1187,22 @@ NO_B_S_W  GETF [0 ] 0
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
-O_B  UnblockS [14919 ] 14919
+O_B  UnblockS [14879 ] 14879
 O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
 O_B  GETF [0 ] 0
 
-NO_B_W  GETX [2005 ] 2005
-NO_B_W  GETS [3743 ] 3743
+NO_B_W  GETX [2001 ] 2001
+NO_B_W  GETS [3732 ] 3732
 NO_B_W  PUT [0 ] 0
 NO_B_W  UnblockS [0 ] 0
 NO_B_W  UnblockM [0 ] 0
 NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
-NO_B_W  Memory_Data [579201 ] 579201
+NO_B_W  Memory_Data [577597 ] 577597
 NO_B_W  GETF [0 ] 0
 
 O_B_W  GETX [51 ] 51
@@ -1212,7 +1212,7 @@ O_B_W  UnblockS [0 ] 0
 O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
-O_B_W  Memory_Data [14919 ] 14919
+O_B_W  Memory_Data [14879 ] 14879
 O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
@@ -1327,10 +1327,10 @@ WB  GETX [94 ] 94
 WB  GETS [184 ] 184
 WB  PUT [0 ] 0
 WB  Unblock [10 ] 10
-WB  Writeback_Clean [8134 ] 8134
+WB  Writeback_Clean [8115 ] 8115
 WB  Writeback_Dirty [99 ] 99
-WB  Writeback_Exclusive_Clean [358228 ] 358228
-WB  Writeback_Exclusive_Dirty [212686 ] 212686
+WB  Writeback_Exclusive_Clean [357214 ] 357214
+WB  Writeback_Exclusive_Dirty [212111 ] 212111
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
@@ -1345,13 +1345,13 @@ WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [99 ] 99
 WB_O_W  GETF [0 ] 0
 
-WB_E_W  GETX [1062 ] 1062
-WB_E_W  GETS [1959 ] 1959
+WB_E_W  GETX [1060 ] 1060
+WB_E_W  GETS [1952 ] 1952
 WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack [212675 ] 212675
+WB_E_W  Memory_Ack [212103 ] 212103
 WB_E_W  GETF [0 ] 0
 
 NO_F  GETX [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index 5f7af8d92..00cab8c91 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -1,74 +1,74 @@
-system.cpu2: completed 10000 read, 5414 write accesses @1885229
-system.cpu1: completed 10000 read, 5302 write accesses @1890168
-system.cpu3: completed 10000 read, 5360 write accesses @1915688
-system.cpu7: completed 10000 read, 5642 write accesses @1921599
-system.cpu4: completed 10000 read, 5405 write accesses @1938259
-system.cpu0: completed 10000 read, 5276 write accesses @1954368
-system.cpu5: completed 10000 read, 5459 write accesses @1966609
-system.cpu6: completed 10000 read, 5462 write accesses @1976068
-system.cpu7: completed 20000 read, 10887 write accesses @3769229
-system.cpu2: completed 20000 read, 10839 write accesses @3812419
-system.cpu3: completed 20000 read, 10626 write accesses @3834729
-system.cpu4: completed 20000 read, 10795 write accesses @3849978
-system.cpu6: completed 20000 read, 10711 write accesses @3859128
-system.cpu1: completed 20000 read, 10709 write accesses @3868509
-system.cpu0: completed 20000 read, 10487 write accesses @3883829
-system.cpu5: completed 20000 read, 10981 write accesses @3886079
-system.cpu7: completed 30000 read, 16345 write accesses @5699399
-system.cpu2: completed 30000 read, 16163 write accesses @5707569
-system.cpu3: completed 30000 read, 16054 write accesses @5753608
-system.cpu4: completed 30000 read, 16228 write accesses @5762628
-system.cpu1: completed 30000 read, 15958 write accesses @5788449
-system.cpu5: completed 30000 read, 16533 write accesses @5821749
-system.cpu0: completed 30000 read, 15924 write accesses @5824589
-system.cpu6: completed 30000 read, 16129 write accesses @5834348
-system.cpu7: completed 40000 read, 21899 write accesses @7654549
-system.cpu4: completed 40000 read, 21830 write accesses @7666399
-system.cpu2: completed 40000 read, 21530 write accesses @7670799
-system.cpu3: completed 40000 read, 21349 write accesses @7687899
-system.cpu5: completed 40000 read, 21853 write accesses @7706209
-system.cpu1: completed 40000 read, 21335 write accesses @7740999
-system.cpu0: completed 40000 read, 21207 write accesses @7785709
-system.cpu6: completed 40000 read, 21495 write accesses @7787590
-system.cpu2: completed 50000 read, 26843 write accesses @9593621
-system.cpu4: completed 50000 read, 27326 write accesses @9612259
-system.cpu7: completed 50000 read, 27316 write accesses @9617878
-system.cpu5: completed 50000 read, 27312 write accesses @9642000
-system.cpu3: completed 50000 read, 26959 write accesses @9653721
-system.cpu6: completed 50000 read, 26913 write accesses @9694819
-system.cpu1: completed 50000 read, 26597 write accesses @9697068
-system.cpu0: completed 50000 read, 26748 write accesses @9738679
-system.cpu2: completed 60000 read, 32089 write accesses @11467409
-system.cpu4: completed 60000 read, 32735 write accesses @11491009
-system.cpu5: completed 60000 read, 32633 write accesses @11520189
-system.cpu7: completed 60000 read, 32794 write accesses @11539719
-system.cpu3: completed 60000 read, 32320 write accesses @11596739
-system.cpu0: completed 60000 read, 32089 write accesses @11619948
-system.cpu6: completed 60000 read, 32335 write accesses @11642479
-system.cpu1: completed 60000 read, 31985 write accesses @11677349
-system.cpu4: completed 70000 read, 38118 write accesses @13391159
-system.cpu2: completed 70000 read, 37499 write accesses @13402439
-system.cpu5: completed 70000 read, 38044 write accesses @13419869
-system.cpu7: completed 70000 read, 38074 write accesses @13454578
-system.cpu3: completed 70000 read, 37729 write accesses @13532920
-system.cpu0: completed 70000 read, 37349 write accesses @13535619
-system.cpu6: completed 70000 read, 37688 write accesses @13582560
-system.cpu1: completed 70000 read, 37275 write accesses @13667028
-system.cpu4: completed 80000 read, 43427 write accesses @15278311
-system.cpu5: completed 80000 read, 43269 write accesses @15290669
-system.cpu2: completed 80000 read, 42945 write accesses @15354249
-system.cpu7: completed 80000 read, 43467 write accesses @15377329
-system.cpu3: completed 80000 read, 42965 write accesses @15400433
-system.cpu0: completed 80000 read, 42539 write accesses @15436171
-system.cpu6: completed 80000 read, 42985 write accesses @15520509
-system.cpu1: completed 80000 read, 42662 write accesses @15613459
-system.cpu4: completed 90000 read, 48791 write accesses @17215361
-system.cpu5: completed 90000 read, 48724 write accesses @17227780
-system.cpu2: completed 90000 read, 48516 write accesses @17311279
-system.cpu7: completed 90000 read, 48844 write accesses @17312899
-system.cpu3: completed 90000 read, 48360 write accesses @17361088
-system.cpu0: completed 90000 read, 47879 write accesses @17373929
-system.cpu6: completed 90000 read, 48388 write accesses @17425899
-system.cpu1: completed 90000 read, 48067 write accesses @17546750
-system.cpu5: completed 100000 read, 53955 write accesses @19129228
+system.cpu2: completed 10000 read, 5409 write accesses @1880159
+system.cpu1: completed 10000 read, 5299 write accesses @1882778
+system.cpu3: completed 10000 read, 5366 write accesses @1911159
+system.cpu7: completed 10000 read, 5649 write accesses @1917229
+system.cpu4: completed 10000 read, 5408 write accesses @1931479
+system.cpu0: completed 10000 read, 5286 write accesses @1950089
+system.cpu5: completed 10000 read, 5459 write accesses @1964580
+system.cpu6: completed 10000 read, 5463 write accesses @1972179
+system.cpu7: completed 20000 read, 10897 write accesses @3761849
+system.cpu2: completed 20000 read, 10831 write accesses @3800179
+system.cpu3: completed 20000 read, 10626 write accesses @3825708
+system.cpu4: completed 20000 read, 10811 write accesses @3842889
+system.cpu6: completed 20000 read, 10715 write accesses @3849899
+system.cpu1: completed 20000 read, 10702 write accesses @3854688
+system.cpu0: completed 20000 read, 10477 write accesses @3872776
+system.cpu5: completed 20000 read, 10977 write accesses @3877309
+system.cpu7: completed 30000 read, 16346 write accesses @5687720
+system.cpu2: completed 30000 read, 16162 write accesses @5688839
+system.cpu3: completed 30000 read, 16041 write accesses @5736199
+system.cpu4: completed 30000 read, 16234 write accesses @5749298
+system.cpu1: completed 30000 read, 15966 write accesses @5776163
+system.cpu5: completed 30000 read, 16541 write accesses @5808819
+system.cpu0: completed 30000 read, 15936 write accesses @5814209
+system.cpu6: completed 30000 read, 16131 write accesses @5822319
+system.cpu7: completed 40000 read, 21881 write accesses @7635659
+system.cpu2: completed 40000 read, 21509 write accesses @7644271
+system.cpu4: completed 40000 read, 21826 write accesses @7644629
+system.cpu3: completed 40000 read, 21340 write accesses @7664288
+system.cpu5: completed 40000 read, 21864 write accesses @7689069
+system.cpu1: completed 40000 read, 21331 write accesses @7720199
+system.cpu6: completed 40000 read, 21482 write accesses @7766439
+system.cpu0: completed 40000 read, 21218 write accesses @7770859
+system.cpu2: completed 50000 read, 26843 write accesses @9567509
+system.cpu4: completed 50000 read, 27341 write accesses @9587739
+system.cpu7: completed 50000 read, 27298 write accesses @9594538
+system.cpu5: completed 50000 read, 27297 write accesses @9615250
+system.cpu3: completed 50000 read, 26951 write accesses @9629869
+system.cpu1: completed 50000 read, 26588 write accesses @9668459
+system.cpu6: completed 50000 read, 26930 write accesses @9674989
+system.cpu0: completed 50000 read, 26761 write accesses @9717328
+system.cpu2: completed 60000 read, 32089 write accesses @11434469
+system.cpu4: completed 60000 read, 32753 write accesses @11460881
+system.cpu5: completed 60000 read, 32638 write accesses @11489388
+system.cpu7: completed 60000 read, 32763 write accesses @11509798
+system.cpu3: completed 60000 read, 32313 write accesses @11569698
+system.cpu0: completed 60000 read, 32096 write accesses @11591548
+system.cpu6: completed 60000 read, 32349 write accesses @11615831
+system.cpu1: completed 60000 read, 31983 write accesses @11646079
+system.cpu2: completed 70000 read, 37474 write accesses @13359218
+system.cpu4: completed 70000 read, 38151 write accesses @13362099
+system.cpu5: completed 70000 read, 38045 write accesses @13387329
+system.cpu7: completed 70000 read, 38043 write accesses @13412879
+system.cpu0: completed 70000 read, 37368 write accesses @13497038
+system.cpu3: completed 70000 read, 37733 write accesses @13497379
+system.cpu6: completed 70000 read, 37699 write accesses @13552039
+system.cpu1: completed 70000 read, 37272 write accesses @13629039
+system.cpu5: completed 80000 read, 43265 write accesses @15246808
+system.cpu4: completed 80000 read, 43470 write accesses @15247621
+system.cpu2: completed 80000 read, 42926 write accesses @15318609
+system.cpu7: completed 80000 read, 43420 write accesses @15337379
+system.cpu3: completed 80000 read, 42961 write accesses @15362279
+system.cpu0: completed 80000 read, 42538 write accesses @15399778
+system.cpu6: completed 80000 read, 42992 write accesses @15485249
+system.cpu1: completed 80000 read, 42648 write accesses @15573879
+system.cpu4: completed 90000 read, 48820 write accesses @17171059
+system.cpu5: completed 90000 read, 48731 write accesses @17183141
+system.cpu7: completed 90000 read, 48795 write accesses @17265336
+system.cpu2: completed 90000 read, 48519 write accesses @17267129
+system.cpu3: completed 90000 read, 48352 write accesses @17313919
+system.cpu0: completed 90000 read, 47888 write accesses @17331279
+system.cpu6: completed 90000 read, 48438 write accesses @17390512
+system.cpu1: completed 90000 read, 48044 write accesses @17499359
+system.cpu5: completed 100000 read, 53983 write accesses @19076439
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index 3955733a4..8fe5f45d4 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:42:10
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 19129228 because maximum number of loads reached
+Exiting @ tick 19076439 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index ab6ce02e1..38761c37f 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -2,10 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.019076                       # Number of seconds simulated
 sim_ticks                                    19076439                       # Number of ticks simulated
+final_tick                                   19076439                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 186481                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 376716                       # Number of bytes of host memory used
-host_seconds                                   102.30                       # Real time elapsed on the host
+host_tick_rate                                 177702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347220                       # Number of bytes of host memory used
+host_seconds                                   107.35                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                           99023                       # number of read accesses completed
 system.cpu0.num_writes                          52778                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 086557882..bcc5fa575 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
 mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu0]
 type=MemTest
@@ -225,6 +228,7 @@ version=0
 [system.l1_cntrl0.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -263,6 +267,7 @@ version=1
 [system.l1_cntrl1.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -301,6 +306,7 @@ version=2
 [system.l1_cntrl2.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -339,6 +345,7 @@ version=3
 [system.l1_cntrl3.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -377,6 +384,7 @@ version=4
 [system.l1_cntrl4.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -415,6 +423,7 @@ version=5
 [system.l1_cntrl5.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -453,6 +462,7 @@ version=6
 [system.l1_cntrl6.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -491,6 +501,7 @@ version=7
 [system.l1_cntrl7.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -519,11 +530,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -761,8 +772,14 @@ hot_lines=false
 num_of_sequencers=8
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index 680cc337d..d3193509d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jun/30/2011 15:06:19
+Real time: Jan/23/2012 05:00:08
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 56
-Elapsed_time_in_minutes: 0.933333
-Elapsed_time_in_hours: 0.0155556
-Elapsed_time_in_days: 0.000648148
+Elapsed_time_in_seconds: 40
+Elapsed_time_in_minutes: 0.666667
+Elapsed_time_in_hours: 0.0111111
+Elapsed_time_in_days: 0.000462963
 
-Virtual_time_in_seconds: 56.03
-Virtual_time_in_minutes: 0.933833
-Virtual_time_in_hours:   0.0155639
-Virtual_time_in_days:    0.000648495
+Virtual_time_in_seconds: 40.57
+Virtual_time_in_minutes: 0.676167
+Virtual_time_in_hours:   0.0112694
+Virtual_time_in_days:    0.00046956
 
 Ruby_current_time: 28725020
 Ruby_start_time: 0
 Ruby_cycles: 28725020
 
-mbytes_resident: 38.0742
-mbytes_total: 349.754
-resident_ratio: 0.10886
+mbytes_resident: 41.0898
+mbytes_total: 338.922
+resident_ratio: 0.121237
 
 ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ]
 
@@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367
 Resource Usage
 --------------
 page_size: 4096
-user_time: 55
+user_time: 40
 system_time: 0
-page_reclaims: 10889
-page_faults: 2
+page_reclaims: 10928
+page_faults: 0
 swaps: 0
-block_inputs: 1408
-block_outputs: 0
+block_inputs: 0
+block_outputs: 168
 
 Network Stats
 -------------
@@ -494,4 +494,5 @@ ID_W  PUTX [0 ] 0
 ID_W  PUTX_NotOwner [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
index c0d7847c8..0a1ec6a6d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 30 2011 15:04:55
-gem5 started Jun 30 2011 15:05:23
-gem5 executing on SC2B0622
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:28
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index b7bb25a59..95c30ab1c 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -2,10 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.028725                       # Number of seconds simulated
 sim_ticks                                    28725020                       # Number of ticks simulated
+final_tick                                   28725020                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 514985                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 358152                       # Number of bytes of host memory used
-host_seconds                                    55.78                       # Real time elapsed on the host
+host_tick_rate                                 711274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347060                       # Number of bytes of host memory used
+host_seconds                                    40.39                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          53147                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index fd178ee5f..ac8d82ede 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
 mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[1]
 
 [system.cpu0]
 type=MemTest
@@ -31,6 +34,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[0]
 test=system.cpu0.l1c.cpu_side
@@ -80,6 +84,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[1]
 test=system.cpu1.l1c.cpu_side
@@ -129,6 +134,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[2]
 test=system.cpu2.l1c.cpu_side
@@ -178,6 +184,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[3]
 test=system.cpu3.l1c.cpu_side
@@ -227,6 +234,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[4]
 test=system.cpu4.l1c.cpu_side
@@ -276,6 +284,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[5]
 test=system.cpu5.l1c.cpu_side
@@ -325,6 +334,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[6]
 test=system.cpu6.l1c.cpu_side
@@ -374,6 +384,7 @@ percent_reads=65
 percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
+suppress_func_warnings=false
 trace_addr=0
 functional=system.funcmem.port[7]
 test=system.cpu7.l1c.cpu_side
@@ -460,7 +471,7 @@ clock=2
 header_cycles=1
 use_default_range=false
 width=16
-port=system.l2c.mem_side system.physmem.port[0]
+port=system.l2c.mem_side system.system_port system.physmem.port[0]
 
 [system.physmem]
 type=PhysicalMemory
@@ -470,7 +481,7 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.port[2]
 
 [system.toL2Bus]
 type=Bus
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
index 78382173c..afb940009 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu5: completed 10000 read accesses @25602084
-system.cpu0: completed 10000 read accesses @26185688
-system.cpu4: completed 10000 read accesses @26212882
-system.cpu3: completed 10000 read accesses @26366308
-system.cpu1: completed 10000 read accesses @26447108
-system.cpu7: completed 10000 read accesses @26537664
-system.cpu2: completed 10000 read accesses @26676832
-system.cpu6: completed 10000 read accesses @26707781
-system.cpu3: completed 20000 read accesses @51951998
-system.cpu5: completed 20000 read accesses @52231737
-system.cpu0: completed 20000 read accesses @52523512
-system.cpu4: completed 20000 read accesses @52614186
-system.cpu7: completed 20000 read accesses @52674871
-system.cpu1: completed 20000 read accesses @52986792
-system.cpu2: completed 20000 read accesses @53365626
-system.cpu6: completed 20000 read accesses @53537042
-system.cpu5: completed 30000 read accesses @78528098
-system.cpu3: completed 30000 read accesses @78636475
-system.cpu7: completed 30000 read accesses @79069859
-system.cpu0: completed 30000 read accesses @79082669
-system.cpu4: completed 30000 read accesses @79163244
-system.cpu6: completed 30000 read accesses @79592442
-system.cpu2: completed 30000 read accesses @79845712
-system.cpu1: completed 30000 read accesses @80286691
-system.cpu5: completed 40000 read accesses @103783596
-system.cpu0: completed 40000 read accesses @103983848
-system.cpu7: completed 40000 read accesses @104306510
-system.cpu3: completed 40000 read accesses @104792070
-system.cpu6: completed 40000 read accesses @104882247
-system.cpu4: completed 40000 read accesses @104921736
-system.cpu1: completed 40000 read accesses @105789168
-system.cpu2: completed 40000 read accesses @106255146
-system.cpu5: completed 50000 read accesses @130119835
-system.cpu0: completed 50000 read accesses @130621851
-system.cpu4: completed 50000 read accesses @131102250
-system.cpu7: completed 50000 read accesses @131131435
-system.cpu3: completed 50000 read accesses @131315326
-system.cpu6: completed 50000 read accesses @131463045
-system.cpu2: completed 50000 read accesses @132748289
-system.cpu1: completed 50000 read accesses @133533726
-system.cpu0: completed 60000 read accesses @157291050
-system.cpu5: completed 60000 read accesses @157331674
-system.cpu3: completed 60000 read accesses @157609229
-system.cpu4: completed 60000 read accesses @158092666
-system.cpu7: completed 60000 read accesses @158094050
-system.cpu6: completed 60000 read accesses @158284016
-system.cpu2: completed 60000 read accesses @159310066
-system.cpu1: completed 60000 read accesses @160315811
-system.cpu5: completed 70000 read accesses @184174146
-system.cpu0: completed 70000 read accesses @184194427
-system.cpu3: completed 70000 read accesses @184756116
-system.cpu7: completed 70000 read accesses @185107500
-system.cpu6: completed 70000 read accesses @185115722
-system.cpu4: completed 70000 read accesses @185437602
-system.cpu2: completed 70000 read accesses @186101472
-system.cpu1: completed 70000 read accesses @187053767
-system.cpu0: completed 80000 read accesses @210453706
-system.cpu7: completed 80000 read accesses @210994557
-system.cpu5: completed 80000 read accesses @211075215
-system.cpu3: completed 80000 read accesses @211165517
-system.cpu4: completed 80000 read accesses @211798954
-system.cpu6: completed 80000 read accesses @211876903
-system.cpu2: completed 80000 read accesses @212410812
-system.cpu1: completed 80000 read accesses @214554639
-system.cpu0: completed 90000 read accesses @236986702
-system.cpu5: completed 90000 read accesses @237258796
-system.cpu7: completed 90000 read accesses @237456793
-system.cpu4: completed 90000 read accesses @237741580
-system.cpu3: completed 90000 read accesses @237892702
-system.cpu6: completed 90000 read accesses @238620248
-system.cpu2: completed 90000 read accesses @239205755
-system.cpu1: completed 90000 read accesses @239913307
-system.cpu5: completed 100000 read accesses @263488655
+system.cpu5: completed 10000 read, 5261 write accesses @25602084
+system.cpu0: completed 10000 read, 5478 write accesses @26185688
+system.cpu4: completed 10000 read, 5410 write accesses @26212882
+system.cpu3: completed 10000 read, 5338 write accesses @26366308
+system.cpu1: completed 10000 read, 5460 write accesses @26447108
+system.cpu7: completed 10000 read, 5362 write accesses @26537664
+system.cpu2: completed 10000 read, 5282 write accesses @26676832
+system.cpu6: completed 10000 read, 5370 write accesses @26707781
+system.cpu3: completed 20000 read, 10741 write accesses @51951998
+system.cpu5: completed 20000 read, 10677 write accesses @52231737
+system.cpu0: completed 20000 read, 11006 write accesses @52523512
+system.cpu4: completed 20000 read, 10704 write accesses @52614186
+system.cpu7: completed 20000 read, 10588 write accesses @52674871
+system.cpu1: completed 20000 read, 10959 write accesses @52986792
+system.cpu2: completed 20000 read, 10676 write accesses @53365626
+system.cpu6: completed 20000 read, 10788 write accesses @53537042
+system.cpu5: completed 30000 read, 16233 write accesses @78528098
+system.cpu3: completed 30000 read, 16192 write accesses @78636475
+system.cpu7: completed 30000 read, 15958 write accesses @79069859
+system.cpu0: completed 30000 read, 16488 write accesses @79082669
+system.cpu4: completed 30000 read, 16215 write accesses @79163244
+system.cpu6: completed 30000 read, 16191 write accesses @79592442
+system.cpu2: completed 30000 read, 16073 write accesses @79845712
+system.cpu1: completed 30000 read, 16466 write accesses @80286691
+system.cpu5: completed 40000 read, 21620 write accesses @103783596
+system.cpu0: completed 40000 read, 21781 write accesses @103983848
+system.cpu7: completed 40000 read, 21333 write accesses @104306510
+system.cpu3: completed 40000 read, 21577 write accesses @104792070
+system.cpu6: completed 40000 read, 21636 write accesses @104882247
+system.cpu4: completed 40000 read, 21525 write accesses @104921736
+system.cpu1: completed 40000 read, 21768 write accesses @105789168
+system.cpu2: completed 40000 read, 21470 write accesses @106255146
+system.cpu5: completed 50000 read, 26996 write accesses @130119835
+system.cpu0: completed 50000 read, 27148 write accesses @130621851
+system.cpu4: completed 50000 read, 26714 write accesses @131102250
+system.cpu7: completed 50000 read, 26744 write accesses @131131435
+system.cpu3: completed 50000 read, 26919 write accesses @131315326
+system.cpu6: completed 50000 read, 27071 write accesses @131463045
+system.cpu2: completed 50000 read, 26691 write accesses @132748289
+system.cpu1: completed 50000 read, 27351 write accesses @133533726
+system.cpu0: completed 60000 read, 32524 write accesses @157291050
+system.cpu5: completed 60000 read, 32351 write accesses @157331674
+system.cpu3: completed 60000 read, 32133 write accesses @157609229
+system.cpu4: completed 60000 read, 32278 write accesses @158092666
+system.cpu7: completed 60000 read, 32237 write accesses @158094050
+system.cpu6: completed 60000 read, 32492 write accesses @158284016
+system.cpu2: completed 60000 read, 32099 write accesses @159310066
+system.cpu1: completed 60000 read, 32786 write accesses @160315811
+system.cpu5: completed 70000 read, 37785 write accesses @184174146
+system.cpu0: completed 70000 read, 37907 write accesses @184194427
+system.cpu3: completed 70000 read, 37695 write accesses @184756116
+system.cpu7: completed 70000 read, 37537 write accesses @185107500
+system.cpu6: completed 70000 read, 37865 write accesses @185115722
+system.cpu4: completed 70000 read, 37642 write accesses @185437602
+system.cpu2: completed 70000 read, 37459 write accesses @186101472
+system.cpu1: completed 70000 read, 38271 write accesses @187053767
+system.cpu0: completed 80000 read, 43182 write accesses @210453706
+system.cpu7: completed 80000 read, 43001 write accesses @210994557
+system.cpu5: completed 80000 read, 43199 write accesses @211075215
+system.cpu3: completed 80000 read, 43061 write accesses @211165517
+system.cpu4: completed 80000 read, 43118 write accesses @211798954
+system.cpu6: completed 80000 read, 43219 write accesses @211876903
+system.cpu2: completed 80000 read, 43025 write accesses @212410812
+system.cpu1: completed 80000 read, 43805 write accesses @214554639
+system.cpu0: completed 90000 read, 48653 write accesses @236986702
+system.cpu5: completed 90000 read, 48401 write accesses @237258796
+system.cpu7: completed 90000 read, 48251 write accesses @237456793
+system.cpu4: completed 90000 read, 48341 write accesses @237741580
+system.cpu3: completed 90000 read, 48504 write accesses @237892702
+system.cpu6: completed 90000 read, 48675 write accesses @238620248
+system.cpu2: completed 90000 read, 48457 write accesses @239205755
+system.cpu1: completed 90000 read, 49067 write accesses @239913307
+system.cpu5: completed 100000 read, 53710 write accesses @263488655
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index 7ecac9f9f..c76c33576 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:24
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:28
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 740dd0fe1..82bd7a1b0 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,622 +1,71 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 329728                       # Number of bytes of host memory used
-host_seconds                                   115.41                       # Real time elapsed on the host
-host_tick_rate                                2283081                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000263                       # Number of seconds simulated
 sim_ticks                                   263488655                       # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses                44809                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits                     7530                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency       1299667421                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate            0.831953                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses                  37279                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency   1262244251                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831953                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses             37279                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    894578632                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits                    1059                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency      1001508092                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate           0.956350                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses                 23202                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency    978215253                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956350                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses            23202                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    569723237                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
-system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.demand_accesses                 69070                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency  38047.907822                       # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
-system.cpu0.l1c.demand_hits                      8589                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency        2301175513                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate             0.875648                       # miss rate for demand accesses
-system.cpu0.l1c.demand_misses                   60481                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency   2240459504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate        0.875648                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses              60481                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
-system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
-system.cpu0.l1c.occ_percent::0               0.678383                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::1              -0.477715                       # Average percentage of cache occupancy
-system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits                     8589                       # number of overall hits
-system.cpu0.l1c.overall_miss_latency       2301175513                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate            0.875648                       # miss rate for overall accesses
-system.cpu0.l1c.overall_misses                  60481                       # number of overall misses
-system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency   2240459504                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate       0.875648                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses             60481                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency   1464301869                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.replacements                    27826                       # number of replacements
-system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
-system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse                  102.742005                       # Cycle average of tags in use
-system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
-system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks                      11972                       # number of writebacks
-system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99815                       # number of read accesses completed
-system.cpu0.num_writes                          53929                       # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses                44539                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits                     7429                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency       1301760811                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate            0.833202                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses                  37110                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency   1264508347                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833202                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses             37110                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    877119159                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses               24341                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_hits                    1066                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency      1014297005                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate           0.956206                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses                 23275                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency    990933889                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956206                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses            23275                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    578327433                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
-system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.demand_accesses                 68880                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency  38354.853291                       # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
-system.cpu1.l1c.demand_hits                      8495                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency        2316057816                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate             0.876670                       # miss rate for demand accesses
-system.cpu1.l1c.demand_misses                   60385                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency   2255442236                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate        0.876670                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses              60385                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
-system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
-system.cpu1.l1c.occ_percent::0               0.675110                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_percent::1              -0.493432                       # Average percentage of cache occupancy
-system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits                     8495                       # number of overall hits
-system.cpu1.l1c.overall_miss_latency       2316057816                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate            0.876670                       # miss rate for overall accesses
-system.cpu1.l1c.overall_misses                  60385                       # number of overall misses
-system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency   2255442236                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate       0.876670                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses             60385                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency   1455446592                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.replacements                    27684                       # number of replacements
-system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
-system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse                   93.018974                       # Cycle average of tags in use
-system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
-system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks                      11809                       # number of writebacks
-system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           98493                       # number of read accesses completed
-system.cpu1.num_writes                          53671                       # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses                44720                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_hits                     7576                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency       1302790562                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate            0.830590                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses                  37144                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency   1265501937                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830590                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses             37144                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    900513056                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses               23954                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_hits                    1069                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency       991654869                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate           0.955373                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses                 22885                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency    968684322                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate      0.955373                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses            22885                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    566349170                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
-system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.demand_accesses                 68674                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency  38222.283080                       # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
-system.cpu2.l1c.demand_hits                      8645                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency        2294445431                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate             0.874115                       # miss rate for demand accesses
-system.cpu2.l1c.demand_misses                   60029                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency   2234186259                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate        0.874115                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses              60029                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
-system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
-system.cpu2.l1c.occ_percent::0               0.674668                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::1              -0.509877                       # Average percentage of cache occupancy
-system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits                     8645                       # number of overall hits
-system.cpu2.l1c.overall_miss_latency       2294445431                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate            0.874115                       # miss rate for overall accesses
-system.cpu2.l1c.overall_misses                  60029                       # number of overall misses
-system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency   2234186259                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate       0.874115                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses             60029                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency   1466862226                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.replacements                    27627                       # number of replacements
-system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
-system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse                   84.373112                       # Cycle average of tags in use
-system.cpu2.l1c.total_refs                      11519                       # Total number of references to valid blocks.
-system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks                      11784                       # number of writebacks
-system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99149                       # number of read accesses completed
-system.cpu2.num_writes                          53185                       # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses                44743                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_hits                     7552                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency       1312024933                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate            0.831214                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses                  37191                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency   1274692143                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate       0.831214                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses             37191                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    889431937                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses               24297                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_hits                    1078                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency       995527685                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate           0.955632                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses                 23219                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency    972218785                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate      0.955632                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses            23219                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    569772276                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
-system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.demand_accesses                 69040                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency  38198.189340                       # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
-system.cpu3.l1c.demand_hits                      8630                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency        2307552618                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate             0.875000                       # miss rate for demand accesses
-system.cpu3.l1c.demand_misses                   60410                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency   2246910928                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate        0.875000                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses              60410                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
-system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
-system.cpu3.l1c.occ_percent::0               0.678857                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::1              -0.475386                       # Average percentage of cache occupancy
-system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits                     8630                       # number of overall hits
-system.cpu3.l1c.overall_miss_latency       2307552618                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate            0.875000                       # miss rate for overall accesses
-system.cpu3.l1c.overall_misses                  60410                       # number of overall misses
-system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency   2246910928                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate       0.875000                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses             60410                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency   1459204213                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.replacements                    27837                       # number of replacements
-system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
-system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse                  104.177298                       # Cycle average of tags in use
-system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
-system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks                      11956                       # number of writebacks
-system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99588                       # number of read accesses completed
-system.cpu3.num_writes                          53645                       # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses                44937                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_hits                     7686                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency       1303112178                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate            0.828961                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses                  37251                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency   1265717116                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate       0.828961                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses             37251                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    898461911                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses               24060                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_hits                    1123                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency       994450363                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate           0.953325                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses                 22937                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency    971425596                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate      0.953325                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses            22937                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    576408625                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
-system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency  38173.099970                       # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
-system.cpu4.l1c.demand_hits                      8809                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency        2297562541                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate             0.872328                       # miss rate for demand accesses
-system.cpu4.l1c.demand_misses                   60188                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency   2237142712                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate        0.872328                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
-system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
-system.cpu4.l1c.occ_percent::0               0.678968                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_percent::1              -0.494043                       # Average percentage of cache occupancy
-system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits                     8809                       # number of overall hits
-system.cpu4.l1c.overall_miss_latency       2297562541                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate            0.872328                       # miss rate for overall accesses
-system.cpu4.l1c.overall_misses                  60188                       # number of overall misses
-system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency   2237142712                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate       0.872328                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency   1474870536                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.replacements                    27683                       # number of replacements
-system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
-system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse                   94.681644                       # Cycle average of tags in use
-system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
-system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks                      11763                       # number of writebacks
-system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99725                       # number of read accesses completed
-system.cpu4.num_writes                          53533                       # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses                44941                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_hits                     7592                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency       1291933371                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate            0.831067                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses                  37349                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency   1254436910                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831067                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses             37349                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    902856034                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses               24139                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_hits                    1126                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency       998304045                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate           0.953353                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses                 23013                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency    975203983                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate      0.953353                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses            23013                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    567587171                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
-system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.demand_accesses                 69080                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency  37941.708625                       # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
-system.cpu5.l1c.demand_hits                      8718                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency        2290237416                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate             0.873798                       # miss rate for demand accesses
-system.cpu5.l1c.demand_misses                   60362                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency   2229640893                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate        0.873798                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses              60362                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
-system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
-system.cpu5.l1c.occ_percent::0               0.677357                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_percent::1              -0.494726                       # Average percentage of cache occupancy
-system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits                     8718                       # number of overall hits
-system.cpu5.l1c.overall_miss_latency       2290237416                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate            0.873798                       # miss rate for overall accesses
-system.cpu5.l1c.overall_misses                  60362                       # number of overall misses
-system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency   2229640893                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate       0.873798                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses             60362                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency   1470443205                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.replacements                    27832                       # number of replacements
-system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
-system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse                   93.507234                       # Cycle average of tags in use
-system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
-system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks                      11908                       # number of writebacks
-system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                          100000                       # number of read accesses completed
-system.cpu5.num_writes                          53710                       # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses                44652                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_hits                     7543                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency       1299799162                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate            0.831071                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses                  37109                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency   1262548698                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate       0.831071                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses             37109                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    877981455                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_hits                    1119                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency      1015775810                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate           0.953877                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses                 23142                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency    992541214                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate      0.953877                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses            23142                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    574689009                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
-system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.demand_accesses                 68913                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency  38432.141740                       # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
-system.cpu6.l1c.demand_hits                      8662                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency        2315574972                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate             0.874305                       # miss rate for demand accesses
-system.cpu6.l1c.demand_misses                   60251                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency   2255089912                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate        0.874305                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses              60251                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
-system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
-system.cpu6.l1c.occ_percent::0               0.678299                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_percent::1              -0.502932                       # Average percentage of cache occupancy
-system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits                     8662                       # number of overall hits
-system.cpu6.l1c.overall_miss_latency       2315574972                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate            0.874305                       # miss rate for overall accesses
-system.cpu6.l1c.overall_misses                  60251                       # number of overall misses
-system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency   2255089912                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate       0.874305                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses             60251                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency   1452670464                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.replacements                    27861                       # number of replacements
-system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
-system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse                   89.788098                       # Cycle average of tags in use
-system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
-system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks                      11849                       # number of writebacks
-system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99389                       # number of read accesses completed
-system.cpu6.num_writes                          53686                       # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses                44748                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_hits                     7593                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency       1287127315                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate            0.830316                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses                  37155                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency   1249829653                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate       0.830316                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses             37155                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    901961636                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses               24232                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_hits                    1111                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency      1006139538                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate           0.954152                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses                 23121                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency    982928032                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate      0.954152                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses            23121                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    558194703                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
-system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.demand_accesses                 68980                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency  38046.102147                       # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
-system.cpu7.l1c.demand_hits                      8704                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency        2293266853                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate             0.873818                       # miss rate for demand accesses
-system.cpu7.l1c.demand_misses                   60276                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency   2232757685                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate        0.873818                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses              60276                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
-system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
-system.cpu7.l1c.occ_percent::0               0.675965                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::1              -0.511413                       # Average percentage of cache occupancy
-system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits                     8704                       # number of overall hits
-system.cpu7.l1c.overall_miss_latency       2293266853                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate            0.873818                       # miss rate for overall accesses
-system.cpu7.l1c.overall_misses                  60276                       # number of overall misses
-system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency   2232757685                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate       0.873818                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses             60276                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency   1460156339                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.replacements                    27727                       # number of replacements
-system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
-system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse                   84.250612                       # Cycle average of tags in use
-system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
-system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks                      11797                       # number of writebacks
-system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99694                       # number of read accesses completed
-system.cpu7.num_writes                          53501                       # number of write accesses completed
-system.l2c.ReadExReq_accesses::0                 8368                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                 8627                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                 8367                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3                 8303                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::4                 8426                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::5                 8436                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::6                 8682                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::7                 8556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            67765                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 403825.305651                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 385121.964187                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 409218.508599                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 403898.224630                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::4 399497.833184                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::5 406171.848193                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::6 385653.166897                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::7 396382.840333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344                       # average ReadExReq mshr miss latency
+final_tick                                  263488655                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_tick_rate                                1768401                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335780                       # Number of bytes of host memory used
+host_seconds                                   149.00                       # Real time elapsed on the host
+system.physmem.bytes_read                     4057580                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  2644316                       # Number of bytes written to this memory
+system.physmem.num_reads                       141878                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       83744                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    15399448602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                   10035786930                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   25435235532                       # Total bandwidth to/from this memory (bytes/s)
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.l2c.replacements                         76856                       # number of replacements
+system.l2c.tagsinuse                       657.714518                       # Cycle average of tags in use
+system.l2c.total_refs                          139150                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                    24.461210                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                    24.025606                       # Average occupied blocks per context
+system.l2c.occ_blocks::5                    23.167376                       # Average occupied blocks per context
+system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
+system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
+system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.023513                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.023339                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.023014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.023888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.023463                       # Average percentage of cache occupancy
+system.l2c.occ_percent::5                    0.022624                       # Average percentage of cache occupancy
+system.l2c.occ_percent::6                    0.022944                       # Average percentage of cache occupancy
+system.l2c.occ_percent::7                    0.022464                       # Average percentage of cache occupancy
+system.l2c.occ_percent::8                    0.457051                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                      10466                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                      10370                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                      10579                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                      10469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::4                      10390                       # number of ReadReq hits
+system.l2c.ReadReq_hits::5                      10384                       # number of ReadReq hits
+system.l2c.ReadReq_hits::6                      10590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::7                      10463                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                    94038                       # number of Writeback hits
+system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     457                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     419                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::2                     446                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::3                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::4                     430                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::5                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::6                     415                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::7                     411                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::0                     2829                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::1                     2819                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::2                     2901                       # number of ReadExReq hits
@@ -626,16 +75,42 @@ system.l2c.ReadExReq_hits::5                     2929                       # nu
 system.l2c.ReadExReq_hits::6                     2882                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::7                     2913                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total                22865                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          2236788368                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.661926                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.673235                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2            0.653281                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3            0.666988                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::4            0.664491                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::5            0.652798                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::6            0.668049                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::7            0.659537                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        5.300305                       # miss rate for ReadExReq accesses
+system.l2c.demand_hits::0                       13295                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                       13189                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                       13480                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                       13234                       # number of demand (read+write) hits
+system.l2c.demand_hits::4                       13217                       # number of demand (read+write) hits
+system.l2c.demand_hits::5                       13313                       # number of demand (read+write) hits
+system.l2c.demand_hits::6                       13472                       # number of demand (read+write) hits
+system.l2c.demand_hits::7                       13376                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                      13295                       # number of overall hits
+system.l2c.overall_hits::1                      13189                       # number of overall hits
+system.l2c.overall_hits::2                      13480                       # number of overall hits
+system.l2c.overall_hits::3                      13234                       # number of overall hits
+system.l2c.overall_hits::4                      13217                       # number of overall hits
+system.l2c.overall_hits::5                      13313                       # number of overall hits
+system.l2c.overall_hits::6                      13472                       # number of overall hits
+system.l2c.overall_hits::7                      13376                       # number of overall hits
+system.l2c.overall_hits::total                 106576                       # number of overall hits
+system.l2c.ReadReq_misses::0                     5163                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     5186                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                     5173                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                     5223                       # number of ReadReq misses
+system.l2c.ReadReq_misses::4                     5193                       # number of ReadReq misses
+system.l2c.ReadReq_misses::5                     5114                       # number of ReadReq misses
+system.l2c.ReadReq_misses::6                     5145                       # number of ReadReq misses
+system.l2c.ReadReq_misses::7                     4996                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  1644                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                  1598                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                  1617                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                  1610                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::4                  1586                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::5                  1626                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::6                  1624                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::7                  1582                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::0                   5539                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::1                   5808                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::2                   5466                       # number of ReadExReq misses
@@ -645,18 +120,29 @@ system.l2c.ReadExReq_misses::5                   5507                       # nu
 system.l2c.ReadExReq_misses::6                   5800                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::7                   5643                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total              44900                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits                    507                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency     1775748338                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       5.305091                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       5.145821                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2       5.305725                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3       5.346622                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::4       5.268573                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::5       5.262328                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::6       5.113223                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::7       5.188523                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total    41.935906                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses                44393                       # number of ReadExReq MSHR misses
+system.l2c.demand_misses::0                     10702                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     10994                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                     10761                       # number of demand (read+write) misses
+system.l2c.demand_misses::4                     10792                       # number of demand (read+write) misses
+system.l2c.demand_misses::5                     10621                       # number of demand (read+write) misses
+system.l2c.demand_misses::6                     10945                       # number of demand (read+write) misses
+system.l2c.demand_misses::7                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                    10702                       # number of overall misses
+system.l2c.overall_misses::1                    10994                       # number of overall misses
+system.l2c.overall_misses::2                    10639                       # number of overall misses
+system.l2c.overall_misses::3                    10761                       # number of overall misses
+system.l2c.overall_misses::4                    10792                       # number of overall misses
+system.l2c.overall_misses::5                    10621                       # number of overall misses
+system.l2c.overall_misses::6                    10945                       # number of overall misses
+system.l2c.overall_misses::7                    10639                       # number of overall misses
+system.l2c.overall_misses::total                86093                       # number of overall misses
+system.l2c.ReadReq_miss_latency            2043791615                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency          261408598                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          2236788368                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency             4280579983                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency            4280579983                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::0                  15629                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::1                  15556                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::2                  15752                       # number of ReadReq accesses(hits+misses)
@@ -666,58 +152,8 @@ system.l2c.ReadReq_accesses::5                  15498                       # nu
 system.l2c.ReadReq_accesses::6                  15735                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::7                  15459                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total             124904                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   395853.498935                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   394097.881797                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   395088.268896                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   391306.072181                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::4   393566.650298                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::5   399646.385413                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::6   397238.409135                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::7   409085.591473                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 3175882.758128                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                      10466                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                      10370                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                      10579                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                      10469                       # number of ReadReq hits
-system.l2c.ReadReq_hits::4                      10390                       # number of ReadReq hits
-system.l2c.ReadReq_hits::5                      10384                       # number of ReadReq hits
-system.l2c.ReadReq_hits::6                      10590                       # number of ReadReq hits
-system.l2c.ReadReq_hits::7                      10463                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency            2043791615                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.330347                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.333376                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.328403                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.332845                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::4              0.333248                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::5              0.329978                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::6              0.326978                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::7              0.323177                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          2.638352                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                     5163                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     5186                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                     5173                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                     5223                       # number of ReadReq misses
-system.l2c.ReadReq_misses::4                     5193                       # number of ReadReq misses
-system.l2c.ReadReq_misses::5                     5114                       # number of ReadReq misses
-system.l2c.ReadReq_misses::6                     5145                       # number of ReadReq misses
-system.l2c.ReadReq_misses::7                     4996                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                      961                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency       1609227416                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         2.574189                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.586269                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         2.554088                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3         2.563854                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::4         2.581788                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::5         2.595948                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::6         2.556848                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::7         2.602497                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total    20.615481                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                  40232                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency   3189139994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0                94038                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::0                2101                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::1                2017                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::2                2063                       # number of UpgradeReq accesses(hits+misses)
@@ -727,26 +163,42 @@ system.l2c.UpgradeReq_accesses::5                2089                       # nu
 system.l2c.UpgradeReq_accesses::6                2039                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::7                1993                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           16391                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                     457                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     419                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::2                     446                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::3                     463                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::4                     430                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::5                     463                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::6                     415                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::7                     411                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency          261408598                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_accesses::0                 8368                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                 8627                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                 8367                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                 8303                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::4                 8426                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::5                 8436                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::6                 8682                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::7                 8556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            67765                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                   23997                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                   24183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                   24119                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                   23995                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::4                   24009                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::5                   23934                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::6                   24417                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::7                   24015                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                  23995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::4                  24009                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::5                  23934                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::6                  24417                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::7                  24015                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.330347                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.333376                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.328403                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.332845                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::4              0.333248                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::5              0.329978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::6              0.326978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::7              0.323177                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          2.638352                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::0           0.782485                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::1           0.792266                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::2           0.783810                       # miss rate for UpgradeReq accesses
@@ -756,17 +208,115 @@ system.l2c.UpgradeReq_miss_rate::5           0.778363                       # mi
 system.l2c.UpgradeReq_miss_rate::6           0.796469                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::7           0.793778                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       6.290529                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  1644                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1598                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                  1617                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                  1610                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::4                  1586                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::5                  1626                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::6                  1624                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::7                  1582                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
+system.l2c.ReadExReq_miss_rate::0            0.661926                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.673235                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2            0.653281                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3            0.666988                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::4            0.664491                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::5            0.652798                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::6            0.668049                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::7            0.659537                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        5.300305                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.445972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.454617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.441105                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.448468                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::4               0.449498                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::5               0.443762                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::6               0.448253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::7               0.443015                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           3.574690                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.445972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.454617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.441105                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.448468                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::4              0.449498                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::5              0.443762                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::6              0.448253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::7              0.443015                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          3.574690                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   395853.498935                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   394097.881797                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   395088.268896                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   391306.072181                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::4   393566.650298                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::5   399646.385413                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::6   397238.409135                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::7   409085.591473                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 3175882.758128                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 403825.305651                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 385121.964187                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 409218.508599                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 403898.224630                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::4 399497.833184                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::5 406171.848193                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::6 385653.166897                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::7 396382.840333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    399979.441506                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    389356.010824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    397786.449494                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::4    396643.808655                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::5    403029.844930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::6    391099.130471                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::7    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   399979.441506                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   389356.010824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   397786.449494                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::4   396643.808655                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::5   403029.844930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::6   391099.130471                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::7   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                           40644                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                      961                       # number of ReadReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits                    49                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits                    507                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits                      1468                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                     1468                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                  40232                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses               12838                       # number of UpgradeReq MSHR misses
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+system.l2c.demand_mshr_misses                   84625                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                  84625                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency       1609227416                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency     513507057                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     1775748338                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        3384975754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       3384975754                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency   3189139994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1723903484                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   4913043478                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         2.574189                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         2.586269                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         2.554088                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         2.563854                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::4         2.581788                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::5         2.595948                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::6         2.556848                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::7         2.602497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total    20.615481                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::0      6.110424                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1      6.364898                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2      6.222976                       # mshr miss rate for UpgradeReq accesses
@@ -776,70 +326,15 @@ system.l2c.UpgradeReq_mshr_miss_rate::5      6.145524                       # ms
 system.l2c.UpgradeReq_mshr_miss_rate::6      6.296224                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::7      6.441545                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total    50.142604                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               12838                       # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1723903484                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0                94038                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                    94038                       # number of Writeback hits
-system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                   23997                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                   24183                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                   24119                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                   23995                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::4                   24009                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::5                   23934                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::6                   24417                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::7                   24015                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    399979.441506                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    389356.010824                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    402347.963436                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3    397786.449494                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::4    396643.808655                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::5    403029.844930                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::6    391099.130471                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::7    402347.963436                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3182590.612752                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  39999.713489                       # average overall mshr miss latency
-system.l2c.demand_hits::0                       13295                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                       13189                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                       13480                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                       13234                       # number of demand (read+write) hits
-system.l2c.demand_hits::4                       13217                       # number of demand (read+write) hits
-system.l2c.demand_hits::5                       13313                       # number of demand (read+write) hits
-system.l2c.demand_hits::6                       13472                       # number of demand (read+write) hits
-system.l2c.demand_hits::7                       13376                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency             4280579983                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.445972                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.454617                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.441105                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.448468                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::4               0.449498                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::5               0.443762                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::6               0.448253                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::7               0.443015                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           3.574690                       # miss rate for demand accesses
-system.l2c.demand_misses::0                     10702                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     10994                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                     10639                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                     10761                       # number of demand (read+write) misses
-system.l2c.demand_misses::4                     10792                       # number of demand (read+write) misses
-system.l2c.demand_misses::5                     10621                       # number of demand (read+write) misses
-system.l2c.demand_misses::6                     10945                       # number of demand (read+write) misses
-system.l2c.demand_misses::7                     10639                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                      1468                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency        3384975754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       5.305091                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       5.145821                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2       5.305725                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::3       5.346622                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::4       5.268573                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::5       5.262328                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::6       5.113223                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::7       5.188523                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total    41.935906                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::0          3.526482                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1          3.499359                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2          3.508645                       # mshr miss rate for demand accesses
@@ -849,78 +344,6 @@ system.l2c.demand_mshr_miss_rate::5          3.535765                       # ms
 system.l2c.demand_mshr_miss_rate::6          3.465823                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::7          3.523839                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total     28.111410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                   84625                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                    24.461210                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                    24.025606                       # Average occupied blocks per context
-system.l2c.occ_blocks::5                    23.167376                       # Average occupied blocks per context
-system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
-system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
-system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.023513                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.023339                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.023014                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.023888                       # Average percentage of cache occupancy
-system.l2c.occ_percent::4                    0.023463                       # Average percentage of cache occupancy
-system.l2c.occ_percent::5                    0.022624                       # Average percentage of cache occupancy
-system.l2c.occ_percent::6                    0.022944                       # Average percentage of cache occupancy
-system.l2c.occ_percent::7                    0.022464                       # Average percentage of cache occupancy
-system.l2c.occ_percent::8                    0.457051                       # Average percentage of cache occupancy
-system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                  23995                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::4                  24009                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::5                  23934                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::6                  24417                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::7                  24015                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   399979.441506                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   389356.010824                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   402347.963436                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3   397786.449494                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::4   396643.808655                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::5   403029.844930                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::6   391099.130471                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::7   402347.963436                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3182590.612752                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 39999.713489                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                      13295                       # number of overall hits
-system.l2c.overall_hits::1                      13189                       # number of overall hits
-system.l2c.overall_hits::2                      13480                       # number of overall hits
-system.l2c.overall_hits::3                      13234                       # number of overall hits
-system.l2c.overall_hits::4                      13217                       # number of overall hits
-system.l2c.overall_hits::5                      13313                       # number of overall hits
-system.l2c.overall_hits::6                      13472                       # number of overall hits
-system.l2c.overall_hits::7                      13376                       # number of overall hits
-system.l2c.overall_hits::total                 106576                       # number of overall hits
-system.l2c.overall_miss_latency            4280579983                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.445972                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.454617                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.441105                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.448468                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::4              0.449498                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::5              0.443762                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::6              0.448253                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::7              0.443015                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          3.574690                       # miss rate for overall accesses
-system.l2c.overall_misses::0                    10702                       # number of overall misses
-system.l2c.overall_misses::1                    10994                       # number of overall misses
-system.l2c.overall_misses::2                    10639                       # number of overall misses
-system.l2c.overall_misses::3                    10761                       # number of overall misses
-system.l2c.overall_misses::4                    10792                       # number of overall misses
-system.l2c.overall_misses::5                    10621                       # number of overall misses
-system.l2c.overall_misses::6                    10945                       # number of overall misses
-system.l2c.overall_misses::7                    10639                       # number of overall misses
-system.l2c.overall_misses::total                86093                       # number of overall misses
-system.l2c.overall_mshr_hits                     1468                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency       3384975754                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate::0         3.526482                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1         3.499359                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2         3.508645                       # mshr miss rate for overall accesses
@@ -930,15 +353,608 @@ system.l2c.overall_mshr_miss_rate::5         3.535765                       # ms
 system.l2c.overall_mshr_miss_rate::6         3.465823                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::7         3.523839                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total    28.111410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                  84625                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   4913043478                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                         76856                       # number of replacements
-system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
+system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  39999.713489                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 39999.713489                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                       657.714518                       # Cycle average of tags in use
-system.l2c.total_refs                          139150                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                           40644                       # number of writebacks
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cpu0.num_reads                           99815                       # number of read accesses completed
+system.cpu0.num_writes                          53929                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu0.l1c.replacements                    27826                       # number of replacements
+system.cpu0.l1c.tagsinuse                  102.742005                       # Cycle average of tags in use
+system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
+system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
+system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
+system.cpu0.l1c.occ_percent::0               0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::1              -0.477715                       # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits                     7530                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits                    1059                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits                      8589                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits                     8589                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses                  37279                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses                 23202                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses                   60481                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses                  60481                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency       1299667421                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency      1001508092                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency        2301175513                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency       2301175513                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses                44809                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses                 69070                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate            0.831953                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate           0.956350                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate             0.875648                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate            0.875648                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency  38047.907822                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu0.l1c.writebacks                      11972                       # number of writebacks
+system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu0.l1c.ReadReq_mshr_misses             37279                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses            23202                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses              60481                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses             60481                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency   1262244251                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency    978215253                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency   2240459504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency   2240459504                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    894578632                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    569723237                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency   1464301869                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831953                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956350                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate        0.875648                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate       0.875648                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu1.num_reads                           98493                       # number of read accesses completed
+system.cpu1.num_writes                          53671                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu1.l1c.replacements                    27684                       # number of replacements
+system.cpu1.l1c.tagsinuse                   93.018974                       # Cycle average of tags in use
+system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
+system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
+system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
+system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
+system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
+system.cpu1.l1c.occ_percent::0               0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::1              -0.493432                       # Average percentage of cache occupancy
+system.cpu1.l1c.ReadReq_hits                     7429                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits                    1066                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits                      8495                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits                     8495                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses                  37110                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses                 23275                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses                   60385                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses                  60385                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency       1301760811                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency      1014297005                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency        2316057816                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency       2316057816                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses                44539                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses               24341                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses                 68880                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate            0.833202                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate           0.956206                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate             0.876670                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate            0.876670                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency  38354.853291                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu1.l1c.writebacks                      11809                       # number of writebacks
+system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu1.l1c.ReadReq_mshr_misses             37110                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses            23275                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses              60385                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses             60385                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency   1264508347                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency    990933889                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency   2255442236                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency   2255442236                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    877119159                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    578327433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency   1455446592                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833202                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956206                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate        0.876670                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate       0.876670                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu2.num_reads                           99149                       # number of read accesses completed
+system.cpu2.num_writes                          53185                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu2.l1c.replacements                    27627                       # number of replacements
+system.cpu2.l1c.tagsinuse                   84.373112                       # Cycle average of tags in use
+system.cpu2.l1c.total_refs                      11519                       # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
+system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
+system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
+system.cpu2.l1c.occ_percent::0               0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::1              -0.509877                       # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits                     7576                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits                    1069                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits                      8645                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits                     8645                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses                  37144                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses                 22885                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses                   60029                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses                  60029                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency       1302790562                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency       991654869                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency        2294445431                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency       2294445431                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses                44720                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses               23954                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses                 68674                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate            0.830590                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate           0.955373                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate             0.874115                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate            0.874115                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency  38222.283080                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu2.l1c.writebacks                      11784                       # number of writebacks
+system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu2.l1c.ReadReq_mshr_misses             37144                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses            22885                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses              60029                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses             60029                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency   1265501937                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency    968684322                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency   2234186259                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency   2234186259                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    900513056                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    566349170                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency   1466862226                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830590                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate      0.955373                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate        0.874115                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate       0.874115                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu3.num_reads                           99588                       # number of read accesses completed
+system.cpu3.num_writes                          53645                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu3.l1c.replacements                    27837                       # number of replacements
+system.cpu3.l1c.tagsinuse                  104.177298                       # Cycle average of tags in use
+system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
+system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
+system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
+system.cpu3.l1c.occ_percent::0               0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::1              -0.475386                       # Average percentage of cache occupancy
+system.cpu3.l1c.ReadReq_hits                     7552                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits                    1078                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits                      8630                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits                     8630                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses                  37191                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses                 23219                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses                   60410                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses                  60410                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency       1312024933                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency       995527685                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency        2307552618                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency       2307552618                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses                44743                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses               24297                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses                 69040                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate            0.831214                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate           0.955632                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate             0.875000                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate            0.875000                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency  38198.189340                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu3.l1c.writebacks                      11956                       # number of writebacks
+system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu3.l1c.ReadReq_mshr_misses             37191                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses            23219                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses              60410                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses             60410                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency   1274692143                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency    972218785                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency   2246910928                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency   2246910928                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    889431937                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    569772276                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency   1459204213                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate       0.831214                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate      0.955632                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate        0.875000                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate       0.875000                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu4.num_reads                           99725                       # number of read accesses completed
+system.cpu4.num_writes                          53533                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu4.l1c.replacements                    27683                       # number of replacements
+system.cpu4.l1c.tagsinuse                   94.681644                       # Cycle average of tags in use
+system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
+system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
+system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
+system.cpu4.l1c.occ_percent::0               0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_percent::1              -0.494043                       # Average percentage of cache occupancy
+system.cpu4.l1c.ReadReq_hits                     7686                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits                    1123                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits                      8809                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits                     8809                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses                  37251                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses                 22937                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses                   60188                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses                  60188                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency       1303112178                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency       994450363                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency        2297562541                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency       2297562541                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses                44937                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses               24060                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate            0.828961                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate           0.953325                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate             0.872328                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate            0.872328                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency  38173.099970                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu4.l1c.writebacks                      11763                       # number of writebacks
+system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu4.l1c.ReadReq_mshr_misses             37251                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses            22937                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency   1265717116                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency    971425596                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency   2237142712                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency   2237142712                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    898461911                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    576408625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency   1474870536                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate       0.828961                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate      0.953325                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate        0.872328                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate       0.872328                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53710                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu5.l1c.replacements                    27832                       # number of replacements
+system.cpu5.l1c.tagsinuse                   93.507234                       # Cycle average of tags in use
+system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
+system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
+system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
+system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
+system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
+system.cpu5.l1c.occ_percent::0               0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::1              -0.494726                       # Average percentage of cache occupancy
+system.cpu5.l1c.ReadReq_hits                     7592                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits                    1126                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits                      8718                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits                     8718                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses                  37349                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses                 23013                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses                   60362                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses                  60362                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency       1291933371                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency       998304045                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency        2290237416                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency       2290237416                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses                44941                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses               24139                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses                 69080                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate            0.831067                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate           0.953353                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate             0.873798                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate            0.873798                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency  37941.708625                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu5.l1c.writebacks                      11908                       # number of writebacks
+system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu5.l1c.ReadReq_mshr_misses             37349                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses            23013                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses              60362                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses             60362                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency   1254436910                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency    975203983                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency   2229640893                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency   2229640893                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    902856034                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    567587171                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency   1470443205                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831067                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate      0.953353                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate        0.873798                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate       0.873798                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu6.num_reads                           99389                       # number of read accesses completed
+system.cpu6.num_writes                          53686                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu6.l1c.replacements                    27861                       # number of replacements
+system.cpu6.l1c.tagsinuse                   89.788098                       # Cycle average of tags in use
+system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
+system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
+system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
+system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
+system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
+system.cpu6.l1c.occ_percent::0               0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::1              -0.502932                       # Average percentage of cache occupancy
+system.cpu6.l1c.ReadReq_hits                     7543                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits                    1119                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits                      8662                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits                     8662                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses                  37109                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses                 23142                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses                   60251                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses                  60251                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency       1299799162                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency      1015775810                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency        2315574972                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency       2315574972                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses                44652                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses                 68913                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate            0.831071                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate           0.953877                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate             0.874305                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate            0.874305                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency  38432.141740                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu6.l1c.writebacks                      11849                       # number of writebacks
+system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu6.l1c.ReadReq_mshr_misses             37109                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses            23142                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses              60251                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses             60251                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency   1262548698                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency    992541214                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency   2255089912                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency   2255089912                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    877981455                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    574689009                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency   1452670464                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate       0.831071                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate      0.953877                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate        0.874305                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate       0.874305                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu7.num_reads                           99694                       # number of read accesses completed
+system.cpu7.num_writes                          53501                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+system.cpu7.l1c.replacements                    27727                       # number of replacements
+system.cpu7.l1c.tagsinuse                   84.250612                       # Cycle average of tags in use
+system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
+system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
+system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
+system.cpu7.l1c.occ_percent::0               0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::1              -0.511413                       # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits                     7593                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits                    1111                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits                      8704                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits                     8704                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses                  37155                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses                 23121                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses                   60276                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses                  60276                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency       1287127315                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency      1006139538                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency        2293266853                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency       2293266853                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses                44748                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses               24232                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses                 68980                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate            0.830316                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate           0.954152                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate             0.873818                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate            0.873818                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency  38046.102147                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu7.l1c.writebacks                      11797                       # number of writebacks
+system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu7.l1c.ReadReq_mshr_misses             37155                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses            23121                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses              60276                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses             60276                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency   1249829653                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency    982928032                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency   2232757685                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency   2232757685                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    901961636                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    558194703                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency   1460156339                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate       0.830316                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate      0.954152                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate        0.873818                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate       0.873818                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
index b84974628..ad26765cf 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -28,6 +31,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_mem_ctrl_latency=1
 transitions_per_cycle=32
 version=0
@@ -63,7 +67,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -73,7 +77,8 @@ l1_response_latency=2
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 to_l2_latency=1
 transitions_per_cycle=32
 version=0
@@ -81,6 +86,7 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -89,11 +95,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=system.tester.cpuPort[0]
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -104,6 +126,7 @@ l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 to_l1_latency=1
 transitions_per_cycle=32
 version=0
@@ -111,6 +134,7 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -124,35 +148,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=true
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -162,6 +169,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -248,10 +256,18 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
 [system.tester]
 type=RubyTester
@@ -259,5 +275,5 @@ check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
+cpuPort=system.l1_cntrl0.sequencer.port[0]
 
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 16ffd52a6..160177fb6 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:32:57
+Real time: Jan/23/2012 04:22:04
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 1.07
-Virtual_time_in_minutes: 0.0178333
-Virtual_time_in_hours:   0.000297222
-Virtual_time_in_days:    1.23843e-05
+Virtual_time_in_seconds: 0.63
+Virtual_time_in_minutes: 0.0105
+Virtual_time_in_hours:   0.000175
+Virtual_time_in_days:    7.29167e-06
 
 Ruby_current_time: 363611
 Ruby_start_time: 0
 Ruby_cycles: 363611
 
-mbytes_resident: 36.0352
-mbytes_total: 219.727
-resident_ratio: 0.164053
+mbytes_resident: 39.3828
+mbytes_total: 209.344
+resident_ratio: 0.188125
 
 ruby_cycles_executed: [ 363612 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10465
+page_reclaims: 10428
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
@@ -198,20 +198,27 @@ links_utilized_percent_switch_3: 1.80417
   outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 55
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 55
   system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   55    100%
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 865
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 865
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   4.50867%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   95.4913%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   865    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -326,12 +333,17 @@ SINK_WB_ACK  L1_Replacement [0 ] 0
 SINK_WB_ACK  WB_Ack [399 ] 399
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 0
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_misses: 883
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 883
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   4.30351%
+  system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   5.77576%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   89.9207%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   883    100%
 
  --- L2Cache ---
  - Event Counts -
@@ -625,4 +637,5 @@ M_DWRI  Fetch [0 ] 0
 M_DWRI  Data [0 ] 0
 M_DWRI  Memory_Ack [0 ] 0
 M_DWRI  DMA_READ [0 ] 0
-M_DWRI  DMA_WRITE
\ No newline at end of file
+M_DWRI  DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index e191e4fe3..bb1def18d 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:32:19
-M5 started Apr 28 2011 14:32:56
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:22:03
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 363611 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index 736578159..a412dab3a 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -1,10 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 225004                       # Number of bytes of host memory used
-host_seconds                                     0.76                       # Real time elapsed on the host
-host_tick_rate                                 480073                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000364                       # Number of seconds simulated
 sim_ticks                                      363611                       # Number of ticks simulated
+final_tick                                     363611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                 742759                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214372                       # Number of bytes of host memory used
+host_seconds                                     0.49                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index cbd638820..cc5b405b4 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -28,6 +31,7 @@ directory_latency=6
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -62,7 +66,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
@@ -71,13 +75,15 @@ l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -86,11 +92,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=system.tester.cpuPort[0]
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -101,12 +123,14 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 response_latency=2
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
 size=512
@@ -120,35 +144,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=true
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -158,6 +165,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -244,10 +252,18 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
 [system.tester]
 type=RubyTester
@@ -255,5 +271,5 @@ check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
+cpuPort=system.l1_cntrl0.sequencer.port[0]
 
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 5cf487608..9cbc6e028 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:49:15
+Real time: Jan/23/2012 04:22:16
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 1.04
-Virtual_time_in_minutes: 0.0173333
-Virtual_time_in_hours:   0.000288889
-Virtual_time_in_days:    1.2037e-05
+Virtual_time_in_seconds: 0.62
+Virtual_time_in_minutes: 0.0103333
+Virtual_time_in_hours:   0.000172222
+Virtual_time_in_days:    7.17593e-06
 
 Ruby_current_time: 371241
 Ruby_start_time: 0
 Ruby_cycles: 371241
 
-mbytes_resident: 36.1758
-mbytes_total: 219.98
-resident_ratio: 0.164503
+mbytes_resident: 39.6328
+mbytes_total: 209.516
+resident_ratio: 0.189164
 
 ruby_cycles_executed: [ 371242 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10488
+page_reclaims: 10451
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
@@ -1466,4 +1466,5 @@ MD  PUTO [0 ] 0
 MD  PUTO_SHARERS [0 ] 0
 MD  DMA_READ [0 ] 0
 MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK
\ No newline at end of file
+MD  DMA_ACK [0 ] 0
+
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 366ed5736..dfaf3cf5d 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:48:31
-M5 started Apr 28 2011 14:49:14
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:16
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 371241 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index e04547500..59e160c20 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,10 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 225264                       # Number of bytes of host memory used
-host_seconds                                     0.74                       # Real time elapsed on the host
-host_tick_rate                                 500630                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000371                       # Number of seconds simulated
 sim_ticks                                      371241                       # Number of ticks simulated
+final_tick                                     371241                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                 812201                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214548                       # Number of bytes of host memory used
+host_seconds                                     0.46                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 0b84aec81..753a30469 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -31,6 +34,7 @@ l2_select_num_bits=0
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -65,7 +69,7 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
+children=L1DcacheMemory L1IcacheMemory sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 N_tokens=2
@@ -80,13 +84,15 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
@@ -95,11 +101,27 @@ start_index_bit=6
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=system.tester.cpuPort[0]
+
 [system.l2_cntrl0]
 type=L2Cache_Controller
 children=L2cacheMemory
@@ -112,12 +134,14 @@ l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
 size=512
@@ -131,35 +155,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=true
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -169,6 +176,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -255,10 +263,18 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
 [system.tester]
 type=RubyTester
@@ -266,5 +282,5 @@ check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
+cpuPort=system.l1_cntrl0.sequencer.port[0]
 
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index 0f1221806..ef66b37d5 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 15:03:52
+Real time: Jan/23/2012 04:22:32
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.59
-Virtual_time_in_minutes: 0.00983333
-Virtual_time_in_hours:   0.000163889
-Virtual_time_in_days:    6.8287e-06
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours:   7.77778e-05
+Virtual_time_in_days:    3.24074e-06
 
 Ruby_current_time: 254811
 Ruby_start_time: 0
 Ruby_cycles: 254811
 
-mbytes_resident: 36.1211
-mbytes_total: 219.867
-resident_ratio: 0.164339
+mbytes_resident: 39.6562
+mbytes_total: 209.445
+resident_ratio: 0.189339
 
 ruby_cycles_executed: [ 254812 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10466
+page_reclaims: 10441
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
@@ -1045,4 +1045,5 @@ DR_L  Tokens [0 ] 0
 DR_L  Request_Timeout [0 ] 0
 DR_L  DMA_READ [0 ] 0
 DR_L  DMA_WRITE [0 ] 0
-DR_L  DMA_WRITE_All_Tokens
\ No newline at end of file
+DR_L  DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 837429f75..151753306 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:03:17
-M5 started Apr 28 2011 15:03:52
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:31
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 254811 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index e56ff9f07..35d3a3293 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,10 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 225148                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
-host_tick_rate                                1244529                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000255                       # Number of seconds simulated
 sim_ticks                                      254811                       # Number of ticks simulated
+final_tick                                     254811                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                1986774                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214476                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 510e558ad..3ae5a9266 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -144,11 +145,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -232,10 +233,16 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
 [system.tester]
 type=RubyTester
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 577ddb4ca..2e775c964 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/10/2012 12:44:12
+Real time: Jan/23/2012 04:21:49
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours:   6.94444e-05
+Virtual_time_in_days:    2.89352e-06
 
 Ruby_current_time: 213131
 Ruby_start_time: 0
 Ruby_cycles: 213131
 
-mbytes_resident: 35.9023
-mbytes_total: 232.609
-resident_ratio: 0.154396
+mbytes_resident: 39.2617
+mbytes_total: 209.207
+resident_ratio: 0.187669
 
 ruby_cycles_executed: [ 213132 ]
 
@@ -125,11 +125,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10130
+page_reclaims: 10363
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 61c2c4ddb..959553323 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 10 2012 12:41:45
-gem5 started Jan 10 2012 12:44:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 213131 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 902497bf0..e2e363d28 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -2,9 +2,16 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000213                       # Number of seconds simulated
 sim_ticks                                      213131                       # Number of ticks simulated
+final_tick                                     213131                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2251733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238196                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                2118201                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214232                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 4187ee062..e6be42bee 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -7,8 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -28,6 +31,7 @@ directory_latency=12
 memBuffer=system.dir_cntrl0.memBuffer
 number_of_TBEs=256
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -62,17 +66,43 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
+children=cacheMemory sequencer
 buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
 cache_response_latency=12
 cntrl_id=0
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=system.tester.cpuPort[0]
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -81,44 +111,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=true
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -128,6 +132,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -192,10 +197,18 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
-warmup_length=100000
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
 [system.tester]
 type=RubyTester
@@ -203,5 +216,5 @@ check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
+cpuPort=system.l1_cntrl0.sequencer.port[0]
 
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index 49a921880..7421fe4ce 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 14:31:22
+Real time: Jan/23/2012 04:59:28
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.36
-Virtual_time_in_minutes: 0.006
-Virtual_time_in_hours:   0.0001
-Virtual_time_in_days:    4.16667e-06
+Virtual_time_in_seconds: 0.22
+Virtual_time_in_minutes: 0.00366667
+Virtual_time_in_hours:   6.11111e-05
+Virtual_time_in_days:    2.5463e-06
 
 Ruby_current_time: 277351
 Ruby_start_time: 0
 Ruby_cycles: 277351
 
-mbytes_resident: 35.5195
-mbytes_total: 219.27
-resident_ratio: 0.162044
+mbytes_resident: 38.8945
+mbytes_total: 208.887
+resident_ratio: 0.186199
 
 ruby_cycles_executed: [ 277352 ]
 
@@ -122,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10312
+page_reclaims: 10335
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 72
 
 Network Stats
 -------------
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 1.69731
   outgoing_messages_switch_2_link_1_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 945
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 945
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+  system.l1_cntrl0.cacheMemory_total_misses: 945
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 945
+  system.l1_cntrl0.cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   4.33862%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   89.5238%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   6.13757%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   4.33862%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   89.5238%
+  system.l1_cntrl0.cacheMemory_request_type_IFETCH:   6.13757%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   945    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   945    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -307,4 +307,5 @@ ID_W  PUTX [0 ] 0
 ID_W  PUTX_NotOwner [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 563fb5cc8..c0a210974 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 14:26:41
-M5 started Apr 28 2011 14:31:22
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:28
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 277351 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 4776ac1eb..22332d2ed 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,10 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 224536                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                2428366                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000277                       # Number of seconds simulated
 sim_ticks                                      277351                       # Number of ticks simulated
+final_tick                                     277351                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                3834985                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213904                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index ea57eb23e..4bff39dc1 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -1,6 +1,6 @@
 [drivesys]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
+children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -8,9 +8,11 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
+memories=drivesys.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-server.rcS
+readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -21,20 +23,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=drivesys.membus.port[2]
 
 [drivesys.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=
-filter_ranges_b=
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=drivesys.iobus.port[0]
-side_b=drivesys.membus.port[0]
+master=drivesys.iobus.port[0]
+slave=drivesys.membus.port[0]
 
 [drivesys.cpu]
 type=AtomicSimpleCPU
@@ -64,8 +64,8 @@ simulate_inst_stalls=false
 system=drivesys
 tracer=drivesys.cpu.tracer
 width=1
-dcache_port=drivesys.membus.port[3]
-icache_port=drivesys.membus.port[2]
+dcache_port=drivesys.membus.port[4]
+icache_port=drivesys.membus.port[3]
 
 [drivesys.cpu.dtb]
 type=AlphaTLB
@@ -125,6 +125,17 @@ read_only=true
 type=IntrControl
 sys=drivesys
 
+[drivesys.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=0:8589934592
+req_size=16
+resp_size=16
+write_ack=false
+master=drivesys.membus.port[5]
+slave=drivesys.iobus.port[32]
+
 [drivesys.iobus]
 type=Bus
 block_size=64
@@ -134,7 +145,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=drivesys.tsunami.pciconfig.pio
-port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma
+port=drivesys.bridge.master drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.iobridge.slave
 
 [drivesys.membus]
 type=Bus
@@ -146,10 +157,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=drivesys.membus.badaddr_responder.pio
-port=drivesys.bridge.side_b drivesys.physmem.port[0] drivesys.cpu.icache_port drivesys.cpu.dcache_port
+port=drivesys.bridge.slave drivesys.physmem.port[0] drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
 
 [drivesys.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -285,13 +297,14 @@ system=drivesys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=drivesys.iobus.port[28]
-dma=drivesys.iobus.port[29]
+config=drivesys.iobus.port[30]
+dma=drivesys.iobus.port[31]
 interface=etherlink.int1
-pio=drivesys.iobus.port[27]
+pio=drivesys.iobus.port[29]
 
 [drivesys.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -308,6 +321,7 @@ pio=drivesys.iobus.port[9]
 
 [drivesys.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -324,6 +338,7 @@ pio=drivesys.iobus.port[20]
 
 [drivesys.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -340,6 +355,7 @@ pio=drivesys.iobus.port[21]
 
 [drivesys.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -356,6 +372,7 @@ pio=drivesys.iobus.port[10]
 
 [drivesys.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -372,6 +389,7 @@ pio=drivesys.iobus.port[12]
 
 [drivesys.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -388,6 +406,7 @@ pio=drivesys.iobus.port[13]
 
 [drivesys.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -404,6 +423,7 @@ pio=drivesys.iobus.port[14]
 
 [drivesys.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -420,6 +440,7 @@ pio=drivesys.iobus.port[15]
 
 [drivesys.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -436,6 +457,7 @@ pio=drivesys.iobus.port[16]
 
 [drivesys.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -452,6 +474,7 @@ pio=drivesys.iobus.port[17]
 
 [drivesys.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -468,6 +491,7 @@ pio=drivesys.iobus.port[18]
 
 [drivesys.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -484,6 +508,7 @@ pio=drivesys.iobus.port[19]
 
 [drivesys.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -500,6 +525,7 @@ pio=drivesys.iobus.port[11]
 
 [drivesys.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -516,6 +542,7 @@ pio=drivesys.iobus.port[8]
 
 [drivesys.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -532,6 +559,7 @@ pio=drivesys.iobus.port[3]
 
 [drivesys.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -548,6 +576,7 @@ pio=drivesys.iobus.port[4]
 
 [drivesys.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -564,6 +593,7 @@ pio=drivesys.iobus.port[5]
 
 [drivesys.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -580,6 +610,7 @@ pio=drivesys.iobus.port[6]
 
 [drivesys.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -655,8 +686,8 @@ pci_func=0
 pio_latency=1000
 platform=drivesys.tsunami
 system=drivesys
-config=drivesys.iobus.port[30]
-dma=drivesys.iobus.port[31]
+config=drivesys.iobus.port[27]
+dma=drivesys.iobus.port[28]
 pio=drivesys.iobus.port[26]
 
 [drivesys.tsunami.io]
@@ -721,7 +752,7 @@ time_sync_spin_threshold=100000000
 
 [testsys]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
+children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -729,9 +760,11 @@ init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
+memories=testsys.physmem
+num_work_ids=16
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-stream-client.rcS
+readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -742,20 +775,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=testsys.membus.port[2]
 
 [testsys.bridge]
 type=Bridge
 delay=50000
-filter_ranges_a=
-filter_ranges_b=
 nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
 write_ack=false
-side_a=testsys.iobus.port[0]
-side_b=testsys.membus.port[0]
+master=testsys.iobus.port[0]
+slave=testsys.membus.port[0]
 
 [testsys.cpu]
 type=AtomicSimpleCPU
@@ -785,8 +816,8 @@ simulate_inst_stalls=false
 system=testsys
 tracer=testsys.cpu.tracer
 width=1
-dcache_port=testsys.membus.port[3]
-icache_port=testsys.membus.port[2]
+dcache_port=testsys.membus.port[4]
+icache_port=testsys.membus.port[3]
 
 [testsys.cpu.dtb]
 type=AlphaTLB
@@ -846,6 +877,17 @@ read_only=true
 type=IntrControl
 sys=testsys
 
+[testsys.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=0:8589934592
+req_size=16
+resp_size=16
+write_ack=false
+master=testsys.membus.port[5]
+slave=testsys.iobus.port[32]
+
 [testsys.iobus]
 type=Bus
 block_size=64
@@ -855,7 +897,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=testsys.tsunami.pciconfig.pio
-port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma
+port=testsys.bridge.master testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ide.dma testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.iobridge.slave
 
 [testsys.membus]
 type=Bus
@@ -867,10 +909,11 @@ header_cycles=1
 use_default_range=false
 width=64
 default=testsys.membus.badaddr_responder.pio
-port=testsys.bridge.side_b testsys.physmem.port[0] testsys.cpu.icache_port testsys.cpu.dcache_port
+port=testsys.bridge.slave testsys.physmem.port[0] testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
 
 [testsys.membus.badaddr_responder]
 type=IsaFake
+fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
@@ -1006,13 +1049,14 @@ system=testsys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=testsys.iobus.port[28]
-dma=testsys.iobus.port[29]
+config=testsys.iobus.port[30]
+dma=testsys.iobus.port[31]
 interface=etherlink.int0
-pio=testsys.iobus.port[27]
+pio=testsys.iobus.port[29]
 
 [testsys.tsunami.fake_OROM]
 type=IsaFake
+fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
@@ -1029,6 +1073,7 @@ pio=testsys.iobus.port[9]
 
 [testsys.tsunami.fake_ata0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
@@ -1045,6 +1090,7 @@ pio=testsys.iobus.port[20]
 
 [testsys.tsunami.fake_ata1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
@@ -1061,6 +1107,7 @@ pio=testsys.iobus.port[21]
 
 [testsys.tsunami.fake_pnp_addr]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
@@ -1077,6 +1124,7 @@ pio=testsys.iobus.port[10]
 
 [testsys.tsunami.fake_pnp_read0]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
@@ -1093,6 +1141,7 @@ pio=testsys.iobus.port[12]
 
 [testsys.tsunami.fake_pnp_read1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
@@ -1109,6 +1158,7 @@ pio=testsys.iobus.port[13]
 
 [testsys.tsunami.fake_pnp_read2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
@@ -1125,6 +1175,7 @@ pio=testsys.iobus.port[14]
 
 [testsys.tsunami.fake_pnp_read3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
@@ -1141,6 +1192,7 @@ pio=testsys.iobus.port[15]
 
 [testsys.tsunami.fake_pnp_read4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
@@ -1157,6 +1209,7 @@ pio=testsys.iobus.port[16]
 
 [testsys.tsunami.fake_pnp_read5]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
@@ -1173,6 +1226,7 @@ pio=testsys.iobus.port[17]
 
 [testsys.tsunami.fake_pnp_read6]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
@@ -1189,6 +1243,7 @@ pio=testsys.iobus.port[18]
 
 [testsys.tsunami.fake_pnp_read7]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
@@ -1205,6 +1260,7 @@ pio=testsys.iobus.port[19]
 
 [testsys.tsunami.fake_pnp_write]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
@@ -1221,6 +1277,7 @@ pio=testsys.iobus.port[11]
 
 [testsys.tsunami.fake_ppc]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
@@ -1237,6 +1294,7 @@ pio=testsys.iobus.port[8]
 
 [testsys.tsunami.fake_sm_chip]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
@@ -1253,6 +1311,7 @@ pio=testsys.iobus.port[3]
 
 [testsys.tsunami.fake_uart1]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
@@ -1269,6 +1328,7 @@ pio=testsys.iobus.port[4]
 
 [testsys.tsunami.fake_uart2]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
@@ -1285,6 +1345,7 @@ pio=testsys.iobus.port[5]
 
 [testsys.tsunami.fake_uart3]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
@@ -1301,6 +1362,7 @@ pio=testsys.iobus.port[6]
 
 [testsys.tsunami.fake_uart4]
 type=IsaFake
+fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
@@ -1376,8 +1438,8 @@ pci_func=0
 pio_latency=1000
 platform=testsys.tsunami
 system=testsys
-config=testsys.iobus.port[30]
-dma=testsys.iobus.port[31]
+config=testsys.iobus.port[27]
+dma=testsys.iobus.port[28]
 pio=testsys.iobus.port[26]
 
 [testsys.tsunami.io]
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index d5294a000..7390a9ac7 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
@@ -1,11 +1,6 @@
 warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
 warn: Obsolete M5 ivlb instruction encountered.
-For more information see: http://www.m5sim.org/warn/fcbd217d
 hack: be nice to actually delete the event here
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index cd96bb2d7..d1174531e 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -1,15 +1,13 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:17:36
-M5 started Apr 19 2011 12:17:43
-M5 executing on maize
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 04:23:10
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
+      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index a57983503..c3a385a95 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -1,231 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.data_accesses                 401302                       # DTB accesses
-drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
-drivesys.cpu.dtb.data_hits                     624235                       # DTB hits
-drivesys.cpu.dtb.data_misses                      569                       # DTB misses
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.read_accesses                 268057                       # DTB read accesses
-drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
-drivesys.cpu.dtb.read_hits                     393500                       # DTB read hits
-drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
-drivesys.cpu.dtb.write_accesses                133245                       # DTB write accesses
-drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
-drivesys.cpu.dtb.write_hits                    230735                       # DTB write hits
-drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
-drivesys.cpu.idle_fraction                   0.999990                       # Percentage of idle cycles
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.fetch_accesses               1337980                       # ITB accesses
-drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
-drivesys.cpu.itb.fetch_hits                   1337786                       # ITB hits
-drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.kern.callpal::swpctx                  70      1.58%      1.58% # number of callpals executed
-drivesys.cpu.kern.callpal::tbi                      5      0.11%      1.69% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl                3654     82.24%     83.93% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                   359      8.08%     92.01% # number of callpals executed
-drivesys.cpu.kern.callpal::rdusp                    1      0.02%     92.03% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                    322      7.25%     99.28% # number of callpals executed
-drivesys.cpu.kern.callpal::callsys                 25      0.56%     99.84% # number of callpals executed
-drivesys.cpu.kern.callpal::imb                      7      0.16%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total                 4443                       # number of callpals executed
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.hwrei                     5483                       # number of hwrei instructions executed
-drivesys.cpu.kern.inst.quiesce                    215                       # number of quiesce instructions executed
-drivesys.cpu.kern.ipl_count::0                   1189     28.37%     28.37% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                    10      0.24%     28.61% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                   205      4.89%     33.50% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                  2787     66.50%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total               4191                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                    1189     45.85%     45.85% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                     10      0.39%     46.24% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                    205      7.91%     54.15% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                   1189     45.85%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total                2593                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0           199571043172    100.00%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21                  1620      0.00%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22                 17630      0.00%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31                300462      0.00%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total       199571362884                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.426624                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.mode_good::kernel               110                      
-drivesys.cpu.kern.mode_good::user                 107                      
-drivesys.cpu.kern.mode_good::idle                   3                      
-drivesys.cpu.kern.mode_switch::kernel             174                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user               107                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle               218                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch_good::kernel     0.632184                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     0.013761                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     1.645945                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel           263256      0.24%      0.24% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user            1278343      1.15%      1.39% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle          109686421     98.61%    100.00% # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                     70                       # number of times the context was actually changed
-drivesys.cpu.kern.syscall::2                        1      4.55%      4.55% # number of syscalls executed
-drivesys.cpu.kern.syscall::6                        3     13.64%     18.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::17                       2      9.09%     27.27% # number of syscalls executed
-drivesys.cpu.kern.syscall::97                       1      4.55%     31.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::99                       2      9.09%     40.91% # number of syscalls executed
-drivesys.cpu.kern.syscall::101                      2      9.09%     50.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::102                      3     13.64%     63.64% # number of syscalls executed
-drivesys.cpu.kern.syscall::104                      1      4.55%     68.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::105                      3     13.64%     81.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::106                      1      4.55%     86.36% # number of syscalls executed
-drivesys.cpu.kern.syscall::118                      2      9.09%     95.45% # number of syscalls executed
-drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
-drivesys.cpu.not_idle_fraction               0.000010                       # Percentage of non-idle cycles
-drivesys.cpu.numCycles                   199571362884                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.num_busy_cycles             1954747.881971                       # Number of busy cycles
-drivesys.cpu.num_conditional_control_insts       161093                       # number of instructions that are conditional controls
-drivesys.cpu.num_fp_alu_accesses                 1278                       # Number of float alu accesses
-drivesys.cpu.num_fp_insts                        1278                       # number of float instructions
-drivesys.cpu.num_fp_register_reads                694                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               698                       # number of times the floating registers were written
-drivesys.cpu.num_func_calls                    121650                       # number of times a function call or return occured
-drivesys.cpu.num_idle_cycles             199569408136.118042                       # Number of idle cycles
-drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
-drivesys.cpu.num_int_alu_accesses             1889973                       # Number of integer alu accesses
-drivesys.cpu.num_int_insts                    1889973                       # number of integer instructions
-drivesys.cpu.num_int_register_reads           2411030                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes          1442447                       # number of times the integer registers were written
-drivesys.cpu.num_load_insts                    394697                       # Number of load instructions
-drivesys.cpu.num_mem_refs                      625939                       # number of memory refs
-drivesys.cpu.num_store_insts                   231242                       # Number of store instructions
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.descDMAReads              4                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes           96                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.tsunami.ethernet.postedInterrupts           16                       # number of posts to CPU
-drivesys.tsunami.ethernet.postedRxDesc              6                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxIdle              4                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.rxBandwidth           38400                       # Receive Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
-drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
-drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
-drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
-drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
-drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.totBandwidth          70320                       # Total Bandwidth (bits/s)
-drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
-drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
-drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.totalTxIdle               4                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.txBandwidth           31920                       # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
-drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
-drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
-drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
-drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              269342091                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478340                       # Number of bytes of host memory used
-host_seconds                                     1.02                       # Real time elapsed on the host
-host_tick_rate                           197020377111                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
 sim_ticks                                200000789468                       # Number of ticks simulated
-testsys.cpu.dtb.data_accesses                  335402                       # DTB accesses
-testsys.cpu.dtb.data_acv                          161                       # DTB access violations
-testsys.cpu.dtb.data_hits                     1163288                       # DTB hits
-testsys.cpu.dtb.data_misses                      3815                       # DTB misses
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+final_tick                               4300236018046                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                              201516796                       # Simulator instruction rate (inst/s)
+host_tick_rate                           147427543497                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 479620                       # Number of bytes of host memory used
+host_seconds                                     1.36                       # Real time elapsed on the host
+sim_insts                                   273374833                       # Number of instructions simulated
+testsys.physmem.bytes_read                   19104208                       # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read              14257548                       # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written                 3887982                       # Number of bytes written to this memory
+testsys.physmem.num_reads                     4226224                       # Number of read requests responded to by this memory
+testsys.physmem.num_writes                     504418                       # Number of write requests responded to by this memory
+testsys.physmem.num_other                           0                       # Number of other requests responded to by this memory
+testsys.physmem.bw_read                      95520663                       # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read                 71287459                       # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write                     19439833                       # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total                    114960496                       # Total bandwidth to/from this memory (bytes/s)
+testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
 testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
 testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.read_accesses                  225414                       # DTB read accesses
-testsys.cpu.dtb.read_acv                           80                       # DTB read access violations
+testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
 testsys.cpu.dtb.read_hits                      658435                       # DTB read hits
 testsys.cpu.dtb.read_misses                      3287                       # DTB read misses
-testsys.cpu.dtb.write_accesses                 109988                       # DTB write accesses
-testsys.cpu.dtb.write_acv                          81                       # DTB write access violations
+testsys.cpu.dtb.read_acv                           80                       # DTB read access violations
+testsys.cpu.dtb.read_accesses                  225414                       # DTB read accesses
 testsys.cpu.dtb.write_hits                     504853                       # DTB write hits
 testsys.cpu.dtb.write_misses                      528                       # DTB write misses
-testsys.cpu.idle_fraction                    0.999982                       # Percentage of idle cycles
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.fetch_accesses                1249822                       # ITB accesses
-testsys.cpu.itb.fetch_acv                          69                       # ITB acv
+testsys.cpu.dtb.write_acv                          81                       # DTB write access violations
+testsys.cpu.dtb.write_accesses                 109988                       # DTB write accesses
+testsys.cpu.dtb.data_hits                     1163288                       # DTB hits
+testsys.cpu.dtb.data_misses                      3815                       # DTB misses
+testsys.cpu.dtb.data_acv                          161                       # DTB access violations
+testsys.cpu.dtb.data_accesses                  335402                       # DTB accesses
 testsys.cpu.itb.fetch_hits                    1248325                       # ITB hits
 testsys.cpu.itb.fetch_misses                     1497                       # ITB misses
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.fetch_acv                          69                       # ITB acv
+testsys.cpu.itb.fetch_accesses                1249822                       # ITB accesses
 testsys.cpu.itb.read_hits                           0                       # DTB read hits
 testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
 testsys.cpu.itb.write_hits                          0                       # DTB write hits
 testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.kern.callpal::swpctx                  438      3.34%      3.34% # number of callpals executed
-testsys.cpu.kern.callpal::tbi                      20      0.15%      3.49% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl                11074     84.39%     87.88% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                    359      2.74%     90.62% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp                     3      0.02%     90.64% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp                     3      0.02%     90.66% # number of callpals executed
-testsys.cpu.kern.callpal::rti                    1041      7.93%     98.60% # number of callpals executed
-testsys.cpu.kern.callpal::callsys                 140      1.07%     99.66% # number of callpals executed
-testsys.cpu.kern.callpal::imb                      44      0.34%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                 13122                       # number of callpals executed
+testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.itb.data_hits                           0                       # DTB hits
+testsys.cpu.itb.data_misses                         0                       # DTB misses
+testsys.cpu.itb.data_acv                            0                       # DTB access violations
+testsys.cpu.itb.data_accesses                       0                       # DTB accesses
+testsys.cpu.numCycles                    199569460393                       # number of cpu cycles simulated
+testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
+testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.num_insts                         3560411                       # Number of instructions executed
+testsys.cpu.num_int_alu_accesses              3348322                       # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
+testsys.cpu.num_func_calls                     107994                       # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts       361828                       # number of instructions that are conditional controls
+testsys.cpu.num_int_insts                     3348322                       # number of integer instructions
+testsys.cpu.num_fp_insts                        17380                       # number of float instructions
+testsys.cpu.num_int_register_reads            4592571                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes           2442795                       # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
+testsys.cpu.num_mem_refs                      1173234                       # number of memory refs
+testsys.cpu.num_load_insts                     666253                       # Number of load instructions
+testsys.cpu.num_store_insts                    506981                       # Number of store instructions
+testsys.cpu.num_idle_cycles              199565902130.465698                       # Number of idle cycles
+testsys.cpu.num_busy_cycles              3558262.534294                       # Number of busy cycles
+testsys.cpu.not_idle_fraction                0.000018                       # Percentage of non-idle cycles
+testsys.cpu.idle_fraction                    0.999982                       # Percentage of idle cycles
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.hwrei                     19053                       # number of hwrei instructions executed
 testsys.cpu.kern.inst.quiesce                     376                       # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei                     19053                       # number of hwrei instructions executed
 testsys.cpu.kern.ipl_count::0                    5061     40.48%     40.48% # number of times we switched to this ipl
 testsys.cpu.kern.ipl_count::21                    184      1.47%     41.95% # number of times we switched to this ipl
 testsys.cpu.kern.ipl_count::22                    205      1.64%     43.59% # number of times we switched to this ipl
@@ -245,20 +106,6 @@ testsys.cpu.kern.ipl_used::0                 0.998814                       # fr
 testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 testsys.cpu.kern.ipl_used::31                0.716615                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.mode_good::kernel                654                      
-testsys.cpu.kern.mode_good::user                  649                      
-testsys.cpu.kern.mode_good::idle                    5                      
-testsys.cpu.kern.mode_switch::kernel             1099                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                649                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle                381                       # number of protection mode switches
-testsys.cpu.kern.mode_switch_good::kernel     0.595086                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle      0.013123                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total     1.608210                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel           1821131      2.10%      2.10% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user             1065606      1.23%      3.32% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle            83963628     96.68%    100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
 testsys.cpu.kern.syscall::2                         3      3.61%      3.61% # number of syscalls executed
 testsys.cpu.kern.syscall::3                         7      8.43%     12.05% # number of syscalls executed
 testsys.cpu.kern.syscall::4                         1      1.20%     13.25% # number of syscalls executed
@@ -281,254 +128,354 @@ testsys.cpu.kern.syscall::104                       1      1.20%     93.98% # nu
 testsys.cpu.kern.syscall::105                       3      3.61%     97.59% # number of syscalls executed
 testsys.cpu.kern.syscall::118                       2      2.41%    100.00% # number of syscalls executed
 testsys.cpu.kern.syscall::total                    83                       # number of syscalls executed
-testsys.cpu.not_idle_fraction                0.000018                       # Percentage of non-idle cycles
-testsys.cpu.numCycles                    199569460393                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.num_busy_cycles              3558262.534294                       # Number of busy cycles
-testsys.cpu.num_conditional_control_insts       361828                       # number of instructions that are conditional controls
-testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
-testsys.cpu.num_fp_insts                        17380                       # number of float instructions
-testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
-testsys.cpu.num_func_calls                     107994                       # number of times a function call or return occured
-testsys.cpu.num_idle_cycles              199565902130.465698                       # Number of idle cycles
-testsys.cpu.num_insts                         3560411                       # Number of instructions executed
-testsys.cpu.num_int_alu_accesses              3348322                       # Number of integer alu accesses
-testsys.cpu.num_int_insts                     3348322                       # number of integer instructions
-testsys.cpu.num_int_register_reads            4592571                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes           2442795                       # number of times the integer registers were written
-testsys.cpu.num_load_insts                     666253                       # Number of load instructions
-testsys.cpu.num_mem_refs                      1173234                       # number of memory refs
-testsys.cpu.num_store_insts                    506981                       # Number of store instructions
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.descDMAReads               6                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites             13                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes          144                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.tsunami.ethernet.postedInterrupts           15                       # number of posts to CPU
-testsys.tsunami.ethernet.postedRxDesc               4                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxIdle               6                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.rxBandwidth            31920                       # Receive Bandwidth (bits/s)
+testsys.cpu.kern.callpal::swpctx                  438      3.34%      3.34% # number of callpals executed
+testsys.cpu.kern.callpal::tbi                      20      0.15%      3.49% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl                11074     84.39%     87.88% # number of callpals executed
+testsys.cpu.kern.callpal::rdps                    359      2.74%     90.62% # number of callpals executed
+testsys.cpu.kern.callpal::wrusp                     3      0.02%     90.64% # number of callpals executed
+testsys.cpu.kern.callpal::rdusp                     3      0.02%     90.66% # number of callpals executed
+testsys.cpu.kern.callpal::rti                    1041      7.93%     98.60% # number of callpals executed
+testsys.cpu.kern.callpal::callsys                 140      1.07%     99.66% # number of callpals executed
+testsys.cpu.kern.callpal::imb                      44      0.34%    100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total                 13122                       # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel             1099                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::user                649                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle                381                       # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel                654                      
+testsys.cpu.kern.mode_good::user                  649                      
+testsys.cpu.kern.mode_good::idle                    5                      
+testsys.cpu.kern.mode_switch_good::kernel     0.595086                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle      0.013123                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total     1.608210                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel           1821131      2.10%      2.10% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user             1065606      1.23%      3.32% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle            83963628     96.68%    100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
+testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
 testsys.tsunami.ethernet.rxBytes                  798                       # Bytes Received
-testsys.tsunami.ethernet.rxIpChecksums              5                       # Number of rx IP Checksums done by device
-testsys.tsunami.ethernet.rxPPS                     25                       # Packet Reception Rate (packets/s)
+testsys.tsunami.ethernet.txPackets                  8                       # Number of Packets Transmitted
 testsys.tsunami.ethernet.rxPackets                  5                       # Number of Packets Received
-testsys.tsunami.ethernet.rxTcpChecksums             5                       # Number of rx TCP Checksums done by device
-testsys.tsunami.ethernet.rxUdpChecksums             0                       # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.totBandwidth           70320                       # Total Bandwidth (bits/s)
-testsys.tsunami.ethernet.totBytes                1758                       # Total Bytes
-testsys.tsunami.ethernet.totPPS                    65                       # Total Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.totPackets                13                       # Total Packets
-testsys.tsunami.ethernet.totalRxDesc                5                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.totalTxIdle                6                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.txBandwidth            38400                       # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
 testsys.tsunami.ethernet.txIpChecksums              2                       # Number of tx IP Checksums done by device
-testsys.tsunami.ethernet.txPPS                     40                       # Packet Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txPackets                  8                       # Number of Packets Transmitted
+testsys.tsunami.ethernet.rxIpChecksums              5                       # Number of rx IP Checksums done by device
 testsys.tsunami.ethernet.txTcpChecksums             2                       # Number of tx TCP Checksums done by device
+testsys.tsunami.ethernet.rxTcpChecksums             5                       # Number of rx TCP Checksums done by device
 testsys.tsunami.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-
----------- End Simulation Statistics   ----------
-
----------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.dtb.data_acv                           0                       # DTB access violations
-drivesys.cpu.dtb.data_hits                          0                       # DTB hits
-drivesys.cpu.dtb.data_misses                        0                       # DTB misses
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.dtb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.dtb.read_hits                          0                       # DTB read hits
-drivesys.cpu.dtb.read_misses                        0                       # DTB read misses
-drivesys.cpu.dtb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.dtb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.dtb.write_hits                         0                       # DTB write hits
-drivesys.cpu.dtb.write_misses                       0                       # DTB write misses
-drivesys.cpu.idle_fraction                          1                       # Percentage of idle cycles
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.itb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.itb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.itb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.hwrei                        0                       # number of hwrei instructions executed
-drivesys.cpu.kern.inst.quiesce                      0                       # number of quiesce instructions executed
-drivesys.cpu.kern.mode_good::kernel                 0                      
-drivesys.cpu.kern.mode_good::user                   0                      
-drivesys.cpu.kern.mode_good::idle                   0                      
-drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle                 0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch_good::kernel     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
-drivesys.cpu.not_idle_fraction                      0                       # Percentage of non-idle cycles
-drivesys.cpu.numCycles                              0                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.num_busy_cycles                        0                       # Number of busy cycles
-drivesys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
-drivesys.cpu.num_fp_insts                           0                       # number of float instructions
-drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
-drivesys.cpu.num_func_calls                         0                       # number of times a function call or return occured
-drivesys.cpu.num_idle_cycles                        0                       # Number of idle cycles
-drivesys.cpu.num_insts                              0                       # Number of instructions executed
-drivesys.cpu.num_int_alu_accesses                   0                       # Number of integer alu accesses
-drivesys.cpu.num_int_insts                          0                       # number of integer instructions
-drivesys.cpu.num_int_register_reads                 0                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes                0                       # number of times the integer registers were written
-drivesys.cpu.num_load_insts                         0                       # Number of load instructions
-drivesys.cpu.num_mem_refs                           0                       # number of memory refs
-drivesys.cpu.num_store_insts                        0                       # Number of store instructions
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.tsunami.ethernet.rxUdpChecksums             0                       # Number of rx UDP Checksums done by device
+testsys.tsunami.ethernet.descDMAReads               6                       # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites             13                       # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes          144                       # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.totBandwidth           70320                       # Total Bandwidth (bits/s)
+testsys.tsunami.ethernet.totPackets                13                       # Total Packets
+testsys.tsunami.ethernet.totBytes                1758                       # Total Bytes
+testsys.tsunami.ethernet.totPPS                    65                       # Total Tranmission Rate (packets/s)
+testsys.tsunami.ethernet.txBandwidth            38400                       # Transmit Bandwidth (bits/s)
+testsys.tsunami.ethernet.rxBandwidth            31920                       # Receive Bandwidth (bits/s)
+testsys.tsunami.ethernet.txPPS                     40                       # Packet Tranmission Rate (packets/s)
+testsys.tsunami.ethernet.rxPPS                     25                       # Packet Reception Rate (packets/s)
+testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+testsys.tsunami.ethernet.postedRxDesc               4                       # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalRxDesc                5                       # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+testsys.tsunami.ethernet.postedTxIdle               6                       # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalTxIdle                6                       # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.postedInterrupts           15                       # number of posts to CPU
+testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
+drivesys.physmem.bytes_read                  10620314                       # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read              7834952                       # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written                1607724                       # Number of bytes written to this memory
+drivesys.physmem.num_reads                    2352907                       # Number of read requests responded to by this memory
+drivesys.physmem.num_writes                    230617                       # Number of write requests responded to by this memory
+drivesys.physmem.num_other                          0                       # Number of other requests responded to by this memory
+drivesys.physmem.bw_read                     53101360                       # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read                39174605                       # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write                     8038588                       # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total                    61139949                       # Total bandwidth to/from this memory (bytes/s)
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOk      no_value                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOrn     no_value                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.coalescedSwi       no_value                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTotal     no_value                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxOk      no_value                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.descDMAReads              0                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-drivesys.tsunami.ethernet.postedRxDesc              0                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
+drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
+drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.dtb.read_hits                     393500                       # DTB read hits
+drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
+drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
+drivesys.cpu.dtb.read_accesses                 268057                       # DTB read accesses
+drivesys.cpu.dtb.write_hits                    230735                       # DTB write hits
+drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
+drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
+drivesys.cpu.dtb.write_accesses                133245                       # DTB write accesses
+drivesys.cpu.dtb.data_hits                     624235                       # DTB hits
+drivesys.cpu.dtb.data_misses                      569                       # DTB misses
+drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
+drivesys.cpu.dtb.data_accesses                 401302                       # DTB accesses
+drivesys.cpu.itb.fetch_hits                   1337786                       # ITB hits
+drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
+drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
+drivesys.cpu.itb.fetch_accesses               1337980                       # ITB accesses
+drivesys.cpu.itb.read_hits                          0                       # DTB read hits
+drivesys.cpu.itb.read_misses                        0                       # DTB read misses
+drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.itb.write_hits                         0                       # DTB write hits
+drivesys.cpu.itb.write_misses                       0                       # DTB write misses
+drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.itb.data_hits                          0                       # DTB hits
+drivesys.cpu.itb.data_misses                        0                       # DTB misses
+drivesys.cpu.itb.data_acv                           0                       # DTB access violations
+drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.numCycles                   199571362884                       # number of cpu cycles simulated
+drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
+drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
+drivesys.cpu.num_int_alu_accesses             1889973                       # Number of integer alu accesses
+drivesys.cpu.num_fp_alu_accesses                 1278                       # Number of float alu accesses
+drivesys.cpu.num_func_calls                    121650                       # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts       161093                       # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts                    1889973                       # number of integer instructions
+drivesys.cpu.num_fp_insts                        1278                       # number of float instructions
+drivesys.cpu.num_int_register_reads           2411030                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes          1442447                       # number of times the integer registers were written
+drivesys.cpu.num_fp_register_reads                694                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes               698                       # number of times the floating registers were written
+drivesys.cpu.num_mem_refs                      625939                       # number of memory refs
+drivesys.cpu.num_load_insts                    394697                       # Number of load instructions
+drivesys.cpu.num_store_insts                   231242                       # Number of store instructions
+drivesys.cpu.num_idle_cycles             199569408136.118042                       # Number of idle cycles
+drivesys.cpu.num_busy_cycles             1954747.881971                       # Number of busy cycles
+drivesys.cpu.not_idle_fraction               0.000010                       # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction                   0.999990                       # Percentage of idle cycles
+drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
+drivesys.cpu.kern.inst.quiesce                    215                       # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei                     5483                       # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0                   1189     28.37%     28.37% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21                    10      0.24%     28.61% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::22                   205      4.89%     33.50% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::31                  2787     66.50%    100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total               4191                       # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0                    1189     45.85%     45.85% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21                     10      0.39%     46.24% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::22                    205      7.91%     54.15% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::31                   1189     45.85%    100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total                2593                       # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0           199571043172    100.00%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21                  1620      0.00%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::22                 17630      0.00%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31                300462      0.00%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total       199571362884                       # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31               0.426624                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.syscall::2                        1      4.55%      4.55% # number of syscalls executed
+drivesys.cpu.kern.syscall::6                        3     13.64%     18.18% # number of syscalls executed
+drivesys.cpu.kern.syscall::17                       2      9.09%     27.27% # number of syscalls executed
+drivesys.cpu.kern.syscall::97                       1      4.55%     31.82% # number of syscalls executed
+drivesys.cpu.kern.syscall::99                       2      9.09%     40.91% # number of syscalls executed
+drivesys.cpu.kern.syscall::101                      2      9.09%     50.00% # number of syscalls executed
+drivesys.cpu.kern.syscall::102                      3     13.64%     63.64% # number of syscalls executed
+drivesys.cpu.kern.syscall::104                      1      4.55%     68.18% # number of syscalls executed
+drivesys.cpu.kern.syscall::105                      3     13.64%     81.82% # number of syscalls executed
+drivesys.cpu.kern.syscall::106                      1      4.55%     86.36% # number of syscalls executed
+drivesys.cpu.kern.syscall::118                      2      9.09%     95.45% # number of syscalls executed
+drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # number of syscalls executed
+drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
+drivesys.cpu.kern.callpal::swpctx                  70      1.58%      1.58% # number of callpals executed
+drivesys.cpu.kern.callpal::tbi                      5      0.11%      1.69% # number of callpals executed
+drivesys.cpu.kern.callpal::swpipl                3654     82.24%     83.93% # number of callpals executed
+drivesys.cpu.kern.callpal::rdps                   359      8.08%     92.01% # number of callpals executed
+drivesys.cpu.kern.callpal::rdusp                    1      0.02%     92.03% # number of callpals executed
+drivesys.cpu.kern.callpal::rti                    322      7.25%     99.28% # number of callpals executed
+drivesys.cpu.kern.callpal::callsys                 25      0.56%     99.84% # number of callpals executed
+drivesys.cpu.kern.callpal::imb                      7      0.16%    100.00% # number of callpals executed
+drivesys.cpu.kern.callpal::total                 4443                       # number of callpals executed
+drivesys.cpu.kern.mode_switch::kernel             174                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::user               107                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle               218                       # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel               110                      
+drivesys.cpu.kern.mode_good::user                 107                      
+drivesys.cpu.kern.mode_good::idle                   3                      
+drivesys.cpu.kern.mode_switch_good::kernel     0.632184                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::idle     0.013761                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total     1.645945                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel           263256      0.24%      0.24% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user            1278343      1.15%      1.39% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle          109686421     98.61%    100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context                     70                       # number of times the context was actually changed
+drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
+drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
+drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
+drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
+drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
+drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
+drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
+drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
+drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
+drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
+drivesys.tsunami.ethernet.descDMAReads              4                       # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes           96                       # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
+drivesys.tsunami.ethernet.totBandwidth          70320                       # Total Bandwidth (bits/s)
+drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
+drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
+drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
+drivesys.tsunami.ethernet.txBandwidth           31920                       # Transmit Bandwidth (bits/s)
+drivesys.tsunami.ethernet.rxBandwidth           38400                       # Receive Bandwidth (bits/s)
+drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
+drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
 drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxIdle              0                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.totalRxDesc               0                       # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
+drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
 drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
+drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
 drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedRxDesc              6                       # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           178043202572                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478340                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              482553899                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   273374833                       # Number of instructions simulated
+drivesys.tsunami.ethernet.postedTxIdle              4                       # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalTxIdle               4                       # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
+drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
+drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.postedInterrupts           16                       # number of posts to CPU
+drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
+
+---------- End Simulation Statistics   ----------
+
+---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000001                       # Number of seconds simulated
 sim_ticks                                      785978                       # Number of ticks simulated
-testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
-testsys.cpu.dtb.data_acv                            0                       # DTB access violations
-testsys.cpu.dtb.data_hits                           0                       # DTB hits
-testsys.cpu.dtb.data_misses                         0                       # DTB misses
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+final_tick                               4300236804024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                           864513825905                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2363296319                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 479620                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
+sim_insts                                   273374833                       # Number of instructions simulated
+testsys.physmem.bytes_read                          0                       # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read                     0                       # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written                       0                       # Number of bytes written to this memory
+testsys.physmem.num_reads                           0                       # Number of read requests responded to by this memory
+testsys.physmem.num_writes                          0                       # Number of write requests responded to by this memory
+testsys.physmem.num_other                           0                       # Number of other requests responded to by this memory
+testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
 testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
 testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
+testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
 testsys.cpu.dtb.read_hits                           0                       # DTB read hits
 testsys.cpu.dtb.read_misses                         0                       # DTB read misses
-testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
+testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
+testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
 testsys.cpu.dtb.write_hits                          0                       # DTB write hits
 testsys.cpu.dtb.write_misses                        0                       # DTB write misses
-testsys.cpu.idle_fraction                           1                       # Percentage of idle cycles
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.itb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
+testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.dtb.data_hits                           0                       # DTB hits
+testsys.cpu.dtb.data_misses                         0                       # DTB misses
+testsys.cpu.dtb.data_acv                            0                       # DTB access violations
+testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
 testsys.cpu.itb.fetch_hits                          0                       # ITB hits
 testsys.cpu.itb.fetch_misses                        0                       # ITB misses
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.fetch_acv                           0                       # ITB acv
+testsys.cpu.itb.fetch_accesses                      0                       # ITB accesses
 testsys.cpu.itb.read_hits                           0                       # DTB read hits
 testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
 testsys.cpu.itb.write_hits                          0                       # DTB write hits
 testsys.cpu.itb.write_misses                        0                       # DTB write misses
+testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.itb.data_hits                           0                       # DTB hits
+testsys.cpu.itb.data_misses                         0                       # DTB misses
+testsys.cpu.itb.data_acv                            0                       # DTB access violations
+testsys.cpu.itb.data_accesses                       0                       # DTB accesses
+testsys.cpu.numCycles                               0                       # number of cpu cycles simulated
+testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
+testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.num_insts                               0                       # Number of instructions executed
+testsys.cpu.num_int_alu_accesses                    0                       # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
+testsys.cpu.num_func_calls                          0                       # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+testsys.cpu.num_int_insts                           0                       # number of integer instructions
+testsys.cpu.num_fp_insts                            0                       # number of float instructions
+testsys.cpu.num_int_register_reads                  0                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes                 0                       # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
+testsys.cpu.num_mem_refs                            0                       # number of memory refs
+testsys.cpu.num_load_insts                          0                       # Number of load instructions
+testsys.cpu.num_store_insts                         0                       # Number of store instructions
+testsys.cpu.num_idle_cycles                         0                       # Number of idle cycles
+testsys.cpu.num_busy_cycles                         0                       # Number of busy cycles
+testsys.cpu.not_idle_fraction                       0                       # Percentage of non-idle cycles
+testsys.cpu.idle_fraction                           1                       # Percentage of idle cycles
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.hwrei                         0                       # number of hwrei instructions executed
 testsys.cpu.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-testsys.cpu.kern.mode_good::kernel                  0                      
-testsys.cpu.kern.mode_good::user                    0                      
-testsys.cpu.kern.mode_good::idle                    0                      
+testsys.cpu.kern.inst.hwrei                         0                       # number of hwrei instructions executed
 testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
 testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
 testsys.cpu.kern.mode_switch::idle                  0                       # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel                  0                      
+testsys.cpu.kern.mode_good::user                    0                      
+testsys.cpu.kern.mode_good::idle                    0                      
 testsys.cpu.kern.mode_switch_good::kernel     no_value                       # fraction of useful protection mode switches
 testsys.cpu.kern.mode_switch_good::user      no_value                       # fraction of useful protection mode switches
 testsys.cpu.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
@@ -537,68 +484,155 @@ testsys.cpu.kern.mode_ticks::kernel                 0                       # nu
 testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
-testsys.cpu.not_idle_fraction                       0                       # Percentage of non-idle cycles
-testsys.cpu.numCycles                               0                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.num_busy_cycles                         0                       # Number of busy cycles
-testsys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
-testsys.cpu.num_fp_insts                            0                       # number of float instructions
-testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
-testsys.cpu.num_func_calls                          0                       # number of times a function call or return occured
-testsys.cpu.num_idle_cycles                         0                       # Number of idle cycles
-testsys.cpu.num_insts                               0                       # Number of instructions executed
-testsys.cpu.num_int_alu_accesses                    0                       # Number of integer alu accesses
-testsys.cpu.num_int_insts                           0                       # number of integer instructions
-testsys.cpu.num_int_register_reads                  0                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes                 0                       # number of times the integer registers were written
-testsys.cpu.num_load_insts                          0                       # Number of load instructions
-testsys.cpu.num_mem_refs                            0                       # number of memory refs
-testsys.cpu.num_store_insts                         0                       # Number of store instructions
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOk       no_value                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOrn      no_value                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.coalescedSwi        no_value                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.coalescedTotal      no_value                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxOk       no_value                       # average number of TxOk's coalesced into each post
 testsys.tsunami.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 testsys.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
 testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.coalescedSwi        no_value                       # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
 testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxOk       no_value                       # average number of RxOk's coalesced into each post
 testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxOk       no_value                       # average number of TxOk's coalesced into each post
 testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+testsys.tsunami.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.coalescedRxOrn      no_value                       # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.coalescedTotal      no_value                       # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
+drivesys.physmem.bytes_read                         0                       # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read                    0                       # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written                      0                       # Number of bytes written to this memory
+drivesys.physmem.num_reads                          0                       # Number of read requests responded to by this memory
+drivesys.physmem.num_writes                         0                       # Number of write requests responded to by this memory
+drivesys.physmem.num_other                          0                       # Number of other requests responded to by this memory
+drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
+drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.dtb.read_hits                          0                       # DTB read hits
+drivesys.cpu.dtb.read_misses                        0                       # DTB read misses
+drivesys.cpu.dtb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.dtb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.dtb.write_hits                         0                       # DTB write hits
+drivesys.cpu.dtb.write_misses                       0                       # DTB write misses
+drivesys.cpu.dtb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.dtb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.dtb.data_hits                          0                       # DTB hits
+drivesys.cpu.dtb.data_misses                        0                       # DTB misses
+drivesys.cpu.dtb.data_acv                           0                       # DTB access violations
+drivesys.cpu.dtb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.itb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.itb.fetch_misses                       0                       # ITB misses
+drivesys.cpu.itb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.itb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.itb.read_hits                          0                       # DTB read hits
+drivesys.cpu.itb.read_misses                        0                       # DTB read misses
+drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.itb.write_hits                         0                       # DTB write hits
+drivesys.cpu.itb.write_misses                       0                       # DTB write misses
+drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.itb.data_hits                          0                       # DTB hits
+drivesys.cpu.itb.data_misses                        0                       # DTB misses
+drivesys.cpu.itb.data_acv                           0                       # DTB access violations
+drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.numCycles                              0                       # number of cpu cycles simulated
+drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
+drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.num_insts                              0                       # Number of instructions executed
+drivesys.cpu.num_int_alu_accesses                   0                       # Number of integer alu accesses
+drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
+drivesys.cpu.num_func_calls                         0                       # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts                          0                       # number of integer instructions
+drivesys.cpu.num_fp_insts                           0                       # number of float instructions
+drivesys.cpu.num_int_register_reads                 0                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes                0                       # number of times the integer registers were written
+drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
+drivesys.cpu.num_mem_refs                           0                       # number of memory refs
+drivesys.cpu.num_load_insts                         0                       # Number of load instructions
+drivesys.cpu.num_store_insts                        0                       # Number of store instructions
+drivesys.cpu.num_idle_cycles                        0                       # Number of idle cycles
+drivesys.cpu.num_busy_cycles                        0                       # Number of busy cycles
+drivesys.cpu.not_idle_fraction                      0                       # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction                          1                       # Percentage of idle cycles
+drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
+drivesys.cpu.kern.inst.quiesce                      0                       # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei                        0                       # number of hwrei instructions executed
+drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle                 0                       # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel                 0                      
+drivesys.cpu.kern.mode_good::user                   0                      
+drivesys.cpu.kern.mode_good::idle                   0                      
+drivesys.cpu.kern.mode_switch_good::kernel     no_value                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::user     no_value                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::idle     no_value                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
+drivesys.tsunami.ethernet.descDMAReads              0                       # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedSwi       no_value                       # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
+drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxIdle     no_value                       # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
+drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOk      no_value                       # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
+drivesys.tsunami.ethernet.postedRxDesc              0                       # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxDesc     no_value                       # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalRxDesc               0                       # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxOk      no_value                       # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
+drivesys.tsunami.ethernet.postedTxIdle              0                       # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxIdle     no_value                       # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxDesc     no_value                       # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
+drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOrn     no_value                       # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
+drivesys.tsunami.ethernet.coalescedTotal     no_value                       # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
-- 
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